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GET /api/patches/44501/?format=api
{ "id": 44501, "url": "http://patches.dpdk.org/api/patches/44501/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536572016-18134-31-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536572016-18134-31-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536572016-18134-31-git-send-email-arybchenko@solarflare.com", "date": "2018-09-10T09:33:29", "name": "[30/37] net/sfc/base: add support to get active FEC type", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "1a0a287fba5e78d9d4d6fab2a766f65c8947b5f0", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536572016-18134-31-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 1244, "url": "http://patches.dpdk.org/api/series/1244/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1244", "date": "2018-09-10T09:33:01", "name": "net/sfc: update base driver", "version": 1, "mbox": "http://patches.dpdk.org/series/1244/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44501/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/44501/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EB2AA1B009;\n\tMon, 10 Sep 2018 11:34:45 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 1A69F4CA1\n\tfor <dev@dpdk.org>; Mon, 10 Sep 2018 11:33:55 +0200 (CEST)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\t665B0780055 for <dev@dpdk.org>; Mon, 10 Sep 2018 09:33:54 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1395.4; Mon, 10 Sep 2018 02:33:48 -0700", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1395.4 via Frontend Transport; Mon, 10 Sep 2018 02:33:48 -0700", "from ukv-loginhost.uk.solarflarecom.com\n\t(ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw8A9XlJJ023870; Mon, 10 Sep 2018 10:33:47 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n\tby ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id\n\tE3ECF1626D1; Mon, 10 Sep 2018 10:33:46 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Vijay Srivastava <vijays@solarflare.com>", "Date": "Mon, 10 Sep 2018 10:33:29 +0100", "Message-ID": "<1536572016-18134-31-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1536572016-18134-1-git-send-email-arybchenko@solarflare.com>", "References": "<1536572016-18134-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.5.1010-24084.005", "X-TM-AS-Result": "No-0.063800-4.000000-10", "X-TMASE-MatchedRID": "jW2Old1ajwBf2oN5IGbAjgPZZctd3P4BWjWsWQUWzVoOjbYPPrAZXCad\n\t94HWeHMSOfAiJ/eonC1mJS6k736MTLQDrl6zjfI2WuD7rjDvQciWhTvVy2NdlJ0Koq3EzpuHd/f\n\tgGgoXNwfe4MFqtgcR//I3oTIsmVRNF7IWNThMK4dWeFNzK1vl0qcJxWZ5/lR8p+cg3PT8JVw86a\n\ty9NNiI8eLzNWBegCW2wgn7iDBesS0qyYS0oyUVZnwvHE5fonBJEgSTIJdWlhBql/DsVDZa0hgOY\n\t0ZunxUT+8zzNvCKk7XY+JOJcECYwmPXCPbKMwBq7MYkxbqFHioMoGKh3pNj671NuKS30BZnQIFI\n\tZLtsgG0DUH+nVLNyiCsqIP9TxvtJo1s8kG68toueqD9WtJkSIw==", "X-TM-AS-User-Approved-Sender": "No", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10-0.063800-4.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.5.1010-24084.005", "X-MDID": "1536572035-a7jtwkd4m6k4", "Subject": "[dpdk-dev] [PATCH 30/37] net/sfc/base: add support to get active\n\tFEC type", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Vijay Srivastava <vijays@solarflare.com>\n\nSigned-off-by: Vijay Srivastava <vijays@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_impl.h | 6 ++++\n drivers/net/sfc/base/ef10_phy.c | 60 +++++++++++++++++++++++++++++---\n drivers/net/sfc/base/efx.h | 11 ++++++\n drivers/net/sfc/base/efx_impl.h | 1 +\n drivers/net/sfc/base/efx_phy.c | 39 ++++++++++++++++++++-\n 5 files changed, 111 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h\nindex 2819ae6ed..b72e7d256 100644\n--- a/drivers/net/sfc/base/ef10_impl.h\n+++ b/drivers/net/sfc/base/ef10_impl.h\n@@ -596,6 +596,7 @@ typedef struct ef10_link_state_s {\n \tuint32_t\t\tels_adv_cap_mask;\n \tuint32_t\t\tels_lp_cap_mask;\n \tunsigned int\t\tels_fcntl;\n+\tefx_phy_fec_type_t\tels_fec;\n \tefx_link_mode_t\t\tels_link_mode;\n #if EFSYS_OPT_LOOPBACK\n \tefx_loopback_type_t\tels_loopback;\n@@ -632,6 +633,11 @@ ef10_phy_oui_get(\n \t__in\t\tefx_nic_t *enp,\n \t__out\t\tuint32_t *ouip);\n \n+extern\t__checkReturn\tefx_rc_t\n+ef10_phy_fec_type_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tefx_phy_fec_type_t *fecp);\n+\n #if EFSYS_OPT_PHY_STATS\n \n extern\t__checkReturn\t\t\tefx_rc_t\ndiff --git a/drivers/net/sfc/base/ef10_phy.c b/drivers/net/sfc/base/ef10_phy.c\nindex a1f59ff1c..ec3600e96 100644\n--- a/drivers/net/sfc/base/ef10_phy.c\n+++ b/drivers/net/sfc/base/ef10_phy.c\n@@ -98,8 +98,10 @@ mcdi_phy_decode_link_mode(\n \t__in\t\tuint32_t link_flags,\n \t__in\t\tunsigned int speed,\n \t__in\t\tunsigned int fcntl,\n+\t__in\t\tuint32_t fec,\n \t__out\t\tefx_link_mode_t *link_modep,\n-\t__out\t\tunsigned int *fcntlp)\n+\t__out\t\tunsigned int *fcntlp,\n+\t__out\t\tefx_phy_fec_type_t *fecp)\n {\n \tboolean_t fd = !!(link_flags &\n \t\t (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));\n@@ -141,6 +143,22 @@ mcdi_phy_decode_link_mode(\n \t\tEFSYS_PROBE1(mc_pcol_error, int, fcntl);\n \t\t*fcntlp = 0;\n \t}\n+\n+\tswitch (fec) {\n+\tcase MC_CMD_FEC_NONE:\n+\t\t*fecp = EFX_PHY_FEC_NONE;\n+\t\tbreak;\n+\tcase MC_CMD_FEC_BASER:\n+\t\t*fecp = EFX_PHY_FEC_BASER;\n+\t\tbreak;\n+\tcase MC_CMD_FEC_RS:\n+\t\t*fecp = EFX_PHY_FEC_RS;\n+\t\tbreak;\n+\tdefault:\n+\t\tEFSYS_PROBE1(mc_pcol_error, int, fec);\n+\t\t*fecp = EFX_PHY_FEC_NONE;\n+\t\tbreak;\n+\t}\n }\n \n \n@@ -154,6 +172,7 @@ ef10_phy_link_ev(\n \tunsigned int link_flags;\n \tunsigned int speed;\n \tunsigned int fcntl;\n+\tefx_phy_fec_type_t fec = MC_CMD_FEC_NONE;\n \tefx_link_mode_t link_mode;\n \tuint32_t lp_cap_mask;\n \n@@ -191,7 +210,8 @@ ef10_phy_link_ev(\n \tlink_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS);\n \tmcdi_phy_decode_link_mode(enp, link_flags, speed,\n \t\t\t\t MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL),\n-\t\t\t\t &link_mode, &fcntl);\n+\t\t\t\t MC_CMD_FEC_NONE, &link_mode,\n+\t\t\t\t &fcntl, &fec);\n \tmcdi_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP),\n \t\t\t &lp_cap_mask);\n \n@@ -242,15 +262,16 @@ ef10_phy_get_link(\n \t__out\t\tef10_link_state_t *elsp)\n {\n \tefx_mcdi_req_t req;\n+\tuint32_t fec;\n \tEFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LINK_IN_LEN,\n-\t\tMC_CMD_GET_LINK_OUT_LEN);\n+\t\tMC_CMD_GET_LINK_OUT_V2_LEN);\n \tefx_rc_t rc;\n \n \treq.emr_cmd = MC_CMD_GET_LINK;\n \treq.emr_in_buf = payload;\n \treq.emr_in_length = MC_CMD_GET_LINK_IN_LEN;\n \treq.emr_out_buf = payload;\n-\treq.emr_out_length = MC_CMD_GET_LINK_OUT_LEN;\n+\treq.emr_out_length = MC_CMD_GET_LINK_OUT_V2_LEN;\n \n \tefx_mcdi_execute(enp, &req);\n \n@@ -269,10 +290,16 @@ ef10_phy_get_link(\n \tmcdi_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP),\n \t\t\t &elsp->els_lp_cap_mask);\n \n+\tif (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_V2_LEN)\n+\t\tfec = MC_CMD_FEC_NONE;\n+\telse\n+\t\tfec = MCDI_OUT_DWORD(req, GET_LINK_OUT_V2_FEC_TYPE);\n+\n \tmcdi_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),\n \t\t\t MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),\n \t\t\t MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),\n-\t\t\t &elsp->els_link_mode, &elsp->els_fcntl);\n+\t\t\t fec, &elsp->els_link_mode,\n+\t\t\t &elsp->els_fcntl, &elsp->els_fec);\n \n #if EFSYS_OPT_LOOPBACK\n \t/*\n@@ -515,6 +542,29 @@ ef10_phy_oui_get(\n \treturn (ENOTSUP);\n }\n \n+\t__checkReturn\tefx_rc_t\n+ef10_phy_fec_type_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tefx_phy_fec_type_t *fecp)\n+{\n+\tefx_rc_t rc;\n+\tef10_link_state_t els;\n+\n+\t/* Obtain the active FEC type */\n+\tif ((rc = ef10_phy_get_link(enp, &els)) != 0)\n+\t\tgoto fail1;\n+\n+\t*fecp = els.els_fec;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\n #if EFSYS_OPT_PHY_STATS\n \n \t__checkReturn\t\t\t\tefx_rc_t\ndiff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h\nindex 15b3882dd..cc68f744e 100644\n--- a/drivers/net/sfc/base/efx.h\n+++ b/drivers/net/sfc/base/efx.h\n@@ -3202,6 +3202,17 @@ efx_nic_set_fw_subvariant(\n \n #endif\t/* EFSYS_OPT_FW_SUBVARIANT_AWARE */\n \n+typedef enum efx_phy_fec_type_e {\n+\tEFX_PHY_FEC_NONE = 0,\n+\tEFX_PHY_FEC_BASER,\n+\tEFX_PHY_FEC_RS\n+} efx_phy_fec_type_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_phy_fec_type_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tefx_phy_fec_type_t *typep);\n+\n #ifdef\t__cplusplus\n }\n #endif\ndiff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h\nindex 2c95571b1..9f44d2f64 100644\n--- a/drivers/net/sfc/base/efx_impl.h\n+++ b/drivers/net/sfc/base/efx_impl.h\n@@ -224,6 +224,7 @@ typedef struct efx_phy_ops_s {\n \tefx_rc_t\t(*epo_reconfigure)(efx_nic_t *);\n \tefx_rc_t\t(*epo_verify)(efx_nic_t *);\n \tefx_rc_t\t(*epo_oui_get)(efx_nic_t *, uint32_t *);\n+\tefx_rc_t\t(*epo_fec_type_get)(efx_nic_t *, efx_phy_fec_type_t *);\n #if EFSYS_OPT_PHY_STATS\n \tefx_rc_t\t(*epo_stats_update)(efx_nic_t *, efsys_mem_t *,\n \t\t\t\t\t uint32_t *);\ndiff --git a/drivers/net/sfc/base/efx_phy.c b/drivers/net/sfc/base/efx_phy.c\nindex ba2f51c17..7c341e429 100644\n--- a/drivers/net/sfc/base/efx_phy.c\n+++ b/drivers/net/sfc/base/efx_phy.c\n@@ -15,6 +15,7 @@ static const efx_phy_ops_t\t__efx_phy_siena_ops = {\n \tsiena_phy_reconfigure,\t\t/* epo_reconfigure */\n \tsiena_phy_verify,\t\t/* epo_verify */\n \tsiena_phy_oui_get,\t\t/* epo_oui_get */\n+\tNULL,\t\t\t\t/* epo_fec_type_get */\n #if EFSYS_OPT_PHY_STATS\n \tsiena_phy_stats_update,\t\t/* epo_stats_update */\n #endif\t/* EFSYS_OPT_PHY_STATS */\n@@ -34,6 +35,7 @@ static const efx_phy_ops_t\t__efx_phy_ef10_ops = {\n \tef10_phy_reconfigure,\t\t/* epo_reconfigure */\n \tef10_phy_verify,\t\t/* epo_verify */\n \tef10_phy_oui_get,\t\t/* epo_oui_get */\n+\tef10_phy_fec_type_get,\t\t/* epo_fec_type_get */\n #if EFSYS_OPT_PHY_STATS\n \tef10_phy_stats_update,\t\t/* epo_stats_update */\n #endif\t/* EFSYS_OPT_PHY_STATS */\n@@ -190,6 +192,11 @@ efx_phy_adv_cap_get(\n \t}\n }\n \n+#define\tEFX_PHY_CAP_FEC_REQ_MASK\t\t\t\\\n+\t(1U << EFX_PHY_CAP_BASER_FEC_REQUESTED)\t|\t\\\n+\t(1U << EFX_PHY_CAP_RS_FEC_REQUESTED)\t|\t\\\n+\t(1U << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED)\n+\n \t__checkReturn\tefx_rc_t\n efx_phy_adv_cap_set(\n \t__in\t\tefx_nic_t *enp,\n@@ -203,7 +210,8 @@ efx_phy_adv_cap_set(\n \tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n \tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n \n-\tif ((mask & ~epp->ep_phy_cap_mask) != 0) {\n+\t/* Ignore don't care bits of FEC (FEC EFX_PHY_CAP_*_REQUESTED) */\n+\tif ((mask & ~(epp->ep_phy_cap_mask | EFX_PHY_CAP_FEC_REQ_MASK)) != 0) {\n \t\trc = ENOTSUP;\n \t\tgoto fail1;\n \t}\n@@ -306,6 +314,35 @@ efx_phy_module_get_info(\n \n \treturn (0);\n \n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\tefx_rc_t\n+efx_phy_fec_type_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tefx_phy_fec_type_t *typep)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_phy_ops_t *epop = epp->ep_epop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\n+\tif (epop->epo_fec_type_get == NULL) {\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif ((rc = epop->epo_fec_type_get(enp, typep)) != 0)\n+\t\tgoto fail2;\n+\n+\treturn (0);\n+\n fail2:\n \tEFSYS_PROBE(fail2);\n fail1:\n", "prefixes": [ "30/37" ] }