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GET /api/patches/44416/?format=api
{ "id": 44416, "url": "http://patches.dpdk.org/api/patches/44416/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536333719-32155-22-git-send-email-igor.russkikh@aquantia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536333719-32155-22-git-send-email-igor.russkikh@aquantia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536333719-32155-22-git-send-email-igor.russkikh@aquantia.com", "date": "2018-09-07T15:21:59", "name": "[21/21] net/atlantic: TX side structures and implementation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fd79b812cfa8971c44cdf2597cb8f6ff225fd3d2", "submitter": { "id": 1124, "url": "http://patches.dpdk.org/api/people/1124/?format=api", "name": "Igor Russkikh", "email": "igor.russkikh@aquantia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536333719-32155-22-git-send-email-igor.russkikh@aquantia.com/mbox/", "series": [ { "id": 1228, "url": "http://patches.dpdk.org/api/series/1228/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1228", "date": "2018-09-07T15:21:39", "name": "net/atlantic: Aquantia aQtion 10G NIC Family DPDK PMD driver", "version": 1, "mbox": "http://patches.dpdk.org/series/1228/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44416/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/44416/checks/", "tags": {}, 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"TEBuiTNN+AC/IajzHam6BL4Lf+MDDcpH7HJPoqD9f2o13OB2g8oxY52P9AmZZo26pk4NFjfyRx8REXvoMjKOUWmys/wjeK/fyNrZLNj531u3iVJpu7b44PdB8+4J9EEPggKfwpiJa9sPtmZYtRhN/3ji8QdWZ5LLvenye+KZo61ksSzDrdki9mnCtc7tiQ1j/owowInyo6vlDFlefq2dqT0rsr36YzJf1AdAMestf8t5G7yN6QdAP7ORLTiBRxbCTv4IgXmsvw5jZMWOidjSyq5b+DS3Id2z/EDGWJUI3n/b06Nw4L2VO+/KP0CdpzOLyyNjmdzVa+KBNBu0UEjXA/m7MlR596ERpJcGN/a7+r0=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "aquantia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Sep 2018 15:23:41.0956\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "5ed4e362-2b70-4c80-47cb-08d614d5e523", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "83e2e134-991c-4ede-8ced-34d47e38e6b1", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BLUPR0701MB1652", "Subject": "[dpdk-dev] [PATCH 21/21] net/atlantic: TX side structures and\n\timplementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavel Belous <pavel.belous@aquantia.com>\n\nSigned-off-by: Igor Russkikh <igor.russkikh@aquantia.com>\n---\n drivers/net/atlantic/atl_ethdev.c | 10 +\n drivers/net/atlantic/atl_rxtx.c | 566 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 576 insertions(+)", "diff": "diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c\nindex bb4d96bb1..7abae2236 100644\n--- a/drivers/net/atlantic/atl_ethdev.c\n+++ b/drivers/net/atlantic/atl_ethdev.c\n@@ -297,6 +297,11 @@ static const struct eth_dev_ops atl_eth_dev_ops = {\n \t.rx_queue_setup = atl_rx_queue_setup,\n \t.rx_queue_release = atl_rx_queue_release,\n \n+\t.tx_queue_start\t = atl_tx_queue_start,\n+\t.tx_queue_stop\t = atl_tx_queue_stop,\n+\t.tx_queue_setup = atl_tx_queue_setup,\n+\t.tx_queue_release = atl_tx_queue_release,\n+\n \t.rx_queue_intr_enable = atl_dev_rx_queue_intr_enable,\n \t.rx_queue_intr_disable = atl_dev_rx_queue_intr_disable,\n \n@@ -324,6 +329,8 @@ static const struct eth_dev_ops atl_eth_dev_ops = {\n \t.mac_addr_set\t = atl_set_default_mac_addr,\n \t.set_mc_addr_list = atl_dev_set_mc_addr_list,\n \t.rxq_info_get\t = atl_rxq_info_get,\n+\t.txq_info_get\t = atl_txq_info_get,\n+\n \t.reta_update = atl_reta_update,\n \t.reta_query = atl_reta_query,\n \t.rss_hash_update = atl_rss_hash_update,\n@@ -639,6 +646,9 @@ atl_dev_start(struct rte_eth_dev *dev)\n \t\t}\n \t}\n \n+\t/* initialize transmission unit */\n+\tatl_tx_init(dev);\n+\n \t/* This can fail when allocating mbufs for descriptor rings */\n \terr = atl_rx_init(dev);\n \tif (err) {\ndiff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c\nindex 6198f5dfe..bed2265b9 100644\n--- a/drivers/net/atlantic/atl_rxtx.c\n+++ b/drivers/net/atlantic/atl_rxtx.c\n@@ -46,6 +46,20 @@\n #include \"hw_atl/hw_atl_b0.h\"\n #include \"hw_atl/hw_atl_b0_internal.h\"\n \n+#define ATL_TX_CKSUM_OFFLOAD_MASK (\t\t\t\t \\\n+\tPKT_TX_IP_CKSUM |\t\t\t\t \\\n+\tPKT_TX_L4_MASK |\t\t\t\t \\\n+\tPKT_TX_TCP_SEG)\n+\n+#define ATL_TX_OFFLOAD_MASK ( \\\n+\tPKT_TX_VLAN_PKT |\t\t\t\t \\\n+\tPKT_TX_IP_CKSUM |\t\t\t\t \\\n+\tPKT_TX_L4_MASK |\t\t\t\t \\\n+\tPKT_TX_TCP_SEG)\n+\n+#define ATL_TX_OFFLOAD_NOTSUP_MASK \\\n+\t(PKT_TX_OFFLOAD_MASK ^ ATL_TX_OFFLOAD_MASK)\n+\n /**\n * Structure associated with each descriptor of the RX ring of a RX queue.\n */\n@@ -54,6 +68,15 @@ struct atl_rx_entry {\n };\n \n /**\n+ * Structure associated with each descriptor of the TX ring of a TX queue.\n+ */\n+struct atl_tx_entry {\n+\tstruct rte_mbuf *mbuf;\n+\tuint16_t next_id;\n+\tuint16_t last_id;\n+};\n+\n+/**\n * Structure associated with each RX queue.\n */\n struct atl_rx_queue {\n@@ -72,6 +95,22 @@ struct atl_rx_queue {\n \tbool\t\t\tl4_csum_enabled;\n };\n \n+/**\n+ * Structure associated with each TX queue.\n+ */\n+struct atl_tx_queue {\n+\tstruct hw_atl_txd_s\t*hw_ring;\n+\tuint64_t\t\thw_ring_phys_addr;\n+\tstruct atl_tx_entry\t*sw_ring;\n+\tuint16_t\t\tnb_tx_desc;\n+\tuint16_t\t\ttx_tail;\n+\tuint16_t\t\ttx_head;\n+\tuint16_t\t\tqueue_id;\n+\tuint16_t\t\tport_id;\n+\tuint16_t\t\ttx_free_thresh;\n+\tuint16_t\t\ttx_free;\n+};\n+\n inline static void\n atl_reset_rx_queue(struct atl_rx_queue *rxq)\n {\n@@ -169,6 +208,134 @@ atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n \treturn 0;\n }\n \n+static inline void\n+atl_reset_tx_queue(struct atl_tx_queue *txq)\n+{\n+\tstruct atl_tx_entry *tx_entry;\n+\tunion hw_atl_txc_s *txc;\n+\tuint16_t i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (!txq) {\n+\t\tPMD_DRV_LOG(ERR, \"Pointer to txq is NULL\");\n+\t\treturn;\n+\t}\n+\n+\ttx_entry = txq->sw_ring;\n+\n+\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n+\t\ttxc = (union hw_atl_txc_s *)&txq->hw_ring[i];\n+\t\ttxc->flags1 = 0;\n+\t\ttxc->flags2 = 2;\n+\t}\n+\n+\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n+\t\ttxq->hw_ring[i].dd = 1;\n+\t\ttx_entry[i].mbuf = NULL;\n+\t}\n+\n+\ttxq->tx_tail = 0;\n+\ttxq->tx_head = 0;\n+\ttxq->tx_free = txq->nb_tx_desc - 1;\n+}\n+\n+int\n+atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n+\t\t uint16_t nb_tx_desc, unsigned int socket_id,\n+\t\t const struct rte_eth_txconf *tx_conf)\n+{\n+\tstruct atl_tx_queue *txq;\n+\tconst struct rte_memzone *mz;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* make sure a valid number of descriptors have been requested */\n+\tif (nb_tx_desc < AQ_HW_MIN_TX_RING_SIZE || nb_tx_desc > AQ_HW_MAX_TX_RING_SIZE) {\n+\t\tPMD_INIT_LOG(ERR, \"Number of Tx descriptors must be \"\n+\t\t\t\"less than or equal to %d, \"\n+\t\t\t\"greater than or equal to %d\", AQ_HW_MAX_TX_RING_SIZE, AQ_HW_MIN_TX_RING_SIZE);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * if this queue existed already, free the associated memory. The\n+\t * queue cannot be reused in case we need to allocate memory on\n+\t * different socket than was previously used.\n+\t */\n+\tif (dev->data->tx_queues[tx_queue_id] != NULL) {\n+\t\tatl_tx_queue_release(dev->data->tx_queues[tx_queue_id]);\n+\t\tdev->data->tx_queues[tx_queue_id] = NULL;\n+\t}\n+\n+\t/* allocate memory for the queue structure */\n+\ttxq = rte_zmalloc_socket(\"atlantic Tx queue\", sizeof(*txq), RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Cannot allocate queue structure\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* setup queue */\n+\ttxq->nb_tx_desc = nb_tx_desc;\n+\ttxq->port_id = dev->data->port_id;\n+\ttxq->queue_id = tx_queue_id;\n+\ttxq->tx_free_thresh = tx_conf->tx_free_thresh;\n+\n+\n+\t/* allocate memory for the software ring */\n+\ttxq->sw_ring = rte_zmalloc_socket(\"atlantic sw tx ring\",\n+\t\t\t\t\t\tnb_tx_desc * sizeof(struct atl_tx_entry),\n+\t\t\t\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq->sw_ring == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Cannot allocate software ring\");\n+\t\trte_free(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/*\n+\t * allocate memory for the hardware descriptor ring. A memzone large\n+\t * enough to hold the maximum ring size is requested to allow for\n+\t * resizing in later calls to the queue setup function.\n+\t */\n+\tmz = rte_eth_dma_zone_reserve(dev, \"tx hw_ring\", tx_queue_id,\n+\t\t\t\t HW_ATL_B0_MAX_TXD * sizeof(struct hw_atl_txd_s),\n+\t\t\t\t 128, socket_id);\n+\tif (mz == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Cannot allocate hardware ring\");\n+\t\trte_free(txq->sw_ring);\n+\t\trte_free(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\ttxq->hw_ring = mz->addr;\n+\ttxq->hw_ring_phys_addr = mz->iova;\n+\n+\tatl_reset_tx_queue(txq);\n+\n+\tdev->data->tx_queues[tx_queue_id] = txq;\n+\treturn 0;\n+}\n+\n+int\n+atl_tx_init(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n+\tstruct atl_tx_queue *txq;\n+\tuint64_t base_addr = 0;\n+\tint i = 0;\n+\tint err = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tfor (i =0 ; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\ttxq = eth_dev->data->tx_queues[i];\n+\t\tbase_addr = txq->hw_ring_phys_addr;\n+\n+\t\terr = hw_atl_b0_hw_ring_tx_init(hw, base_addr, txq->queue_id, txq->nb_tx_desc, 0, txq->port_id);\n+\t}\n+\n+\treturn err;\n+}\n+\n int\n atl_rx_init(struct rte_eth_dev *eth_dev)\n {\n@@ -324,6 +491,77 @@ atl_rx_queue_release(void *rx_queue)\n \t}\n }\n \n+static void\n+atl_tx_queue_release_mbufs(struct atl_tx_queue *txq)\n+{\n+\tint i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (txq->sw_ring != NULL) {\n+\t\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n+\t\t\tif (txq->sw_ring[i].mbuf != NULL) {\n+\t\t\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n+\t\t\t\ttxq->sw_ring[i].mbuf = NULL;\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+int\n+atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (tx_queue_id < dev->data->nb_tx_queues) {\n+\t\thw_atl_b0_hw_ring_tx_start(hw, tx_queue_id);\n+\n+\t\trte_wmb();\n+\t\thw_atl_b0_hw_tx_ring_tail_update(hw, 0, tx_queue_id);\n+\t\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n+\t} else {\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct atl_tx_queue *txq;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\n+\thw_atl_b0_hw_ring_tx_stop(hw, tx_queue_id);\n+\n+\tatl_tx_queue_release_mbufs(txq);\n+\tatl_reset_tx_queue(txq);\n+\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\treturn 0;\n+}\n+\n+void\n+atl_tx_queue_release(void *tx_queue)\n+{\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (tx_queue != NULL) {\n+\t\tstruct atl_tx_queue *txq = (struct atl_tx_queue *)tx_queue;\n+\n+\t\tatl_tx_queue_release_mbufs(txq);\n+\t\trte_free(txq->sw_ring);\n+\t\trte_free(txq);\n+\t}\n+}\n+\n void\n atl_free_queues(struct rte_eth_dev *dev)\n {\n@@ -337,6 +575,11 @@ atl_free_queues(struct rte_eth_dev *dev)\n \t}\n \tdev->data->nb_rx_queues = 0;\n \n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tatl_tx_queue_release(dev->data->tx_queues[i]);\n+\t\tdev->data->tx_queues[i] = 0;\n+\t}\n+\tdev->data->nb_tx_queues = 0;\n }\n \n int\n@@ -346,6 +589,13 @@ atl_start_queues(struct rte_eth_dev *dev)\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tif (atl_tx_queue_start(dev, i) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Start Tx queue %d failed\", i);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n \tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n \t\tif (atl_rx_queue_start(dev, i) != 0) {\n \t\t\tPMD_DRV_LOG(ERR, \"Start Rx queue %d failed\", i);\n@@ -363,6 +613,13 @@ atl_stop_queues(struct rte_eth_dev *dev)\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tif (atl_tx_queue_stop(dev, i) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Stop Tx queue %d failed\", i);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n \tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n \t\tif (atl_rx_queue_stop(dev, i) != 0) {\n \t\t\tPMD_DRV_LOG(ERR, \"Stop Rx queue %d failed\", i);\n@@ -387,6 +644,18 @@ atl_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, struct rte_eth_rxq_\n \tqinfo->nb_desc = rxq->nb_rx_desc;\n }\n \n+void\n+atl_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, struct rte_eth_txq_info *qinfo)\n+{\n+\tstruct atl_tx_queue *txq;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttxq = dev->data->tx_queues[queue_id];\n+\n+\tqinfo->nb_desc = txq->nb_tx_desc;\n+}\n+\n /* Return Rx queue avail count */\n \n uint32_t\n@@ -459,6 +728,31 @@ atl_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)\n \treturn RTE_ETH_RX_DESC_AVAIL;\n }\n \n+int\n+atl_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)\n+{\n+\tstruct atl_tx_queue *txq = tx_queue;\n+\tstruct hw_atl_txd_s *txd;\n+\tuint32_t idx;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (unlikely(offset >= txq->nb_tx_desc))\n+\t\treturn -EINVAL;\n+\n+\tidx = txq->tx_tail + offset;\n+\n+\tif (idx >= txq->nb_tx_desc)\n+\t\tidx -= txq->nb_tx_desc;\n+\n+\ttxd = &txq->hw_ring[idx];\n+\n+\tif (txd->dd)\n+\t\treturn RTE_ETH_TX_DESC_DONE;\n+\n+\treturn RTE_ETH_TX_DESC_FULL;\n+}\n+\n static int\n atl_rx_enable_intr(struct rte_eth_dev *dev, uint16_t queue_id, bool enable)\n {\n@@ -495,6 +789,46 @@ atl_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, uint16_t queue_id)\n \treturn atl_rx_enable_intr(eth_dev, queue_id, false);\n }\n \n+uint16_t\n+atl_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tint i, ret;\n+\tuint64_t ol_flags;\n+\tstruct rte_mbuf *m;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tfor (i = 0; i < nb_pkts; i++) {\n+\t\tm = tx_pkts[i];\n+\t\tol_flags = m->ol_flags;\n+\n+\t\tif (m->nb_segs > AQ_HW_MAX_SEGS_SIZE) {\n+\t\t\trte_errno = -EINVAL;\n+\t\t\treturn i;\n+\t\t}\n+\n+\t\tif (ol_flags & ATL_TX_OFFLOAD_NOTSUP_MASK) {\n+\t\t\trte_errno = -ENOTSUP;\n+\t\t\treturn i;\n+\t\t}\n+\n+#ifdef RTE_LIBRTE_ETHDEV_DEBUG\n+\t\tret = rte_validate_tx_offload(m);\n+\t\tif (ret != 0) {\n+\t\t\trte_errno = ret;\n+\t\t\treturn i;\n+\t\t}\n+#endif\n+\t\tret = rte_net_intel_cksum_prepare(m);\n+\t\tif (ret != 0) {\n+\t\t\trte_errno = ret;\n+\t\t\treturn i;\n+\t\t}\n+\t}\n+\n+\treturn i;\n+}\n+\n static uint64_t\n atl_desc_to_offload_flags(struct atl_rx_queue *rxq, struct hw_atl_rxd_wb_s *rxd_wb)\n {\n@@ -756,3 +1090,235 @@ atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \n \treturn nb_rx;\n }\n+\n+static void \n+atl_xmit_cleanup(struct atl_tx_queue *txq)\n+{\n+\tstruct atl_tx_entry *sw_ring;\n+\tstruct hw_atl_txd_s *txd;\n+\tint to_clean = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (txq != NULL) {\n+\t\tsw_ring = txq->sw_ring;\n+\t\tint head = txq->tx_head;\n+\t\tint cnt;\n+\t\tint i;\n+\n+\t\tfor (i = 0, cnt = head; ; i++) {\n+\t\t\ttxd = &txq->hw_ring[cnt];\n+\n+\t\t\tif (txd->dd)\n+\t\t\t\tto_clean++;\n+\n+\t\t\tcnt = (cnt + 1) % txq->nb_tx_desc;\n+\t\t\tif (cnt == txq->tx_tail)\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (to_clean == 0)\n+\t\t\treturn;\n+\n+\t\twhile (to_clean) {\n+\t\t\ttxd = &txq->hw_ring[head];\n+\n+\t\t\tstruct atl_tx_entry *rx_entry = &sw_ring[head];\n+\n+\t\t\tif (rx_entry->mbuf) {\n+\t\t\t\trte_pktmbuf_free_seg(rx_entry->mbuf);\n+\t\t\t\trx_entry->mbuf = NULL;\n+\t\t\t}\n+\n+\t\t\tif (txd->dd) {\n+\t\t\t\tto_clean--;\n+\t\t\t}\n+\n+\t\t\ttxd->buf_addr = 0;\n+\t\t\ttxd->flags = 0;\n+\n+\t\t\thead = (head + 1) % txq->nb_tx_desc;\n+\t\t\ttxq->tx_free++;\n+\t\t}\n+\n+\t\ttxq->tx_head = head;\n+\t}\n+}\n+\n+static int\n+atl_tso_setup(struct rte_mbuf *tx_pkt, union hw_atl_txc_s *txc)\n+{\n+\tuint32_t tx_cmd = 0;\n+\tuint64_t ol_flags = tx_pkt->ol_flags;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (ol_flags & PKT_TX_TCP_SEG) {\n+\t\tPMD_DRV_LOG(DEBUG, \"xmit TSO pkt\");\n+\t\n+\t\ttx_cmd |= tx_desc_cmd_lso | tx_desc_cmd_l4cs;\n+\n+\t\ttxc->cmd = 0x4;\n+\n+\t\tif (ol_flags & PKT_TX_IPV6)\n+\t\t\ttxc->cmd |= 0x2;\n+\n+\t\ttxc->l2_len = tx_pkt->l2_len;\n+\t\ttxc->l3_len = tx_pkt->l3_len;\n+\t\ttxc->l4_len = tx_pkt->l4_len;\n+\n+\t\ttxc->mss_len = tx_pkt->tso_segsz;\n+\t}\n+\n+\tif (ol_flags & PKT_TX_VLAN_PKT) {\n+\t\ttx_cmd |= tx_desc_cmd_vlan;\n+\t\ttxc->vlan_tag = tx_pkt->vlan_tci;\n+\t}\n+\n+\tif (tx_cmd) {\n+\t\ttxc->type = tx_desc_type_ctx;\n+\t\ttxc->idx = 0;\n+\t}\n+\n+\treturn tx_cmd;\n+}\n+\n+static inline void\n+atl_setup_csum_offload(struct rte_mbuf *mbuf, struct hw_atl_txd_s *txd, uint32_t tx_cmd)\n+{\n+\ttxd->cmd |= tx_desc_cmd_fcs;\n+\ttxd->cmd |= (mbuf->ol_flags & PKT_TX_IP_CKSUM) ? tx_desc_cmd_ipv4 : 0;\n+\t/* L4 csum requested */\n+\ttxd->cmd |= (mbuf->ol_flags & PKT_TX_L4_MASK) ? tx_desc_cmd_l4cs : 0;\n+\ttxd->cmd |= tx_cmd;\n+}\n+\n+static inline void\n+atl_xmit_pkt(struct aq_hw_s *hw, struct atl_tx_queue *txq, struct rte_mbuf *tx_pkt)\n+{\n+\tstruct atl_adapter *adapter = ATL_DEV_TO_ADAPTER(&rte_eth_devices[txq->port_id]);\n+\tuint32_t pay_len = 0;\n+\tint tail = 0;\n+\tstruct atl_tx_entry *tx_entry;\n+\tuint64_t buf_dma_addr;\n+\tstruct rte_mbuf *m_seg;\n+\tunion hw_atl_txc_s *txc = NULL;\n+\tstruct hw_atl_txd_s *txd = NULL;\n+\tu32 tx_cmd = 0U;\n+\tint desc_count = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttail = txq->tx_tail;\n+\n+\ttxc = (union hw_atl_txc_s *)&txq->hw_ring[tail];\n+\n+\ttxc->flags1 = 0U;\n+\ttxc->flags2 = 0U;\n+\n+\ttx_cmd = atl_tso_setup(tx_pkt, txc);\n+\n+\tif (tx_cmd) {\n+\t\t/* We've consumed the first desc, adjust counters */\n+\t\ttail = (tail + 1) % txq->nb_tx_desc;\n+\t\ttxq->tx_tail = tail;\n+\t\ttxq->tx_free -= 1;\n+\n+\t\ttxd = &txq->hw_ring[tail];\n+\t\ttxd->flags = 0U;\n+\t} else {\n+\t\ttxd = (struct hw_atl_txd_s *)txc;\n+\t}\n+\n+\ttxd->ct_en = !!tx_cmd;\n+\n+\ttxd->type = tx_desc_type_desc;\n+\n+\tatl_setup_csum_offload(tx_pkt, txd, tx_cmd);\n+\n+\tif (tx_cmd) {\n+\t\ttxd->ct_idx = 0;\n+\t}\n+\n+\tpay_len = tx_pkt->pkt_len;\n+\n+\ttxd->pay_len = pay_len;\n+\t\n+\tfor (m_seg = tx_pkt; m_seg; m_seg = m_seg->next) {\n+\t\tif (desc_count > 0) {\n+\t\t\ttxd = &txq->hw_ring[tail];\n+\t\t\ttxd->flags = 0U;\n+\t\t}\n+\n+\t\tbuf_dma_addr = rte_mbuf_data_iova(m_seg);\n+\t\ttxd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);\n+\n+\t\ttxd->type = tx_desc_type_desc;\n+\t\ttxd->len = m_seg->data_len;\n+\t\ttxd->pay_len = pay_len;\n+\n+\t\t/* Store mbuf for freeing later */\n+\t\ttx_entry = &txq->sw_ring[tail];\n+\n+\t\tif (tx_entry->mbuf)\n+\t\t\trte_pktmbuf_free_seg(tx_entry->mbuf);\n+\t\ttx_entry->mbuf = m_seg;\n+\n+\t\ttail = (tail + 1) % txq->nb_tx_desc;\n+\n+\t\tdesc_count++;\n+\t}\n+\n+\t// Last descriptor requires EOP and WB\n+\ttxd->eop = 1U;\n+\ttxd->cmd |= tx_desc_cmd_wb;\n+\n+\thw_atl_b0_hw_tx_ring_tail_update(hw, tail, txq->queue_id);\n+\n+\ttxq->tx_tail = tail;\n+\n+\ttxq->tx_free -= desc_count;\n+\n+\tadapter->sw_stats.q_opackets[txq->queue_id]++;\n+\tadapter->sw_stats.q_obytes[txq->queue_id] += pay_len;\n+}\n+\n+uint16_t\n+atl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct rte_eth_dev *dev = NULL;\n+\tstruct aq_hw_s *hw = NULL;\n+\tstruct atl_tx_queue *txq = tx_queue;\n+\tstruct rte_mbuf *tx_pkt;\n+\tuint16_t nb_tx;\n+\n+\tdev = &rte_eth_devices[txq->port_id];\n+\thw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tPMD_TX_LOG(DEBUG, \"txq%d pkts: %d tx_free=%d tx_tail=%d tx_head=%d\",\n+\t\t\ttxq->queue_id, nb_pkts, txq->tx_free, txq->tx_tail, txq->tx_head);\n+\n+\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n+\t\ttx_pkt = *tx_pkts++;\n+\n+\t\t/* Clean Tx queue if needed */\n+\t\tif (txq->tx_free < txq->tx_free_thresh)\n+\t\t\tatl_xmit_cleanup(txq);\n+\n+\t\t/* Check if we have enough free descriptors */\n+\t\tif (txq->tx_free < tx_pkt->nb_segs)\n+\t\t\tbreak;\n+\n+\t\t/* check mbuf is valid */\n+\t\tif ((tx_pkt->nb_segs == 0) || ((tx_pkt->nb_segs > 1) && (tx_pkt->next == NULL)))\n+\t\t\tbreak;\n+\n+\t\t/* Send the packet */\n+\t\tatl_xmit_pkt(hw, txq, tx_pkt);\n+\t}\n+\n+\tPMD_TX_LOG(DEBUG, \"atl_xmit_pkts %d transmitted\", nb_tx);\n+\n+\treturn nb_tx;\n+}\n+\n", "prefixes": [ "21/21" ] }