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GET /api/patches/44204/?format=api
{ "id": 44204, "url": "http://patches.dpdk.org/api/patches/44204/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-25-git-send-email-ajoseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536033560-21541-25-git-send-email-ajoseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536033560-21541-25-git-send-email-ajoseph@caviumnetworks.com", "date": "2018-09-04T03:59:11", "name": "[v2,24/33] common/cpt: add support for zuc and snow3g", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "605bd0eb14e7081bea40f1b5ea4848edeb543955", "submitter": { "id": 891, "url": "http://patches.dpdk.org/api/people/891/?format=api", "name": "Anoob Joseph", "email": "ajoseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-25-git-send-email-ajoseph@caviumnetworks.com/mbox/", "series": [ { "id": 1164, "url": "http://patches.dpdk.org/api/series/1164/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1164", "date": "2018-09-04T03:58:47", "name": "Adding Cavium's OcteonTX crypto PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/1164/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44204/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/44204/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D99D4AAB5;\n\tTue, 4 Sep 2018 06:03:40 +0200 (CEST)", "from NAM01-SN1-obe.outbound.protection.outlook.com\n\t(mail-sn1nam01on0084.outbound.protection.outlook.com [104.47.32.84])\n\tby dpdk.org (Postfix) with ESMTP id CAB167D05\n\tfor <dev@dpdk.org>; Tue, 4 Sep 2018 06:03:35 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1101.15; Tue, 4 Sep 2018 04:03:30 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=JOPF2NEMS2MQu17LoG5roAJUZ1ODsaEmlUE7APDV/8M=;\n\tb=oQsX/XtcOQ8obaoS/MwfJ3iS0A++BZaRZvamzPSg9CFIc6v99nQ3IV5pxuHRhAqg+nYSXT4WK0xCd5D+AZSTa2sp5SlTY0UypTgzrfCO5abH9W+Pq1ShwhPcY5NOzGO2LhpKUT0b5FaUWOXfByfxNMV9q6AqnTYnxcIg7qeBC1I=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <ajoseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Srisivasubramanian S <ssrinivasan@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tdev@dpdk.org, Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tAnoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tRagothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tTejasree Kondoj <kondoj.tejasree@caviumnetworks.com>", "Date": "Tue, 4 Sep 2018 09:29:11 +0530", "Message-Id": "<1536033560-21541-25-git-send-email-ajoseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "References": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:d::33) To BYAPR07MB4902.namprd07.prod.outlook.com\n\t(2603:10b6:a02:ef::25)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "6f300846-64b0-4d43-4e89-08d6121b6264", "X-Microsoft-Antispam": "BCL:0; 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"YlhXwqsucSQu21GTFIQ41SVZ7VJwdwGYAqjhf7e2AeBzWZPscwEwUafDS/6DRKIL2VgCOiQI+w4bV7T1ZBKB1rW1TzUr6H6pb5PuqhhMdvUeNAKzTxKVKYfsioqyWhO9a34fvJTjia/icKYzKJDk4vWzxWBltD6+V7Hb6DKCk8aXx10h7gnWbg0oxCtmhaPb/OLPVeUGOS16/irEdPD4eUrbCBqpf8iphVNGYH6S0DJagGBYZlozpVFH79UPhY2EOFxrv0Age1VCG78nsuPRlqDpJEeOfqGYDB3ywuibigcf0PxtM8yRvolJl/rJ0Mc1ACJDEiB5iSAvydgcT+bLr2TYcYr9KWybhQIaArslUNk=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Sep 2018 04:03:30.5224\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "6f300846-64b0-4d43-4e89-08d6121b6264", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR07MB4902", "Subject": "[dpdk-dev] [PATCH v2 24/33] common/cpt: add support for zuc and\n\tsnow3g", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\n\nAdding microcode interface for supporting ZUC and SNOW3G.\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/common/cpt/cpt_ucode.h | 618 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 618 insertions(+)", "diff": "diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h\nindex 6949d35..383dff2 100644\n--- a/drivers/common/cpt/cpt_ucode.h\n+++ b/drivers/common/cpt/cpt_ucode.h\n@@ -1164,6 +1164,618 @@ cpt_dec_hmac_prep(uint32_t flags,\n \treturn 0;\n }\n \n+static __rte_always_inline int\n+cpt_zuc_snow3g_enc_prep(uint32_t req_flags,\n+\t\t\tuint64_t d_offs,\n+\t\t\tuint64_t d_lens,\n+\t\t\tfc_params_t *params,\n+\t\t\tvoid *op,\n+\t\t\tvoid **prep_req)\n+{\n+\tuint32_t size;\n+\tint32_t inputlen, outputlen;\n+\tstruct cpt_ctx *cpt_ctx;\n+\tuint32_t mac_len = 0;\n+\tuint8_t snow3g, j;\n+\tstruct cpt_request_info *req;\n+\tbuf_ptr_t *buf_p;\n+\tuint32_t encr_offset = 0, auth_offset = 0;\n+\tuint32_t encr_data_len = 0, auth_data_len = 0;\n+\tint flags, iv_len = 16, m_size;\n+\tvoid *m_vaddr, *c_vaddr;\n+\tuint64_t m_dma, c_dma, offset_ctrl;\n+\tuint64_t *offset_vaddr, offset_dma;\n+\tuint32_t *iv_s, iv[4];\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tvq_cmd_word3_t vq_cmd_w3;\n+\topcode_info_t opcode;\n+\n+\tbuf_p = ¶ms->meta_buf;\n+\tm_vaddr = buf_p->vaddr;\n+\tm_dma = buf_p->dma_addr;\n+\tm_size = buf_p->size;\n+\n+\tcpt_ctx = params->ctx_buf.vaddr;\n+\tflags = cpt_ctx->zsk_flags;\n+\tmac_len = cpt_ctx->mac_len;\n+\tsnow3g = cpt_ctx->snow3g;\n+\n+\t/*\n+\t * Save initial space that followed app data for completion code &\n+\t * alternate completion code to fall in same cache line as app data\n+\t */\n+\tm_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;\n+\tm_dma += COMPLETION_CODE_SIZE;\n+\tsize = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -\n+\t\t(uint8_t *)m_vaddr;\n+\n+\tc_vaddr = (uint8_t *)m_vaddr + size;\n+\tc_dma = m_dma + size;\n+\tsize += sizeof(cpt_res_s_t);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Reserve memory for cpt request info */\n+\treq = m_vaddr;\n+\n+\tsize = sizeof(struct cpt_request_info);\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Initialising ctrl and opcode\n+\t * fields for cpt request\n+\t */\n+\n+\treq->se_req = SE_CORE_REQ;\n+\treq->dma_mode = CTRL_DMA_MODE_SGIO;\n+\n+\topcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;\n+\n+\t/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */\n+\topcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |\n+\t\t\t (0 << 3) | (flags & 0x7));\n+\n+\tif (flags == 0x1) {\n+\t\t/*\n+\t\t * Microcode expects offsets in bytes\n+\t\t * TODO: Rounding off\n+\t\t */\n+\t\tauth_data_len = AUTH_DLEN(d_lens);\n+\n+\t\t/* EIA3 or UIA2 */\n+\t\tauth_offset = AUTH_OFFSET(d_offs);\n+\t\tauth_offset = auth_offset / 8;\n+\n+\t\t/* consider iv len */\n+\t\tauth_offset += iv_len;\n+\n+\t\tinputlen = auth_offset +\n+\t\t\t(RTE_ALIGN(auth_data_len, 8) / 8);\n+\t\toutputlen = mac_len;\n+\n+\t\toffset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);\n+\n+\t} else {\n+\t\t/* EEA3 or UEA2 */\n+\t\t/*\n+\t\t * Microcode expects offsets in bytes\n+\t\t * TODO: Rounding off\n+\t\t */\n+\t\tencr_data_len = ENCR_DLEN(d_lens);\n+\n+\n+\t\tencr_offset = ENCR_OFFSET(d_offs);\n+\t\tencr_offset = encr_offset / 8;\n+\t\t/* consider iv len */\n+\t\tencr_offset += iv_len;\n+\n+\t\tinputlen = encr_offset +\n+\t\t\t(RTE_ALIGN(encr_data_len, 8) / 8);\n+\t\toutputlen = inputlen;\n+\n+\t\t/* iv offset is 0 */\n+\t\toffset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);\n+\t}\n+\n+\t/* IV */\n+\tiv_s = (flags == 0x1) ? params->auth_iv_buf :\n+\t\tparams->iv_buf;\n+\n+\tif (snow3g) {\n+\t\t/*\n+\t\t * DPDK seems to provide it in form of IV3 IV2 IV1 IV0\n+\t\t * and BigEndian, MC needs it as IV0 IV1 IV2 IV3\n+\t\t */\n+\n+\t\tfor (j = 0; j < 4; j++)\n+\t\t\tiv[j] = iv_s[3 - j];\n+\t} else {\n+\t\t/* ZUC doesn't need a swap */\n+\t\tfor (j = 0; j < 4; j++)\n+\t\t\tiv[j] = iv_s[j];\n+\t}\n+\n+\t/*\n+\t * GP op header, lengths are expected in bits.\n+\t */\n+\tvq_cmd_w0.u64 = 0;\n+\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);\n+\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);\n+\n+\t/*\n+\t * In 83XX since we have a limitation of\n+\t * IV & Offset control word not part of instruction\n+\t * and need to be part of Data Buffer, we check if\n+\t * head room is there and then only do the Direct mode processing\n+\t */\n+\tif (likely((req_flags & SINGLE_BUF_INPLACE) &&\n+\t\t (req_flags & SINGLE_BUF_HEADTAILROOM))) {\n+\t\tvoid *dm_vaddr = params->bufs[0].vaddr;\n+\t\tuint64_t dm_dma_addr = params->bufs[0].dma_addr;\n+\t\t/*\n+\t\t * This flag indicates that there is 24 bytes head room and\n+\t\t * 8 bytes tail room available, so that we get to do\n+\t\t * DIRECT MODE with limitation\n+\t\t */\n+\n+\t\toffset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -\n+\t\t\t\t\t OFF_CTRL_LEN - iv_len);\n+\t\toffset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;\n+\n+\t\t/* DPTR */\n+\t\treq->ist.ei1 = offset_dma;\n+\t\t/* RPTR should just exclude offset control word */\n+\t\treq->ist.ei2 = dm_dma_addr - iv_len;\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr\n+\t\t\t\t\t\t + outputlen - iv_len);\n+\n+\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);\n+\n+\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr\n+\t\t\t\t\t\t + OFF_CTRL_LEN);\n+\t\t\tmemcpy(iv_d, iv, 16);\n+\t\t}\n+\n+\t\t*offset_vaddr = offset_ctrl;\n+\t} else {\n+\t\tuint32_t i, g_size_bytes, s_size_bytes;\n+\t\tuint64_t dptr_dma, rptr_dma;\n+\t\tsg_comp_t *gather_comp;\n+\t\tsg_comp_t *scatter_comp;\n+\t\tuint8_t *in_buffer;\n+\t\tuint32_t *iv_d;\n+\n+\t\t/*save space for iv */\n+\t\toffset_vaddr = m_vaddr;\n+\t\toffset_dma = m_dma;\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;\n+\t\tm_dma += OFF_CTRL_LEN + iv_len;\n+\t\tm_size -= OFF_CTRL_LEN + iv_len;\n+\n+\t\topcode.s.major |= CPT_DMA_MODE;\n+\n+\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\n+\t\t/* DPTR has SG list */\n+\t\tin_buffer = m_vaddr;\n+\t\tdptr_dma = m_dma;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* TODO Add error check if space will be sufficient */\n+\t\tgather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);\n+\n+\t\t/*\n+\t\t * Input Gather List\n+\t\t */\n+\t\ti = 0;\n+\n+\t\t/* Offset control word followed by iv */\n+\n+\t\ti = fill_sg_comp(gather_comp, i, offset_dma,\n+\t\t\t\t offset_vaddr, OFF_CTRL_LEN + iv_len);\n+\n+\t\t/* iv offset is 0 */\n+\t\t*offset_vaddr = offset_ctrl;\n+\n+\t\tiv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);\n+\t\tmemcpy(iv_d, iv, 16);\n+\n+\t\t/* input data */\n+\t\tsize = inputlen - iv_len;\n+\t\tif (size) {\n+\n+\t\t\ti = fill_sg_comp_from_iov(gather_comp, i,\n+\t\t\t\t\t\t params->src_iov,\n+\t\t\t\t\t\t 0, &size, NULL, 0);\n+\t\t\tif (size)\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\t\tg_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\t/*\n+\t\t * Output Scatter List\n+\t\t */\n+\n+\t\ti = 0;\n+\t\tscatter_comp =\n+\t\t\t(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\tif (flags == 0x1) {\n+\t\t\t/* IV in SLIST only for EEA3 & UEA2 */\n+\t\t\tiv_len = 0;\n+\t\t}\n+\n+\t\tif (iv_len) {\n+\t\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t\t offset_dma + OFF_CTRL_LEN,\n+\t\t\t\t\t (uint8_t *)offset_vaddr + OFF_CTRL_LEN,\n+\t\t\t\t\t iv_len);\n+\t\t}\n+\n+\t\t/* Add output data */\n+\t\tif (req_flags & VALID_MAC_BUF) {\n+\t\t\tsize = outputlen - iv_len - mac_len;\n+\t\t\tif (size) {\n+\t\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t\t\t params->dst_iov, 0,\n+\t\t\t\t\t\t\t &size, NULL, 0);\n+\n+\t\t\t\tif (size)\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t}\n+\n+\t\t\t/* mac data */\n+\t\t\tif (mac_len) {\n+\t\t\t\ti = fill_sg_comp_from_buf(scatter_comp, i,\n+\t\t\t\t\t\t\t ¶ms->mac_buf);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* Output including mac */\n+\t\t\tsize = outputlen - iv_len;\n+\t\t\tif (size) {\n+\t\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t\t\t params->dst_iov, 0,\n+\t\t\t\t\t\t\t &size, NULL, 0);\n+\n+\t\t\t\tif (size)\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\t\ts_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n+\n+\t\t/* This is DPTR len incase of SG mode */\n+\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\t\tm_dma += size;\n+\t\tm_size -= size;\n+\n+\t\t/* cpt alternate completion address saved earlier */\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);\n+\t\t*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);\n+\t\trptr_dma = c_dma - 8;\n+\n+\t\treq->ist.ei1 = dptr_dma;\n+\t\treq->ist.ei2 = rptr_dma;\n+\t}\n+\n+\t/* First 16-bit swap then 64-bit swap */\n+\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n+\t * to eliminate all the swapping\n+\t */\n+\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n+\n+\t/* vq command w3 */\n+\tvq_cmd_w3.u64 = 0;\n+\tvq_cmd_w3.s.grp = 0;\n+\tvq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +\n+\t\toffsetof(struct cpt_ctx, zs_ctx);\n+\n+\t/* 16 byte aligned cpt res address */\n+\treq->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);\n+\t*req->completion_addr = COMPLETION_CODE_INIT;\n+\treq->comp_baddr = c_dma;\n+\n+\t/* Fill microcode part of instruction */\n+\treq->ist.ei0 = vq_cmd_w0.u64;\n+\treq->ist.ei3 = vq_cmd_w3.u64;\n+\n+\treq->op = op;\n+\n+\t*prep_req = req;\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+cpt_zuc_snow3g_dec_prep(uint32_t req_flags,\n+\t\t\tuint64_t d_offs,\n+\t\t\tuint64_t d_lens,\n+\t\t\tfc_params_t *params,\n+\t\t\tvoid *op,\n+\t\t\tvoid **prep_req)\n+{\n+\tuint32_t size;\n+\tint32_t inputlen = 0, outputlen;\n+\tstruct cpt_ctx *cpt_ctx;\n+\tuint8_t snow3g, iv_len = 16;\n+\tstruct cpt_request_info *req;\n+\tbuf_ptr_t *buf_p;\n+\tuint32_t encr_offset;\n+\tuint32_t encr_data_len;\n+\tint flags, m_size;\n+\tvoid *m_vaddr, *c_vaddr;\n+\tuint64_t m_dma, c_dma;\n+\tuint64_t *offset_vaddr, offset_dma;\n+\tuint32_t *iv_s, iv[4], j;\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tvq_cmd_word3_t vq_cmd_w3;\n+\topcode_info_t opcode;\n+\n+\t(void)req_flags;\n+\tbuf_p = ¶ms->meta_buf;\n+\tm_vaddr = buf_p->vaddr;\n+\tm_dma = buf_p->dma_addr;\n+\tm_size = buf_p->size;\n+\n+\t/*\n+\t * Microcode expects offsets in bytes\n+\t * TODO: Rounding off\n+\t */\n+\tencr_offset = ENCR_OFFSET(d_offs) / 8;\n+\tencr_data_len = ENCR_DLEN(d_lens);\n+\n+\tcpt_ctx = params->ctx_buf.vaddr;\n+\tflags = cpt_ctx->zsk_flags;\n+\tsnow3g = cpt_ctx->snow3g;\n+\t/*\n+\t * Save initial space that followed app data for completion code &\n+\t * alternate completion code to fall in same cache line as app data\n+\t */\n+\tm_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;\n+\tm_dma += COMPLETION_CODE_SIZE;\n+\tsize = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -\n+\t\t(uint8_t *)m_vaddr;\n+\n+\tc_vaddr = (uint8_t *)m_vaddr + size;\n+\tc_dma = m_dma + size;\n+\tsize += sizeof(cpt_res_s_t);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Reserve memory for cpt request info */\n+\treq = m_vaddr;\n+\n+\tsize = sizeof(struct cpt_request_info);\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Initialising ctrl and opcode\n+\t * fields for cpt request\n+\t */\n+\n+\treq->se_req = SE_CORE_REQ;\n+\treq->dma_mode = CTRL_DMA_MODE_SGIO;\n+\n+\topcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;\n+\n+\t/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */\n+\topcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |\n+\t\t\t (0 << 3) | (flags & 0x7));\n+\n+\t/* consider iv len */\n+\tencr_offset += iv_len;\n+\n+\tinputlen = encr_offset +\n+\t\t(RTE_ALIGN(encr_data_len, 8) / 8);\n+\toutputlen = inputlen;\n+\n+\t/* IV */\n+\tiv_s = params->iv_buf;\n+\tif (snow3g) {\n+\t\t/*\n+\t\t * DPDK seems to provide it in form of IV3 IV2 IV1 IV0\n+\t\t * and BigEndian, MC needs it as IV0 IV1 IV2 IV3\n+\t\t */\n+\n+\t\tfor (j = 0; j < 4; j++)\n+\t\t\tiv[j] = iv_s[3 - j];\n+\t} else {\n+\t\t/* ZUC doesn't need a swap */\n+\t\tfor (j = 0; j < 4; j++)\n+\t\t\tiv[j] = iv_s[j];\n+\t}\n+\n+\t/*\n+\t * GP op header, lengths are expected in bits.\n+\t */\n+\tvq_cmd_w0.u64 = 0;\n+\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);\n+\n+\t/*\n+\t * In 83XX since we have a limitation of\n+\t * IV & Offset control word not part of instruction\n+\t * and need to be part of Data Buffer, we check if\n+\t * head room is there and then only do the Direct mode processing\n+\t */\n+\tif (likely((req_flags & SINGLE_BUF_INPLACE) &&\n+\t\t (req_flags & SINGLE_BUF_HEADTAILROOM))) {\n+\t\tvoid *dm_vaddr = params->bufs[0].vaddr;\n+\t\tuint64_t dm_dma_addr = params->bufs[0].dma_addr;\n+\t\t/*\n+\t\t * This flag indicates that there is 24 bytes head room and\n+\t\t * 8 bytes tail room available, so that we get to do\n+\t\t * DIRECT MODE with limitation\n+\t\t */\n+\n+\t\toffset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -\n+\t\t\t\t\t OFF_CTRL_LEN - iv_len);\n+\t\toffset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;\n+\n+\t\t/* DPTR */\n+\t\treq->ist.ei1 = offset_dma;\n+\t\t/* RPTR should just exclude offset control word */\n+\t\treq->ist.ei2 = dm_dma_addr - iv_len;\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr\n+\t\t\t\t\t\t + outputlen - iv_len);\n+\n+\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);\n+\n+\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr\n+\t\t\t\t\t\t + OFF_CTRL_LEN);\n+\t\t\tmemcpy(iv_d, iv, 16);\n+\t\t}\n+\n+\t\t/* iv offset is 0 */\n+\t\t*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);\n+\t} else {\n+\t\tuint32_t i, g_size_bytes, s_size_bytes;\n+\t\tuint64_t dptr_dma, rptr_dma;\n+\t\tsg_comp_t *gather_comp;\n+\t\tsg_comp_t *scatter_comp;\n+\t\tuint8_t *in_buffer;\n+\t\tuint32_t *iv_d;\n+\n+\t\t/* save space for offset and iv... */\n+\t\toffset_vaddr = m_vaddr;\n+\t\toffset_dma = m_dma;\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;\n+\t\tm_dma += OFF_CTRL_LEN + iv_len;\n+\t\tm_size -= OFF_CTRL_LEN + iv_len;\n+\n+\t\topcode.s.major |= CPT_DMA_MODE;\n+\n+\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\n+\t\t/* DPTR has SG list */\n+\t\tin_buffer = m_vaddr;\n+\t\tdptr_dma = m_dma;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* TODO Add error check if space will be sufficient */\n+\t\tgather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);\n+\n+\t\t/*\n+\t\t * Input Gather List\n+\t\t */\n+\t\ti = 0;\n+\n+\t\t/* Offset control word */\n+\n+\t\t/* iv offset is 0 */\n+\t\t*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);\n+\n+\t\ti = fill_sg_comp(gather_comp, i, offset_dma, offset_vaddr,\n+\t\t\t\t OFF_CTRL_LEN + iv_len);\n+\n+\t\tiv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);\n+\t\tmemcpy(iv_d, iv, 16);\n+\n+\t\t/* Add input data */\n+\t\tsize = inputlen - iv_len;\n+\t\tif (size) {\n+\t\t\ti = fill_sg_comp_from_iov(gather_comp, i,\n+\t\t\t\t\t\t params->src_iov,\n+\t\t\t\t\t\t 0, &size, NULL, 0);\n+\t\t\tif (size)\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\t\tg_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\t/*\n+\t\t * Output Scatter List\n+\t\t */\n+\n+\t\ti = 0;\n+\t\tscatter_comp =\n+\t\t\t(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\t/* IV */\n+\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t offset_dma + OFF_CTRL_LEN,\n+\t\t\t\t (uint8_t *)offset_vaddr + OFF_CTRL_LEN,\n+\t\t\t\t iv_len);\n+\n+\t\t/* Add output data */\n+\t\tsize = outputlen - iv_len;\n+\t\tif (size) {\n+\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t\t params->dst_iov, 0,\n+\t\t\t\t\t\t &size, NULL, 0);\n+\n+\t\t\tif (size)\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\t\ts_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n+\n+\t\t/* This is DPTR len incase of SG mode */\n+\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\t\tm_dma += size;\n+\t\tm_size -= size;\n+\n+\t\t/* cpt alternate completion address saved earlier */\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);\n+\t\t*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);\n+\t\trptr_dma = c_dma - 8;\n+\n+\t\treq->ist.ei1 = dptr_dma;\n+\t\treq->ist.ei2 = rptr_dma;\n+\t}\n+\n+\t/* First 16-bit swap then 64-bit swap */\n+\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n+\t * to eliminate all the swapping\n+\t */\n+\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n+\n+\t/* vq command w3 */\n+\tvq_cmd_w3.u64 = 0;\n+\tvq_cmd_w3.s.grp = 0;\n+\tvq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +\n+\t\toffsetof(struct cpt_ctx, zs_ctx);\n+\n+\t/* 16 byte aligned cpt res address */\n+\treq->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);\n+\t*req->completion_addr = COMPLETION_CODE_INIT;\n+\treq->comp_baddr = c_dma;\n+\n+\t/* Fill microcode part of instruction */\n+\treq->ist.ei0 = vq_cmd_w0.u64;\n+\treq->ist.ei3 = vq_cmd_w3.u64;\n+\n+\treq->op = op;\n+\n+\t*prep_req = req;\n+\treturn 0;\n+}\n+\n static __rte_always_inline void *\n cpt_fc_dec_hmac_prep(uint32_t flags,\n \t\t uint64_t d_offs,\n@@ -1181,6 +1793,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags,\n \tif (likely(fc_type == FC_GEN)) {\n \t\tret = cpt_dec_hmac_prep(flags, d_offs, d_lens,\n \t\t\t\t\tfc_params, op, &prep_req);\n+\t} else if (fc_type == ZUC_SNOW3G) {\n+\t\tret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,\n+\t\t\t\t\t fc_params, op, &prep_req);\n \t} else {\n \t\t/*\n \t\t * For AUTH_ONLY case,\n@@ -1211,6 +1826,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \tif (likely(fc_type == FC_GEN)) {\n \t\tret = cpt_enc_hmac_prep(flags, d_offs, d_lens,\n \t\t\t\t\tfc_params, op, &prep_req);\n+\t} else if (fc_type == ZUC_SNOW3G) {\n+\t\tret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,\n+\t\t\t\t\t fc_params, op, &prep_req);\n \t} else {\n \t\tret = ERR_EIO;\n \t}\n", "prefixes": [ "v2", "24/33" ] }