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GET /api/patches/44201/?format=api
{ "id": 44201, "url": "http://patches.dpdk.org/api/patches/44201/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-22-git-send-email-ajoseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536033560-21541-22-git-send-email-ajoseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536033560-21541-22-git-send-email-ajoseph@caviumnetworks.com", "date": "2018-09-04T03:59:08", "name": "[v2,21/33] common/cpt: add microcode interface for encryption", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9d49059c18722061f65915232a6c1a091e7badf7", "submitter": { "id": 891, "url": "http://patches.dpdk.org/api/people/891/?format=api", "name": "Anoob Joseph", "email": "ajoseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-22-git-send-email-ajoseph@caviumnetworks.com/mbox/", "series": [ { "id": 1164, "url": "http://patches.dpdk.org/api/series/1164/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1164", "date": "2018-09-04T03:58:47", "name": "Adding Cavium's OcteonTX crypto PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/1164/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44201/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/44201/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CBA197EB4;\n\tTue, 4 Sep 2018 06:03:36 +0200 (CEST)", "from NAM02-CY1-obe.outbound.protection.outlook.com\n\t(mail-cys01nam02on0067.outbound.protection.outlook.com\n\t[104.47.37.67]) by dpdk.org (Postfix) with ESMTP id C92D55B2E\n\tfor <dev@dpdk.org>; Tue, 4 Sep 2018 06:03:21 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1101.15; Tue, 4 Sep 2018 04:03:16 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=ddgCZ6JKDkkxkDCWWU0fiq+3eF4kuSM9FDGsZM3qM2I=;\n\tb=T4vkImUEcYuFR0ykNYduAsLE2HBbYo9NeMdRHWYP73WXoyb052DLJtlCIZFbmxsM/LlZZNbjMzHHsxWlq/XlgcsPmuFQ32ExdtkhcGHGo7vCBnPmYlSUjwgWOOXuj08pmXeUtRbcc50w35LBQksHE+Fp3nRPxJpKInjhkrOCJ2E=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <ajoseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tdev@dpdk.org, Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tAnoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tSrisivasubramanian S <ssrinivasan@caviumnetworks.com>,\n\tTejasree Kondoj <kondoj.tejasree@caviumnetworks.com>", "Date": "Tue, 4 Sep 2018 09:29:08 +0530", "Message-Id": "<1536033560-21541-22-git-send-email-ajoseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "References": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:d::33) To BYAPR07MB4902.namprd07.prod.outlook.com\n\t(2603:10b6:a02:ef::25)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "a658f027-811b-4b21-d84e-08d6121b59f1", "X-Microsoft-Antispam": "BCL:0; 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"BGKxpY+f4SxnUJHxgfXlOL/XXFZS+0Yg2Luf75fHD4XU65/t9G+PL+WuWw9qC/NFvJzFERXWOrUB42qaIsdbjKze55MAivIA74UmNN/2bp1nlNKLFkc6A4Sx0aHr0KNIaxmamXj3ELlSnuEex1Y0b3w1Rfh/1fEEgcKOcv0IdbLt1FPrtVMsI4f6eOIXpugiQGH2llseieSxfmF6u1SRn/WNyOkOxE3IpNt0uA0KYVl6wF94PuGYIKhZyahSY5T0OYuNF/1TT00k8H/uO55f2IR6Dh7lHtxrKuNm6l+nNQCzVuiAK5PcS+wCYrDmtom0wSYQwyGn6ERvyMDFHQFSPnnCKyGsM6iMC0afgNTcwak=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Sep 2018 04:03:16.3661\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "a658f027-811b-4b21-d84e-08d6121b59f1", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR07MB4902", "Subject": "[dpdk-dev] [PATCH v2 21/33] common/cpt: add microcode interface for\n\tencryption", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\n\nAdding microcode interface additions for supporting encryption.\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/common/cpt/cpt_ucode.h | 1003 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 1003 insertions(+)", "diff": "diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h\nindex a9aef68..add5f95 100644\n--- a/drivers/common/cpt/cpt_ucode.h\n+++ b/drivers/common/cpt/cpt_ucode.h\n@@ -5,6 +5,10 @@\n #ifndef _CPT_UCODE_H_\n #define _CPT_UCODE_H_\n \n+#include <stdbool.h>\n+\n+#include \"cpt_common.h\"\n+#include \"cpt_hw_types.h\"\n #include \"cpt_mcode_defines.h\"\n \n /*\n@@ -64,6 +68,14 @@ gen_key_snow3g(uint8_t *ck, uint32_t *keyx)\n \t}\n }\n \n+static __rte_always_inline void\n+cpt_fc_salt_update(void *ctx,\n+\t\t uint8_t *salt)\n+{\n+\tstruct cpt_ctx *cpt_ctx = ctx;\n+\tmemcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4);\n+}\n+\n static __rte_always_inline int\n cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key,\n \t\t uint16_t key_len, uint8_t *salt)\n@@ -217,6 +229,564 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key,\n \treturn 0;\n }\n \n+static __rte_always_inline uint32_t\n+fill_sg_comp(sg_comp_t *list,\n+\t uint32_t i,\n+\t phys_addr_t dma_addr,\n+\t void *vaddr,\n+\t uint32_t size)\n+{\n+\tsg_comp_t *to = &list[i>>2];\n+\n+\tto->u.s.len[i%4] = rte_cpu_to_be_16(size);\n+\tto->ptr[i%4] = rte_cpu_to_be_64(dma_addr);\n+\t(void) vaddr;\n+\ti++;\n+\treturn i;\n+}\n+\n+static __rte_always_inline uint32_t\n+fill_sg_comp_from_buf(sg_comp_t *list,\n+\t\t uint32_t i,\n+\t\t buf_ptr_t *from)\n+{\n+\tsg_comp_t *to = &list[i>>2];\n+\n+\tto->u.s.len[i%4] = rte_cpu_to_be_16(from->size);\n+\tto->ptr[i%4] = rte_cpu_to_be_64(from->dma_addr);\n+\ti++;\n+\treturn i;\n+}\n+\n+static __rte_always_inline uint32_t\n+fill_sg_comp_from_buf_min(sg_comp_t *list,\n+\t\t\t uint32_t i,\n+\t\t\t buf_ptr_t *from,\n+\t\t\t uint32_t *psize)\n+{\n+\tsg_comp_t *to = &list[i >> 2];\n+\tuint32_t size = *psize;\n+\tuint32_t e_len;\n+\n+\te_len = (size > from->size) ? from->size : size;\n+\tto->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);\n+\tto->ptr[i % 4] = rte_cpu_to_be_64(from->dma_addr);\n+\t*psize -= e_len;\n+\ti++;\n+\treturn i;\n+}\n+\n+/*\n+ * This fills the MC expected SGIO list\n+ * from IOV given by user.\n+ */\n+static __rte_always_inline uint32_t\n+fill_sg_comp_from_iov(sg_comp_t *list,\n+\t\t uint32_t i,\n+\t\t iov_ptr_t *from, uint32_t from_offset,\n+\t\t uint32_t *psize, buf_ptr_t *extra_buf,\n+\t\t uint32_t extra_offset)\n+{\n+\tint32_t j;\n+\tuint32_t extra_len = extra_buf ? extra_buf->size : 0;\n+\tuint32_t size = *psize - extra_len;\n+\tbuf_ptr_t *bufs;\n+\n+\tbufs = from->bufs;\n+\tfor (j = 0; (j < from->buf_cnt) && size; j++) {\n+\t\tphys_addr_t e_dma_addr;\n+\t\tuint32_t e_len;\n+\t\tsg_comp_t *to = &list[i >> 2];\n+\n+\t\tif (!bufs[j].size)\n+\t\t\tcontinue;\n+\n+\t\tif (unlikely(from_offset)) {\n+\t\t\tif (from_offset >= bufs[j].size) {\n+\t\t\t\tfrom_offset -= bufs[j].size;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\te_dma_addr = bufs[j].dma_addr + from_offset;\n+\t\t\te_len = (size > (bufs[j].size - from_offset)) ?\n+\t\t\t\t(bufs[j].size - from_offset) : size;\n+\t\t\tfrom_offset = 0;\n+\t\t} else {\n+\t\t\te_dma_addr = bufs[j].dma_addr;\n+\t\t\te_len = (size > bufs[j].size) ?\n+\t\t\t\tbufs[j].size : size;\n+\t\t}\n+\n+\t\tto->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);\n+\t\tto->ptr[i % 4] = rte_cpu_to_be_64(e_dma_addr);\n+\n+\t\tif (extra_len && (e_len >= extra_offset)) {\n+\t\t\t/* Break the data at given offset */\n+\t\t\tuint32_t next_len = e_len - extra_offset;\n+\t\t\tphys_addr_t next_dma = e_dma_addr + extra_offset;\n+\n+\t\t\tif (!extra_offset) {\n+\t\t\t\ti--;\n+\t\t\t} else {\n+\t\t\t\te_len = extra_offset;\n+\t\t\t\tsize -= e_len;\n+\t\t\t\tto->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);\n+\t\t\t}\n+\n+\t\t\t/* Insert extra data ptr */\n+\t\t\tif (extra_len) {\n+\t\t\t\ti++;\n+\t\t\t\tto = &list[i >> 2];\n+\t\t\t\tto->u.s.len[i % 4] =\n+\t\t\t\t\trte_cpu_to_be_16(extra_buf->size);\n+\t\t\t\tto->ptr[i % 4] =\n+\t\t\t\t\trte_cpu_to_be_64(extra_buf->dma_addr);\n+\n+\t\t\t\t/* size already decremented by extra len */\n+\t\t\t}\n+\n+\t\t\t/* insert the rest of the data */\n+\t\t\tif (next_len) {\n+\t\t\t\ti++;\n+\t\t\t\tto = &list[i >> 2];\n+\t\t\t\tto->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);\n+\t\t\t\tto->ptr[i % 4] = rte_cpu_to_be_64(next_dma);\n+\t\t\t\tsize -= next_len;\n+\t\t\t}\n+\t\t\textra_len = 0;\n+\n+\t\t} else {\n+\t\t\tsize -= e_len;\n+\t\t}\n+\t\tif (extra_offset)\n+\t\t\textra_offset -= size;\n+\t\ti++;\n+\t}\n+\n+\t*psize = size;\n+\treturn (uint32_t)i;\n+}\n+\n+static __rte_always_inline int\n+cpt_enc_hmac_prep(uint32_t flags,\n+\t\t uint64_t d_offs,\n+\t\t uint64_t d_lens,\n+\t\t fc_params_t *fc_params,\n+\t\t void *op,\n+\t\t void **prep_req)\n+{\n+\tuint32_t iv_offset = 0;\n+\tint32_t inputlen, outputlen, enc_dlen, auth_dlen;\n+\tstruct cpt_ctx *cpt_ctx;\n+\tuint32_t cipher_type, hash_type;\n+\tuint32_t mac_len, size;\n+\tuint8_t iv_len = 16;\n+\tstruct cpt_request_info *req;\n+\tbuf_ptr_t *meta_p, *aad_buf = NULL;\n+\tuint32_t encr_offset, auth_offset;\n+\tuint32_t encr_data_len, auth_data_len, aad_len = 0;\n+\tuint32_t passthrough_len = 0;\n+\tvoid *m_vaddr, *offset_vaddr;\n+\tuint64_t m_dma, offset_dma, ctx_dma;\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tvq_cmd_word3_t vq_cmd_w3;\n+\tvoid *c_vaddr;\n+\tuint64_t c_dma;\n+\tint32_t m_size;\n+\topcode_info_t opcode;\n+\n+\tmeta_p = &fc_params->meta_buf;\n+\tm_vaddr = meta_p->vaddr;\n+\tm_dma = meta_p->dma_addr;\n+\tm_size = meta_p->size;\n+\n+\tencr_offset = ENCR_OFFSET(d_offs);\n+\tauth_offset = AUTH_OFFSET(d_offs);\n+\tencr_data_len = ENCR_DLEN(d_lens);\n+\tauth_data_len = AUTH_DLEN(d_lens);\n+\tif (unlikely(flags & VALID_AAD_BUF)) {\n+\t\t/*\n+\t\t * We dont support both aad\n+\t\t * and auth data separately\n+\t\t */\n+\t\tauth_data_len = 0;\n+\t\tauth_offset = 0;\n+\t\taad_len = fc_params->aad_buf.size;\n+\t\taad_buf = &fc_params->aad_buf;\n+\t}\n+\tcpt_ctx = fc_params->ctx_buf.vaddr;\n+\tcipher_type = cpt_ctx->enc_cipher;\n+\thash_type = cpt_ctx->hash_type;\n+\tmac_len = cpt_ctx->mac_len;\n+\n+\t/*\n+\t * Save initial space that followed app data for completion code &\n+\t * alternate completion code to fall in same cache line as app data\n+\t */\n+\tm_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;\n+\tm_dma += COMPLETION_CODE_SIZE;\n+\tsize = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -\n+\t\t(uint8_t *)m_vaddr;\n+\n+\tc_vaddr = (uint8_t *)m_vaddr + size;\n+\tc_dma = m_dma + size;\n+\tsize += sizeof(cpt_res_s_t);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* start cpt request info struct at 8 byte boundary */\n+\tsize = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -\n+\t\t(uint8_t *)m_vaddr;\n+\n+\treq = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);\n+\n+\tsize += sizeof(struct cpt_request_info);\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\tif (hash_type == GMAC_TYPE)\n+\t\tencr_data_len = 0;\n+\n+\tif (unlikely(!(flags & VALID_IV_BUF))) {\n+\t\tiv_len = 0;\n+\t\tiv_offset = ENCR_IV_OFFSET(d_offs);\n+\t}\n+\n+\tif (unlikely(flags & VALID_AAD_BUF)) {\n+\t\t/*\n+\t\t * When AAD is given, data above encr_offset is pass through\n+\t\t * Since AAD is given as separate pointer and not as offset,\n+\t\t * this is a special case as we need to fragment input data\n+\t\t * into passthrough + encr_data and then insert AAD in between.\n+\t\t */\n+\t\tif (hash_type != GMAC_TYPE) {\n+\t\t\tpassthrough_len = encr_offset;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tencr_offset = passthrough_len + aad_len + iv_len;\n+\t\t\tauth_data_len = aad_len + encr_data_len;\n+\t\t} else {\n+\t\t\tpassthrough_len = 16 + aad_len;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tauth_data_len = aad_len;\n+\t\t}\n+\t} else {\n+\t\tencr_offset += iv_len;\n+\t\tauth_offset += iv_len;\n+\t}\n+\n+\t/* Initialising ctrl and opcode\n+\t * fields in cpt request structure\n+\t */\n+\n+\treq->se_req = SE_CORE_REQ;\n+\t/*\n+\t * We are using DMA mode but indicate that\n+\t * SGIO list is already populated.\n+\t */\n+\treq->dma_mode = CTRL_DMA_MODE_SGIO;\n+\n+\t/* Encryption */\n+\topcode.s.major = CPT_MAJOR_OP_FC;\n+\topcode.s.minor = 0;\n+\n+\tauth_dlen = auth_offset + auth_data_len;\n+\tenc_dlen = encr_data_len + encr_offset;\n+\tif (unlikely(encr_data_len & 0xf)) {\n+\t\tif ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))\n+\t\t\tenc_dlen = ROUNDUP8(encr_data_len) + encr_offset;\n+\t\telse if (likely((cipher_type == AES_CBC) ||\n+\t\t\t\t(cipher_type == AES_ECB)))\n+\t\t\tenc_dlen = ROUNDUP16(encr_data_len) + encr_offset;\n+\t}\n+\n+\tif (unlikely(hash_type == GMAC_TYPE)) {\n+\t\tencr_offset = auth_dlen;\n+\t\tenc_dlen = 0;\n+\t}\n+\n+\tif (unlikely(auth_dlen > enc_dlen)) {\n+\t\tinputlen = auth_dlen;\n+\t\toutputlen = auth_dlen + mac_len;\n+\t} else {\n+\t\tinputlen = enc_dlen;\n+\t\toutputlen = enc_dlen + mac_len;\n+\t}\n+\n+\t/*GP op header */\n+\tvq_cmd_w0.u64 = 0;\n+\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);\n+\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);\n+\t/*\n+\t * In 83XX since we have a limitation of\n+\t * IV & Offset control word not part of instruction\n+\t * and need to be part of Data Buffer, we check if\n+\t * head room is there and then only do the Direct mode processing\n+\t */\n+\tif (likely((flags & SINGLE_BUF_INPLACE) &&\n+\t\t (flags & SINGLE_BUF_HEADTAILROOM))) {\n+\t\tvoid *dm_vaddr = fc_params->bufs[0].vaddr;\n+\t\tuint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;\n+\t\t/*\n+\t\t * This flag indicates that there is 24 bytes head room and\n+\t\t * 8 bytes tail room available, so that we get to do\n+\t\t * DIRECT MODE with limitation\n+\t\t */\n+\n+\t\toffset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;\n+\t\toffset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;\n+\n+\t\t/* DPTR */\n+\t\treq->ist.ei1 = offset_dma;\n+\t\t/* RPTR should just exclude offset control word */\n+\t\treq->ist.ei2 = dm_dma_addr - iv_len;\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr\n+\t\t\t\t\t\t + outputlen - iv_len);\n+\n+\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);\n+\n+\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr\n+\t\t\t\t\t\t + OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t\t*(uint64_t *)offset_vaddr =\n+\t\t\trte_cpu_to_be_64(((uint64_t)encr_offset << 16) |\n+\t\t\t\t((uint64_t)iv_offset << 8) |\n+\t\t\t\t((uint64_t)auth_offset));\n+\n+\t} else {\n+\t\tuint32_t i, g_size_bytes, s_size_bytes;\n+\t\tuint64_t dptr_dma, rptr_dma;\n+\t\tsg_comp_t *gather_comp;\n+\t\tsg_comp_t *scatter_comp;\n+\t\tuint8_t *in_buffer;\n+\n+\t\t/* This falls under strict SG mode */\n+\t\toffset_vaddr = m_vaddr;\n+\t\toffset_dma = m_dma;\n+\t\tsize = OFF_CTRL_LEN + iv_len;\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\t\tm_dma += size;\n+\t\tm_size -= size;\n+\n+\t\topcode.s.major |= CPT_DMA_MODE;\n+\n+\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr\n+\t\t\t\t\t\t + OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t\t*(uint64_t *)offset_vaddr =\n+\t\t\trte_cpu_to_be_64(((uint64_t)encr_offset << 16) |\n+\t\t\t\t((uint64_t)iv_offset << 8) |\n+\t\t\t\t((uint64_t)auth_offset));\n+\n+\t\t/* DPTR has SG list */\n+\t\tin_buffer = m_vaddr;\n+\t\tdptr_dma = m_dma;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* TODO Add error check if space will be sufficient */\n+\t\tgather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);\n+\n+\t\t/*\n+\t\t * Input Gather List\n+\t\t */\n+\n+\t\ti = 0;\n+\n+\t\t/* Offset control word that includes iv */\n+\t\ti = fill_sg_comp(gather_comp, i, offset_dma,\n+\t\t\t\t offset_vaddr, OFF_CTRL_LEN + iv_len);\n+\n+\t\t/* Add input data */\n+\t\tsize = inputlen - iv_len;\n+\t\tif (likely(size)) {\n+\t\t\tuint32_t aad_offset = aad_len ? passthrough_len : 0;\n+\n+\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\ti = fill_sg_comp_from_buf_min(gather_comp, i,\n+\t\t\t\t\t\t\t fc_params->bufs,\n+\t\t\t\t\t\t\t &size);\n+\t\t\t} else {\n+\n+\t\t\t\ti = fill_sg_comp_from_iov(gather_comp, i,\n+\t\t\t\t\t\t\t fc_params->src_iov,\n+\t\t\t\t\t\t\t 0, &size,\n+\t\t\t\t\t\t\t aad_buf, aad_offset);\n+\t\t\t}\n+\n+\t\t\tif (unlikely(size)) {\n+\t\t\t\tCPT_LOG_DP_ERR(\"Insufficient buffer space,\"\n+\t\t\t\t\t \" size %d need\\n\", size);\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\t\tg_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\t/*\n+\t\t * Output Scatter list\n+\t\t */\n+\t\ti = 0;\n+\t\tscatter_comp =\n+\t\t\t(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\t/* Add IV */\n+\t\tif (likely(iv_len)) {\n+\t\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t\t offset_dma + OFF_CTRL_LEN,\n+\t\t\t\t\t (uint8_t *)offset_vaddr + OFF_CTRL_LEN,\n+\t\t\t\t\t iv_len);\n+\t\t}\n+\n+\t\t/* output data or output data + digest*/\n+\t\tif (unlikely(flags & VALID_MAC_BUF)) {\n+\t\t\tsize = outputlen - iv_len - mac_len;\n+\t\t\tif (size) {\n+\t\t\t\tuint32_t aad_offset =\n+\t\t\t\t\taad_len ? passthrough_len : 0;\n+\n+\t\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\t\t\tscatter_comp,\n+\t\t\t\t\t\t\t\ti,\n+\t\t\t\t\t\t\t\tfc_params->bufs,\n+\t\t\t\t\t\t\t\t&size);\n+\t\t\t\t} else {\n+\t\t\t\t\ti = fill_sg_comp_from_iov(scatter_comp,\n+\t\t\t\t\t\t\t\ti,\n+\t\t\t\t\t\t\t fc_params->dst_iov,\n+\t\t\t\t\t\t\t\t0,\n+\t\t\t\t\t\t\t\t&size,\n+\t\t\t\t\t\t\t\taad_buf,\n+\t\t\t\t\t\t\t\taad_offset);\n+\t\t\t\t}\n+\t\t\t\tif (size)\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t}\n+\t\t\t/* mac_data */\n+\t\t\tif (mac_len) {\n+\t\t\t\ti = fill_sg_comp_from_buf(scatter_comp, i,\n+\t\t\t\t\t\t\t &fc_params->mac_buf);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* Output including mac */\n+\t\t\tsize = outputlen - iv_len;\n+\t\t\tif (likely(size)) {\n+\t\t\t\tuint32_t aad_offset =\n+\t\t\t\t\taad_len ? passthrough_len : 0;\n+\n+\t\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\t\t\tscatter_comp,\n+\t\t\t\t\t\t\t\ti,\n+\t\t\t\t\t\t\t\tfc_params->bufs,\n+\t\t\t\t\t\t\t\t&size);\n+\t\t\t\t} else {\n+\t\t\t\t\ti = fill_sg_comp_from_iov(scatter_comp,\n+\t\t\t\t\t\t\t\ti,\n+\t\t\t\t\t\t\t fc_params->dst_iov,\n+\t\t\t\t\t\t\t\t0,\n+\t\t\t\t\t\t\t\t&size,\n+\t\t\t\t\t\t\t\taad_buf,\n+\t\t\t\t\t\t\t\taad_offset);\n+\t\t\t\t}\n+\t\t\t\tif (unlikely(size)) {\n+\t\t\t\t\tCPT_LOG_DP_ERR(\"Insufficient \"\n+\t\t\t\t\t\"buffer space, size %d need\\n\", size);\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\t\ts_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n+\n+\t\t/* This is DPTR len incase of SG mode */\n+\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\t\tm_dma += size;\n+\t\tm_size -= size;\n+\n+\t\t/* cpt alternate completion address saved earlier */\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);\n+\t\t*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);\n+\t\trptr_dma = c_dma - 8;\n+\n+\t\treq->ist.ei1 = dptr_dma;\n+\t\treq->ist.ei2 = rptr_dma;\n+\t}\n+\n+\t/* First 16-bit swap then 64-bit swap */\n+\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n+\t * to eliminate all the swapping\n+\t */\n+\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n+\n+\tctx_dma = fc_params->ctx_buf.dma_addr +\n+\t\toffsetof(struct cpt_ctx, fctx);\n+\t/* vq command w3 */\n+\tvq_cmd_w3.u64 = 0;\n+\tvq_cmd_w3.s.grp = 0;\n+\tvq_cmd_w3.s.cptr = ctx_dma;\n+\n+\t/* 16 byte aligned cpt res address */\n+\treq->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);\n+\t*req->completion_addr = COMPLETION_CODE_INIT;\n+\treq->comp_baddr = c_dma;\n+\n+\t/* Fill microcode part of instruction */\n+\treq->ist.ei0 = vq_cmd_w0.u64;\n+\treq->ist.ei3 = vq_cmd_w3.u64;\n+\n+\treq->op = op;\n+\n+\t*prep_req = req;\n+\treturn 0;\n+}\n+\n+static __rte_always_inline void *__hot\n+cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n+\t\t fc_params_t *fc_params, void *op, int *ret_val)\n+{\n+\tstruct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;\n+\tuint8_t fc_type;\n+\tvoid *prep_req = NULL;\n+\tint ret;\n+\n+\tfc_type = ctx->fc_type;\n+\n+\t/* Common api for rest of the ops */\n+\tif (likely(fc_type == FC_GEN)) {\n+\t\tret = cpt_enc_hmac_prep(flags, d_offs, d_lens,\n+\t\t\t\t\tfc_params, op, &prep_req);\n+\t} else {\n+\t\tret = ERR_EIO;\n+\t}\n+\n+\tif (unlikely(!prep_req))\n+\t\t*ret_val = ret;\n+\treturn prep_req;\n+}\n+\n static __rte_always_inline int\n cpt_fc_auth_set_key(void *ctx, auth_type_t type, uint8_t *key,\n \t\t uint16_t key_len, uint16_t mac_len)\n@@ -618,4 +1188,437 @@ fill_sess_gmac(struct rte_crypto_sym_xform *xform,\n \treturn 0;\n }\n \n+static __rte_always_inline void *\n+alloc_op_meta(struct rte_mbuf *m_src,\n+\t buf_ptr_t *buf,\n+\t int32_t len,\n+\t struct rte_mempool *cpt_meta_pool)\n+{\n+\tuint8_t *mdata;\n+\n+#ifndef CPT_ALWAYS_USE_SEPARATE_BUF\n+\tif (likely(m_src && (m_src->nb_segs == 1))) {\n+\t\tint32_t tailroom;\n+\t\tphys_addr_t mphys;\n+\n+\t\t/* Check if tailroom is sufficient to hold meta data */\n+\t\ttailroom = rte_pktmbuf_tailroom(m_src);\n+\t\tif (likely(tailroom > len + 8)) {\n+\t\t\tmdata = (uint8_t *)m_src->buf_addr + m_src->buf_len;\n+\t\t\tmphys = m_src->buf_physaddr + m_src->buf_len;\n+\t\t\tmdata -= len;\n+\t\t\tmphys -= len;\n+\t\t\tbuf->vaddr = mdata;\n+\t\t\tbuf->dma_addr = mphys;\n+\t\t\tbuf->size = len;\n+\t\t\t/* Indicate that this is a mbuf allocated mdata */\n+\t\t\tmdata = (uint8_t *)((uint64_t)mdata | 1ull);\n+\t\t\treturn mdata;\n+\t\t}\n+\t}\n+#else\n+\t(void) m_src;\n+#endif\n+\n+\tif (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))\n+\t\treturn NULL;\n+\n+\tbuf->vaddr = mdata;\n+\tbuf->dma_addr = rte_mempool_virt2iova(mdata);\n+\tbuf->size = len;\n+\n+\treturn mdata;\n+}\n+\n+/**\n+ * cpt_free_metabuf - free metabuf to mempool.\n+ * @param instance: pointer to instance.\n+ * @param objp: pointer to the metabuf.\n+ */\n+static __rte_always_inline void\n+free_op_meta(void *mdata, struct rte_mempool *cpt_meta_pool)\n+{\n+\tbool nofree = ((uintptr_t)mdata & 1ull);\n+\n+\tif (likely(nofree))\n+\t\treturn;\n+\trte_mempool_put(cpt_meta_pool, mdata);\n+}\n+\n+static __rte_always_inline uint32_t\n+prepare_iov_from_pkt(struct rte_mbuf *pkt,\n+\t\t iov_ptr_t *iovec, uint32_t start_offset)\n+{\n+\tuint16_t index = 0;\n+\tvoid *seg_data = NULL;\n+\tphys_addr_t seg_phys;\n+\tint32_t seg_size = 0;\n+\n+\tif (!pkt) {\n+\t\tiovec->buf_cnt = 0;\n+\t\treturn 0;\n+\t}\n+\n+\tif (!start_offset) {\n+\t\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n+\t\tseg_phys = rte_pktmbuf_mtophys(pkt);\n+\t\tseg_size = pkt->data_len;\n+\t} else {\n+\t\twhile (start_offset >= pkt->data_len) {\n+\t\t\tstart_offset -= pkt->data_len;\n+\t\t\tpkt = pkt->next;\n+\t\t}\n+\n+\t\tseg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);\n+\t\tseg_phys = rte_pktmbuf_mtophys_offset(pkt, start_offset);\n+\t\tseg_size = pkt->data_len - start_offset;\n+\t\tif (!seg_size)\n+\t\t\treturn 1;\n+\t}\n+\n+\t/* first seg */\n+\tiovec->bufs[index].vaddr = seg_data;\n+\tiovec->bufs[index].dma_addr = seg_phys;\n+\tiovec->bufs[index].size = seg_size;\n+\tindex++;\n+\tpkt = pkt->next;\n+\n+\twhile (unlikely(pkt != NULL)) {\n+\t\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n+\t\tseg_phys = rte_pktmbuf_mtophys(pkt);\n+\t\tseg_size = pkt->data_len;\n+\t\tif (!seg_size)\n+\t\t\tbreak;\n+\n+\t\tiovec->bufs[index].vaddr = seg_data;\n+\t\tiovec->bufs[index].dma_addr = seg_phys;\n+\t\tiovec->bufs[index].size = seg_size;\n+\n+\t\tindex++;\n+\n+\t\t/* FIXME: Not depending on wqe.w0.s.bufs to break */\n+\t\tpkt = pkt->next;\n+\t}\n+\n+\tiovec->buf_cnt = index;\n+\treturn 0;\n+}\n+\n+static __rte_always_inline uint32_t\n+prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,\n+\t\t\t fc_params_t *param,\n+\t\t\t uint32_t *flags)\n+{\n+\tuint16_t index = 0;\n+\tvoid *seg_data = NULL;\n+\tphys_addr_t seg_phys;\n+\tuint32_t seg_size = 0;\n+\tiov_ptr_t *iovec;\n+\n+\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n+\tseg_phys = rte_pktmbuf_mtophys(pkt);\n+\tseg_size = pkt->data_len;\n+\n+\t/* first seg */\n+\tif (likely(!pkt->next)) {\n+\t\tuint32_t headroom, tailroom;\n+\n+\t\t*flags |= SINGLE_BUF_INPLACE;\n+\t\theadroom = rte_pktmbuf_headroom(pkt);\n+\t\ttailroom = rte_pktmbuf_tailroom(pkt);\n+\t\tif (likely((headroom >= 24) &&\n+\t\t (tailroom >= 8))) {\n+\t\t\t/* In 83XX this is prerequivisit for Direct mode */\n+\t\t\t*flags |= SINGLE_BUF_HEADTAILROOM;\n+\t\t}\n+\t\tparam->bufs[0].vaddr = seg_data;\n+\t\tparam->bufs[0].dma_addr = seg_phys;\n+\t\tparam->bufs[0].size = seg_size;\n+\t\treturn 0;\n+\t}\n+\tiovec = param->src_iov;\n+\tiovec->bufs[index].vaddr = seg_data;\n+\tiovec->bufs[index].dma_addr = seg_phys;\n+\tiovec->bufs[index].size = seg_size;\n+\tindex++;\n+\tpkt = pkt->next;\n+\n+\twhile (unlikely(pkt != NULL)) {\n+\t\tseg_data = rte_pktmbuf_mtod(pkt, void *);\n+\t\tseg_phys = rte_pktmbuf_mtophys(pkt);\n+\t\tseg_size = pkt->data_len;\n+\n+\t\tif (!seg_size)\n+\t\t\tbreak;\n+\n+\t\tiovec->bufs[index].vaddr = seg_data;\n+\t\tiovec->bufs[index].dma_addr = seg_phys;\n+\t\tiovec->bufs[index].size = seg_size;\n+\n+\t\tindex++;\n+\n+\t\tpkt = pkt->next;\n+\t}\n+\n+\tiovec->buf_cnt = index;\n+\treturn 0;\n+}\n+\n+static __rte_always_inline void *\n+fill_fc_params(struct rte_crypto_op *cop,\n+\t struct cpt_sess_misc *sess_misc,\n+\t void **mdata_ptr,\n+\t int *op_ret)\n+{\n+\tuint32_t space = 0;\n+\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n+\tvoid *mdata;\n+\tuintptr_t *op;\n+\tuint32_t mc_hash_off;\n+\tuint32_t flags = 0;\n+\tuint64_t d_offs, d_lens;\n+\tvoid *prep_req = NULL;\n+\tstruct rte_mbuf *m_src, *m_dst;\n+\tuint8_t cpt_op = sess_misc->cpt_op;\n+\tuint8_t zsk_flag = sess_misc->zsk_flag;\n+\tuint8_t aes_gcm = sess_misc->aes_gcm;\n+\tuint16_t mac_len = sess_misc->mac_len;\n+#ifdef CPT_ALWAYS_USE_SG_MODE\n+\tuint8_t inplace = 0;\n+#else\n+\tuint8_t inplace = 1;\n+#endif\n+\tfc_params_t fc_params;\n+\tchar src[SRC_IOV_SIZE];\n+\tchar dst[SRC_IOV_SIZE];\n+\tuint32_t iv_buf[4];\n+\tstruct cptvf_meta_info *cpt_m_info =\n+\t\t\t\t(struct cptvf_meta_info *)(*mdata_ptr);\n+\n+\tif (likely(sess_misc->iv_length)) {\n+\t\tflags |= VALID_IV_BUF;\n+\t\tfc_params.iv_buf = rte_crypto_op_ctod_offset(cop,\n+\t\t\t\t uint8_t *, sess_misc->iv_offset);\n+\t\tif (sess_misc->aes_ctr &&\n+\t\t unlikely(sess_misc->iv_length != 16)) {\n+\t\t\tmemcpy((uint8_t *)iv_buf,\n+\t\t\t\trte_crypto_op_ctod_offset(cop,\n+\t\t\t\tuint8_t *, sess_misc->iv_offset), 12);\n+\t\t\tiv_buf[3] = rte_cpu_to_be_32(0x1);\n+\t\t\tfc_params.iv_buf = iv_buf;\n+\t\t}\n+\t}\n+\n+\tif (zsk_flag) {\n+\t\tfc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,\n+\t\t\t\t\tuint8_t *,\n+\t\t\t\t\tsess_misc->auth_iv_offset);\n+\t\tif (zsk_flag == K_F9) {\n+\t\t\tCPT_LOG_DP_ERR(\"Should not reach here for \"\n+\t\t\t\"kasumi F9\\n\");\n+\t\t}\n+\t\tif (zsk_flag != ZS_EA)\n+\t\t\tinplace = 0;\n+\t}\n+\tm_src = sym_op->m_src;\n+\tm_dst = sym_op->m_dst;\n+\n+\tif (aes_gcm) {\n+\t\tuint8_t *salt;\n+\t\tuint8_t *aad_data;\n+\t\tuint16_t aad_len;\n+\n+\t\td_offs = sym_op->aead.data.offset;\n+\t\td_lens = sym_op->aead.data.length;\n+\t\tmc_hash_off = sym_op->aead.data.offset +\n+\t\t\t sym_op->aead.data.length;\n+\n+\t\taad_data = sym_op->aead.aad.data;\n+\t\taad_len = sess_misc->aad_length;\n+\t\tif (likely((aad_data + aad_len) ==\n+\t\t\t rte_pktmbuf_mtod_offset(m_src,\n+\t\t\t\tuint8_t *,\n+\t\t\t\tsym_op->aead.data.offset))) {\n+\t\t\td_offs = (d_offs - aad_len) | (d_offs << 16);\n+\t\t\td_lens = (d_lens + aad_len) | (d_lens << 32);\n+\t\t} else {\n+\t\t\tfc_params.aad_buf.vaddr = sym_op->aead.aad.data;\n+\t\t\tfc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr;\n+\t\t\tfc_params.aad_buf.size = aad_len;\n+\t\t\tflags |= VALID_AAD_BUF;\n+\t\t\tinplace = 0;\n+\t\t\td_offs = d_offs << 16;\n+\t\t\td_lens = d_lens << 32;\n+\t\t}\n+\n+\t\tsalt = fc_params.iv_buf;\n+\t\tif (unlikely(*(uint32_t *)salt != sess_misc->salt)) {\n+\t\t\tcpt_fc_salt_update(SESS_PRIV(sess_misc), salt);\n+\t\t\tsess_misc->salt = *(uint32_t *)salt;\n+\t\t}\n+\t\tfc_params.iv_buf = salt + 4;\n+\t\tif (likely(mac_len)) {\n+\t\t\tstruct rte_mbuf *m = (cpt_op & CPT_OP_ENCODE) ? m_dst :\n+\t\t\t\t\t m_src;\n+\n+\t\t\tif (!m)\n+\t\t\t\tm = m_src;\n+\n+\t\t\t/* hmac immediately following data is best case */\n+\t\t\tif (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +\n+\t\t\t mc_hash_off !=\n+\t\t\t (uint8_t *)sym_op->aead.digest.data)) {\n+\t\t\t\tflags |= VALID_MAC_BUF;\n+\t\t\t\tfc_params.mac_buf.size = sess_misc->mac_len;\n+\t\t\t\tfc_params.mac_buf.vaddr =\n+\t\t\t\t sym_op->aead.digest.data;\n+\t\t\t\tfc_params.mac_buf.dma_addr =\n+\t\t\t\t sym_op->aead.digest.phys_addr;\n+\t\t\t\tinplace = 0;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\td_offs = sym_op->cipher.data.offset;\n+\t\td_lens = sym_op->cipher.data.length;\n+\t\tmc_hash_off = sym_op->cipher.data.offset +\n+\t\t\t sym_op->cipher.data.length;\n+\t\td_offs = (d_offs << 16) | sym_op->auth.data.offset;\n+\t\td_lens = (d_lens << 32) | sym_op->auth.data.length;\n+\n+\t\tif (mc_hash_off < (sym_op->auth.data.offset +\n+\t\t\t\t sym_op->auth.data.length)){\n+\t\t\tmc_hash_off = (sym_op->auth.data.offset +\n+\t\t\t\t sym_op->auth.data.length);\n+\t\t}\n+\t\t/* for gmac, salt should be updated like in gcm */\n+\t\tif (unlikely(sess_misc->is_gmac)) {\n+\t\t\tuint8_t *salt;\n+\t\t\tsalt = fc_params.iv_buf;\n+\t\t\tif (unlikely(*(uint32_t *)salt != sess_misc->salt)) {\n+\t\t\t\tcpt_fc_salt_update(SESS_PRIV(sess_misc), salt);\n+\t\t\t\tsess_misc->salt = *(uint32_t *)salt;\n+\t\t\t}\n+\t\t\tfc_params.iv_buf = salt + 4;\n+\t\t}\n+\t\t\t/* */\n+\t\tif (likely(mac_len)) {\n+\t\t\tstruct rte_mbuf *m =\n+\t\t\t(cpt_op & CPT_OP_ENCODE) ? m_dst : m_src;\n+\n+\t\t\tif (!m)\n+\t\t\t\tm = m_src;\n+\n+\t\t/* hmac immediately following data is best case */\n+\t\t\tif (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +\n+\t\t\t mc_hash_off !=\n+\t\t\t (uint8_t *)sym_op->auth.digest.data)) {\n+\t\t\t\tflags |= VALID_MAC_BUF;\n+\t\t\t\tfc_params.mac_buf.size =\n+\t\t\t\t\tsess_misc->mac_len;\n+\t\t\t\tfc_params.mac_buf.vaddr =\n+\t\t\t\t\tsym_op->auth.digest.data;\n+\t\t\t\tfc_params.mac_buf.dma_addr =\n+\t\t\t\tsym_op->auth.digest.phys_addr;\n+\t\t\t\tinplace = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tfc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc);\n+\tfc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr;\n+\n+\tif (unlikely(sess_misc->is_null || sess_misc->cpt_op == CPT_OP_DECODE))\n+\t\tinplace = 0;\n+\n+\tif (likely(!m_dst && inplace)) {\n+\t\t/* Case of single buffer without AAD buf or\n+\t\t * separate mac buf in place and\n+\t\t * not air crypto\n+\t\t */\n+\t\tfc_params.dst_iov = fc_params.src_iov = (void *)src;\n+\n+\t\tif (unlikely(prepare_iov_from_pkt_inplace(m_src,\n+\t\t\t\t\t\t\t &fc_params,\n+\t\t\t\t\t\t\t &flags))) {\n+\t\t\tCPT_LOG_DP_ERR(\"Prepare inplace src iov failed\\n\");\n+\t\t\t*op_ret = -1;\n+\t\t\treturn NULL;\n+\t\t}\n+\n+\t} else {\n+\t\t/* Out of place processing */\n+\t\tfc_params.src_iov = (void *)src;\n+\t\tfc_params.dst_iov = (void *)dst;\n+\n+\t\t/*Store SG I/O in the api for reuse */\n+\t\tif (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {\n+\t\t\tCPT_LOG_DP_ERR(\"Prepare src iov failed\\n\");\n+\t\t\t*op_ret = -1;\n+\t\t\treturn NULL;\n+\t\t}\n+\n+\t\tif (unlikely(m_dst != NULL)) {\n+\t\t\tuint32_t pkt_len;\n+\n+\t\t\t/* Try to make room as much as src has */\n+\t\t\tm_dst = sym_op->m_dst;\n+\t\t\tpkt_len = rte_pktmbuf_pkt_len(m_dst);\n+\n+\t\t\tif (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {\n+\t\t\t\tpkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;\n+\t\t\t\tif (!rte_pktmbuf_append(m_dst, pkt_len)) {\n+\t\t\t\t\tCPT_LOG_DP_ERR(\"Not enough space in \"\n+\t\t\t\t\t \"m_dst %p, need %u more\\n\",\n+\t\t\t\t\t m_dst, pkt_len);\n+\t\t\t\t\treturn NULL;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tif (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {\n+\t\t\t\tCPT_LOG_DP_ERR(\"Prepare dst iov failed for \"\n+\t\t\t\t \"m_dst %p\\n\", m_dst);\n+\t\t\t\treturn NULL;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tfc_params.dst_iov = (void *)src;\n+\t\t}\n+\n+\t}\n+\n+\tif (likely(flags & SINGLE_BUF_HEADTAILROOM))\n+\t\tmdata = alloc_op_meta(m_src,\n+\t\t\t\t &fc_params.meta_buf,\n+\t\t\t\t cpt_m_info->cptvf_op_sb_mlen,\n+\t\t\t\t cpt_m_info->cptvf_meta_pool);\n+\telse\n+\t\tmdata = alloc_op_meta(NULL,\n+\t\t\t\t &fc_params.meta_buf,\n+\t\t\t\t cpt_m_info->cptvf_op_mlen,\n+\t\t\t\t cpt_m_info->cptvf_meta_pool);\n+\n+\tif (unlikely(mdata == NULL)) {\n+\t\tCPT_LOG_DP_ERR(\"Error allocating meta buffer for request\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\top = (uintptr_t *)((uintptr_t)mdata & (uintptr_t)~1ull);\n+\top[0] = (uintptr_t)mdata;\n+\top[1] = (uintptr_t)cop;\n+\top[2] = op[3] = 0; /* Used to indicate auth verify */\n+\tspace += 4 * sizeof(uint64_t);\n+\n+\tfc_params.meta_buf.vaddr = (uint8_t *)op + space;\n+\tfc_params.meta_buf.dma_addr += space;\n+\tfc_params.meta_buf.size -= space;\n+\n+\t/* Finally prepare the instruction */\n+\tif (cpt_op & CPT_OP_ENCODE)\n+\t\tprep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,\n+\t\t\t\t\t\t&fc_params, op, op_ret);\n+\n+\tif (unlikely(!prep_req))\n+\t\tfree_op_meta(mdata, cpt_m_info->cptvf_meta_pool);\n+\t*mdata_ptr = mdata;\n+\treturn prep_req;\n+}\n+\n #endif /*_CPT_UCODE_H_ */\n", "prefixes": [ "v2", "21/33" ] }