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GET /api/patches/44194/?format=api
{ "id": 44194, "url": "http://patches.dpdk.org/api/patches/44194/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-27-git-send-email-ajoseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536033560-21541-27-git-send-email-ajoseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536033560-21541-27-git-send-email-ajoseph@caviumnetworks.com", "date": "2018-09-04T03:59:13", "name": "[v2,26/33] common/cpt: add support for hash", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cb6c9dfbbbaf5cfbbb06877b6a7318ddd4ca32f3", "submitter": { "id": 891, "url": "http://patches.dpdk.org/api/people/891/?format=api", "name": "Anoob Joseph", "email": "ajoseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-27-git-send-email-ajoseph@caviumnetworks.com/mbox/", "series": [ { "id": 1164, "url": "http://patches.dpdk.org/api/series/1164/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1164", "date": "2018-09-04T03:58:47", "name": "Adding Cavium's OcteonTX crypto PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/1164/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44194/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/44194/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C31282BF3;\n\tTue, 4 Sep 2018 06:03:46 +0200 (CEST)", "from NAM02-CY1-obe.outbound.protection.outlook.com\n\t(mail-cys01nam02on0055.outbound.protection.outlook.com\n\t[104.47.37.55]) by dpdk.org (Postfix) with ESMTP id 908231AEE9\n\tfor <dev@dpdk.org>; Tue, 4 Sep 2018 06:03:44 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1101.15; Tue, 4 Sep 2018 04:03:39 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=Ab4TDxZl7GxMm+8tN/ry5HUSiqNUl9H/ZOJCA+c85HQ=;\n\tb=bBIRBY8sZCmSt7BklCY6NYM5puwJlA5/eot0TtlVOtGO/8Ja+z9W5rLNJCE9JQpbFemq8WwT3MwNk3A+0MpcAXH/CqMrqPmd01FZq8P+Hf8+gtPSbGtrvNpk3SBBnh8LMZp5xu05V8JtpM46Uesw6V0Rj9oWFaeDt4t31aFfrXM=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <ajoseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Srisivasubramanian S <ssrinivasan@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tdev@dpdk.org, Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tAnoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tRagothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tTejasree Kondoj <kondoj.tejasree@caviumnetworks.com>", "Date": "Tue, 4 Sep 2018 09:29:13 +0530", "Message-Id": "<1536033560-21541-27-git-send-email-ajoseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "References": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:d::33) To BYAPR07MB4902.namprd07.prod.outlook.com\n\t(2603:10b6:a02:ef::25)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "7bcb7fd4-08cf-4980-d48c-08d6121b67bc", "X-Microsoft-Antispam": "BCL:0; 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"UqkITQT3npAq2y7hskooJdTK76nIDksq1ygUk5mxrXYSsD3vlathmAv2Y9J05Fzm4oDnXfdWELYQRMVngtR4ec30lQ0Nv9OxYNN6uO+BaPN3+Y/GXJ+54JYIknME+xR81bNCYWCyveqjGNJTUqK58YtoXcpaFrTIvjtgKTWkzNUmnthqiWsINwSZ+3zL58SagMQAZGnErqz5LQB+JvsdNRXQEJP2Sq5OBgWwQxS+69/VEox7OTprGbNN1SFtI0WT6FRCqU8Bm1Kx+eZ86vO24sp4SzTAyv63E/fuxvAjEIefLMRXD/J4tQ7WGm0j3JSt40ATNvvfE7tfWAMjgsdaF2OlKT1xC6WURzi3V5kKe+U=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Sep 2018 04:03:39.5067\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "7bcb7fd4-08cf-4980-d48c-08d6121b67bc", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR07MB4902", "Subject": "[dpdk-dev] [PATCH v2 26/33] common/cpt: add support for hash", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\n\nAdding microcode interface for supporting verify and authentication\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/common/cpt/cpt_mcode_defines.h | 6 +\n drivers/common/cpt/cpt_request_mgr.h | 2 +\n drivers/common/cpt/cpt_ucode.h | 424 ++++++++++++++++++++++++++++++++-\n 3 files changed, 431 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h\nindex 17b0de3..b580289 100644\n--- a/drivers/common/cpt/cpt_mcode_defines.h\n+++ b/drivers/common/cpt/cpt_mcode_defines.h\n@@ -334,6 +334,12 @@ typedef struct fc_params {\n \n } fc_params_t;\n \n+/*\n+ * Parameters for digest\n+ * generate requests\n+ * Only src_iov, op, ctx_buf, mac_buf, prep_req\n+ * meta_buf, auth_data_len are used for digest gen.\n+ */\n typedef struct fc_params digest_params_t;\n \n /* Cipher Algorithms */\ndiff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h\nindex c082e21..d843ee7 100644\n--- a/drivers/common/cpt/cpt_request_mgr.h\n+++ b/drivers/common/cpt/cpt_request_mgr.h\n@@ -74,6 +74,8 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,\n \n \tif (likely(cpt_op & CPT_OP_CIPHER_MASK))\n \t\tprep_req = fill_fc_params(op, sess, &mdata, &ret);\n+\telse\n+\t\tprep_req = fill_digest_params(op, sess, &mdata, &ret);\n \n \tif (unlikely(!prep_req)) {\n \t\tCPT_LOG_DP_ERR(\"prep cryto req : op %p, cpt_op 0x%x \"\ndiff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h\nindex f618203..7d2b3ef 100644\n--- a/drivers/common/cpt/cpt_ucode.h\n+++ b/drivers/common/cpt/cpt_ucode.h\n@@ -4,7 +4,6 @@\n \n #ifndef _CPT_UCODE_H_\n #define _CPT_UCODE_H_\n-\n #include <stdbool.h>\n \n #include \"cpt_common.h\"\n@@ -367,6 +366,218 @@ fill_sg_comp_from_iov(sg_comp_t *list,\n }\n \n static __rte_always_inline int\n+cpt_digest_gen_prep(uint32_t flags,\n+\t\t uint64_t d_offs,\n+\t\t uint64_t d_lens,\n+\t\t digest_params_t *params,\n+\t\t void *op,\n+\t\t void **prep_req)\n+{\n+\tstruct cpt_request_info *req;\n+\tuint32_t size, i;\n+\tint32_t m_size;\n+\tuint16_t data_len, mac_len, key_len;\n+\tauth_type_t hash_type;\n+\tbuf_ptr_t *meta_p;\n+\tstruct cpt_ctx *ctx;\n+\tsg_comp_t *gather_comp;\n+\tsg_comp_t *scatter_comp;\n+\tuint8_t *in_buffer;\n+\tuint32_t g_size_bytes, s_size_bytes;\n+\tuint64_t dptr_dma, rptr_dma;\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tvq_cmd_word3_t vq_cmd_w3;\n+\tvoid *c_vaddr, *m_vaddr;\n+\tuint64_t c_dma, m_dma;\n+\topcode_info_t opcode;\n+\n+\tif (!params || !params->ctx_buf.vaddr)\n+\t\treturn ERR_BAD_INPUT_ARG;\n+\n+\t(void)d_offs;\n+\tctx = params->ctx_buf.vaddr;\n+\tmeta_p = ¶ms->meta_buf;\n+\n+\tif (!meta_p->vaddr || !meta_p->dma_addr)\n+\t\treturn ERR_BAD_INPUT_ARG;\n+\n+\tif (meta_p->size < sizeof(struct cpt_request_info))\n+\t\treturn ERR_BAD_INPUT_ARG;\n+\n+\tm_vaddr = meta_p->vaddr;\n+\tm_dma = meta_p->dma_addr;\n+\tm_size = meta_p->size;\n+\n+\t/*\n+\t * Save initial space that followed app data for completion code &\n+\t * alternate completion code to fall in same cache line as app data\n+\t */\n+\tm_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;\n+\tm_dma += COMPLETION_CODE_SIZE;\n+\tsize = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -\n+\t\t(uint8_t *)m_vaddr;\n+\tc_vaddr = (uint8_t *)m_vaddr + size;\n+\tc_dma = m_dma + size;\n+\tsize += sizeof(cpt_res_s_t);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\treq = m_vaddr;\n+\n+\tsize = sizeof(struct cpt_request_info);\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Initialising ctrl and opcode fields */\n+\n+\treq->dma_mode = CTRL_DMA_MODE_SGIO;\n+\treq->se_req = SE_CORE_REQ;\n+\n+\thash_type = ctx->hash_type;\n+\tmac_len = ctx->mac_len;\n+\tkey_len = ctx->auth_key_len;\n+\tdata_len = AUTH_DLEN(d_lens);\n+\n+\t/*GP op header */\n+\tvq_cmd_w0.u64 = 0;\n+\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(((uint16_t)hash_type << 8));\n+\tif (ctx->hmac) {\n+\t\topcode.s.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE;\n+\t\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(key_len);\n+\t\tvq_cmd_w0.s.dlen =\n+\t\t\trte_cpu_to_be_16((data_len + ROUNDUP8(key_len)));\n+\t} else {\n+\t\topcode.s.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE;\n+\t\tvq_cmd_w0.s.param1 = 0;\n+\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(data_len);\n+\t\t/* This is required for null auth only case */\n+\t\tif (!hash_type && !ctx->enc_cipher)\n+\t\t\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(data_len);\n+\t}\n+\n+\topcode.s.minor = 0;\n+\n+\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\n+\t/* DPTR has SG list */\n+\tin_buffer = m_vaddr;\n+\tdptr_dma = m_dma;\n+\n+\t((uint16_t *)in_buffer)[0] = 0;\n+\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t/* TODO Add error check if space will be sufficient */\n+\tgather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);\n+\n+\t/*\n+\t * Input gather list\n+\t */\n+\n+\ti = 0;\n+\n+\tif (ctx->hmac) {\n+\t\tuint64_t k_dma = params->ctx_buf.dma_addr +\n+\t\t\toffsetof(struct cpt_ctx, auth_key);\n+\t\t/* Key */\n+\t\ti = fill_sg_comp(gather_comp, i, k_dma,\n+\t\t\t\t ctx->auth_key, ROUNDUP8(key_len));\n+\t}\n+\n+\t/* input data */\n+\tsize = data_len;\n+\tif (size) {\n+\t\ti = fill_sg_comp_from_iov(gather_comp, i, params->src_iov,\n+\t\t\t\t\t 0, &size, NULL, 0);\n+\t\tif (size) {\n+\t\t\tCPT_LOG_DP_DEBUG(\"Insufficient dst IOV size, short\"\n+\t\t\t\" by %dB\\n\", size);\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t}\n+\t} else {\n+\t\t/*\n+\t\t * Looks like we need to support zero data\n+\t\t * gather ptr in case of hash & hmac\n+\t\t */\n+\t\ti++;\n+\t}\n+\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\tg_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\n+\t/*\n+\t * Output Gather list\n+\t */\n+\n+\ti = 0;\n+\tscatter_comp =\n+\t\t(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\tif (flags & VALID_MAC_BUF) {\n+\t\tif (params->mac_buf.size < mac_len)\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+\n+\t\tsize = mac_len;\n+\t\ti = fill_sg_comp_from_buf_min(scatter_comp, i,\n+\t\t\t\t\t ¶ms->mac_buf, &size);\n+\t} else {\n+\t\tsize = mac_len;\n+\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t params->src_iov, data_len,\n+\t\t\t\t\t &size, NULL, 0);\n+\t\tif (size) {\n+\t\t\tCPT_LOG_DP_DEBUG(\"Insufficient dst IOV size, short by\"\n+\t\t\t\t \" %dB\\n\", size);\n+\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t}\n+\t}\n+\n+\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\ts_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n+\n+\t/* This is DPTR len incase of SG mode */\n+\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* cpt alternate completion address saved earlier */\n+\treq->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);\n+\t*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);\n+\trptr_dma = c_dma - 8;\n+\n+\treq->ist.ei1 = dptr_dma;\n+\treq->ist.ei2 = rptr_dma;\n+\t/* First 16-bit swap then 64-bit swap */\n+\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n+\t * to eliminate all the swapping\n+\t */\n+\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n+\n+\t/* vq command w3 */\n+\tvq_cmd_w3.u64 = 0;\n+\n+\t/* 16 byte aligned cpt res address */\n+\treq->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);\n+\t*req->completion_addr = COMPLETION_CODE_INIT;\n+\treq->comp_baddr = c_dma;\n+\n+\t/* Fill microcode part of instruction */\n+\treq->ist.ei0 = vq_cmd_w0.u64;\n+\treq->ist.ei3 = vq_cmd_w3.u64;\n+\n+\treq->op = op;\n+\n+\t*prep_req = req;\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n cpt_enc_hmac_prep(uint32_t flags,\n \t\t uint64_t d_offs,\n \t\t uint64_t d_lens,\n@@ -2306,6 +2517,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \t} else if (fc_type == KASUMI) {\n \t\tret = cpt_kasumi_enc_prep(flags, d_offs, d_lens,\n \t\t\t\t\t fc_params, op, &prep_req);\n+\t} else if (fc_type == HASH_HMAC) {\n+\t\tret = cpt_digest_gen_prep(flags, d_offs, d_lens,\n+\t\t\t\t\t fc_params, op, &prep_req);\n \t} else {\n \t\tret = ERR_EIO;\n \t}\n@@ -3195,4 +3409,212 @@ instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)\n \treturn -1;\n }\n \n+static __rte_always_inline void\n+find_kasumif9_direction_and_length(uint8_t *src,\n+\t\t\t\t uint32_t counter_num_bytes,\n+\t\t\t\t uint32_t *addr_length_in_bits,\n+\t\t\t\t uint8_t *addr_direction)\n+{\n+\tuint8_t found = 0;\n+\twhile (!found && counter_num_bytes > 0) {\n+\t\tcounter_num_bytes--;\n+\t\tif (src[counter_num_bytes] == 0x00)\n+\t\t\tcontinue;\n+\t\tif (src[counter_num_bytes] == 0x80) {\n+\t\t\t*addr_direction = src[counter_num_bytes - 1] & 0x1;\n+\t\t\t*addr_length_in_bits = counter_num_bytes * 8 - 1;\n+\t\t\tfound = 1;\n+\t\t} else {\n+\t\t\tint i = 0;\n+\t\t\tuint8_t last_byte = src[counter_num_bytes];\n+\t\t\tfor (i = 0; i < 8 && found == 0; i++) {\n+\t\t\t\tif (last_byte & (1 << i)) {\n+\t\t\t\t\t*addr_direction = (last_byte >> (i+1))\n+\t\t\t\t\t\t\t & 0x1;\n+\t\t\t\t\tif (i != 6)\n+\t\t\t\t\t\t*addr_length_in_bits =\n+\t\t\t\t\t\t\tcounter_num_bytes * 8\n+\t\t\t\t\t\t\t+ (8 - (i + 2));\n+\t\t\t\t\telse\n+\t\t\t\t\t\t*addr_length_in_bits =\n+\t\t\t\t\t\t\tcounter_num_bytes * 8;\n+\n+\t\t\t\t\tfound = 1;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t}\n+}\n+/*\n+ * This handles all auth only except AES_GMAC\n+ */\n+static __rte_always_inline void *\n+fill_digest_params(struct rte_crypto_op *cop,\n+\t\t struct cpt_sess_misc *sess,\n+\t\t void **mdata_ptr,\n+\t\t int *op_ret)\n+{\n+\tuint32_t space = 0;\n+\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n+\tvoid *mdata;\n+\tphys_addr_t mphys;\n+\tuint64_t *op;\n+\tuint32_t auth_range_off;\n+\tuint32_t flags = 0;\n+\tuint64_t d_offs = 0, d_lens;\n+\tvoid *prep_req = NULL;\n+\tstruct rte_mbuf *m_src, *m_dst;\n+\tuint16_t auth_op = sess->cpt_op & CPT_OP_AUTH_MASK;\n+\tuint8_t zsk_flag = sess->zsk_flag;\n+\tuint16_t mac_len = sess->mac_len;\n+\tfc_params_t params;\n+\tchar src[SRC_IOV_SIZE];\n+\tuint8_t iv_buf[16];\n+\tmemset(¶ms, 0, sizeof(fc_params_t));\n+\tstruct cptvf_meta_info *cpt_m_info =\n+\t\t\t\t(struct cptvf_meta_info *)(*mdata_ptr);\n+\n+\tm_src = sym_op->m_src;\n+\n+\t/* For just digest lets force mempool alloc */\n+\tmdata = alloc_op_meta(NULL, ¶ms.meta_buf, cpt_m_info->cptvf_op_mlen,\n+\t\t\t cpt_m_info->cptvf_meta_pool);\n+\tif (mdata == NULL) {\n+\t\tCPT_LOG_DP_ERR(\"Error allocating meta buffer for\"\n+\t\t\" request\\n\");\n+\t\t*op_ret = -ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tmphys = params.meta_buf.dma_addr;\n+\n+\top = mdata;\n+\top[0] = (uintptr_t)mdata;\n+\top[1] = (uintptr_t)cop;\n+\top[2] = op[3] = 0; /* Used to indicate auth verify */\n+\tspace += 4 * sizeof(uint64_t);\n+\n+\tauth_range_off = sym_op->auth.data.offset;\n+\n+\tflags = VALID_MAC_BUF;\n+\tparams.src_iov = (void *)src;\n+\tif (unlikely(zsk_flag)) {\n+\t\t/*\n+\t\t * Since for Zuc, Kasumi, Snow3g offsets are in bits\n+\t\t * we will send pass through even for auth only case,\n+\t\t * let MC handle it\n+\t\t */\n+\t\td_offs = auth_range_off;\n+\t\tauth_range_off = 0;\n+\t\tparams.auth_iv_buf = rte_crypto_op_ctod_offset(cop,\n+\t\t\t\t\tuint8_t *, sess->auth_iv_offset);\n+\t\tif (zsk_flag == K_F9) {\n+\t\t\tuint32_t length_in_bits, num_bytes;\n+\t\t\tuint8_t *src, direction = 0;\n+\t\t\tuint32_t counter_num_bytes;\n+\n+\t\t\tmemcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src,\n+\t\t\t\t\t\t\tuint8_t *), 8);\n+\t\t\t/*\n+\t\t\t * This is kasumi f9, take direction from\n+\t\t\t * source buffer\n+\t\t\t */\n+\t\t\tlength_in_bits = cop->sym->auth.data.length;\n+\t\t\tnum_bytes = (length_in_bits >> 3);\n+\t\t\tcounter_num_bytes = num_bytes;\n+\t\t\tsrc = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);\n+\t\t\tfind_kasumif9_direction_and_length(src,\n+\t\t\t\t\t\tcounter_num_bytes,\n+\t\t\t\t\t\t&length_in_bits,\n+\t\t\t\t\t\t&direction);\n+\t\t\tlength_in_bits -= 64;\n+\t\t\tcop->sym->auth.data.offset += 64;\n+\t\t\td_offs = cop->sym->auth.data.offset;\n+\t\t\tauth_range_off = d_offs / 8;\n+\t\t\tcop->sym->auth.data.length = length_in_bits;\n+\n+\t\t\t/* Store it at end of auth iv */\n+\t\t\tiv_buf[8] = direction;\n+\t\t\tparams.auth_iv_buf = iv_buf;\n+\t\t}\n+\t}\n+\n+\td_lens = sym_op->auth.data.length;\n+\n+\tparams.ctx_buf.vaddr = SESS_PRIV(sess);\n+\tparams.ctx_buf.dma_addr = sess->ctx_dma_addr;\n+\n+\tif (auth_op == CPT_OP_AUTH_GENERATE) {\n+\t\tif (sym_op->auth.digest.data) {\n+\t\t\t/*\n+\t\t\t * Digest to be generated\n+\t\t\t * in separate buffer\n+\t\t\t */\n+\t\t\tparams.mac_buf.size =\n+\t\t\t\tsess->mac_len;\n+\t\t\tparams.mac_buf.vaddr =\n+\t\t\t\tsym_op->auth.digest.data;\n+\t\t\tparams.mac_buf.dma_addr =\n+\t\t\t\tsym_op->auth.digest.phys_addr;\n+\t\t} else {\n+\t\t\tuint32_t off = sym_op->auth.data.offset +\n+\t\t\t\tsym_op->auth.data.length;\n+\t\t\tint32_t dlen, space;\n+\n+\t\t\tm_dst = sym_op->m_dst ?\n+\t\t\t\tsym_op->m_dst : sym_op->m_src;\n+\t\t\tdlen = rte_pktmbuf_pkt_len(m_dst);\n+\n+\t\t\tspace = off + mac_len - dlen;\n+\t\t\tif (space > 0)\n+\t\t\t\tif (!rte_pktmbuf_append(m_dst, space)) {\n+\t\t\t\t\tCPT_LOG_DP_ERR(\"Failed to extend \"\n+\t\t\t\t\t \"mbuf by %uB\\n\", space);\n+\t\t\t\t\tgoto err;\n+\t\t\t\t}\n+\n+\t\t\tparams.mac_buf.vaddr =\n+\t\t\t\trte_pktmbuf_mtod_offset(m_dst,\n+\t\t\t\t\t\t\tvoid *, off);\n+\t\t\tparams.mac_buf.dma_addr =\n+\t\t\t\trte_pktmbuf_mtophys_offset(m_dst, off);\n+\t\t\tparams.mac_buf.size = mac_len;\n+\t\t}\n+\t} else {\n+\t\t/* Need space for storing generated mac */\n+\t\tparams.mac_buf.vaddr =\n+\t\t\t(uint8_t *)mdata + space;\n+\t\tparams.mac_buf.dma_addr = mphys + space;\n+\t\tparams.mac_buf.size = mac_len;\n+\t\tspace += RTE_ALIGN_CEIL(mac_len, 8);\n+\t\top[2] = (uintptr_t)params.mac_buf.vaddr;\n+\t\top[3] = mac_len;\n+\n+\t}\n+\n+\tparams.meta_buf.vaddr = (uint8_t *)mdata + space;\n+\tparams.meta_buf.dma_addr = mphys + space;\n+\tparams.meta_buf.size -= space;\n+\n+\t/* Out of place processing */\n+\tparams.src_iov = (void *)src;\n+\n+\t/*Store SG I/O in the api for reuse */\n+\tif (prepare_iov_from_pkt(m_src, params.src_iov,\n+\t\t\t\t auth_range_off)) {\n+\t\tCPT_LOG_DP_ERR(\"Prepare src iov failed\\n\");\n+\t\t*op_ret = -1;\n+\t\tgoto err;\n+\t}\n+\n+\tprep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,\n+\t\t\t\t\t¶ms, op, op_ret);\n+\t*mdata_ptr = mdata;\n+\treturn prep_req;\n+err:\n+\tif (unlikely(!prep_req))\n+\t\tfree_op_meta(mdata, cpt_m_info->cptvf_meta_pool);\n+\treturn NULL;\n+}\n+\n #endif /*_CPT_UCODE_H_ */\n", "prefixes": [ "v2", "26/33" ] }