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GET /api/patches/44188/?format=api
{ "id": 44188, "url": "http://patches.dpdk.org/api/patches/44188/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-14-git-send-email-ajoseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536033560-21541-14-git-send-email-ajoseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536033560-21541-14-git-send-email-ajoseph@caviumnetworks.com", "date": "2018-09-04T03:59:00", "name": "[v2,13/33] crypto/octeontx: add basic dev ops", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "229f4c853c4538af8a89ed7ad7655c51a19cdd22", "submitter": { "id": 891, "url": "http://patches.dpdk.org/api/people/891/?format=api", "name": "Anoob Joseph", "email": "ajoseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-14-git-send-email-ajoseph@caviumnetworks.com/mbox/", "series": [ { "id": 1164, "url": "http://patches.dpdk.org/api/series/1164/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1164", "date": "2018-09-04T03:58:47", "name": "Adding Cavium's OcteonTX crypto PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/1164/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44188/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/44188/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 151A15F21;\n\tTue, 4 Sep 2018 06:03:26 +0200 (CEST)", "from NAM01-SN1-obe.outbound.protection.outlook.com\n\t(mail-sn1nam01on0082.outbound.protection.outlook.com [104.47.32.82])\n\tby dpdk.org (Postfix) with ESMTP id D544A2C38\n\tfor <dev@dpdk.org>; Tue, 4 Sep 2018 06:03:08 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1101.15; Tue, 4 Sep 2018 04:02:39 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=TWELDeQrWTR0gemWlemqfgA/oyTILRRv/pSErf1mLPo=;\n\tb=Ld1u1GAPjlEJ94wcHRYNhLH3aBy6AJeC7c3nXSl9m7TxqPZ+WCJ2dibR3xJSaYCLkw+IJdZahp3/WbS6dvR4KqAKtgN12SvI+3Ulguo3AssfvQQuVK9nj4UsJ8kK7VCiYnTJVvQMda0xCBNB1bWEA3KxNHVsNksOhqLW0ujZPAU=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <ajoseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tdev@dpdk.org, Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tAnoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tRagothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tSrisivasubramanian S <ssrinivasan@caviumnetworks.com>,\n\tTejasree Kondoj <kondoj.tejasree@caviumnetworks.com>", "Date": "Tue, 4 Sep 2018 09:29:00 +0530", "Message-Id": "<1536033560-21541-14-git-send-email-ajoseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "References": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:d::33) To BYAPR07MB4902.namprd07.prod.outlook.com\n\t(2603:10b6:a02:ef::25)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "730c8533-531c-429b-ffa6-08d6121b440e", "X-Microsoft-Antispam": "BCL:0; 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"X+mXCO0nrFjGJ63HX4p3TRNM1pHlV2QRaOsMvcE2evFEhhjpELv5Ao6PjSOehdqddmmsJ7BN9rJC8j0Ox4HH1PkfEl57Sj6DpgDpQTCOdRckA60+MJo5PBW9xQo1CDssk2Jf9KEeVHeWdygOSYWEon1LNKEu83x/Wf41gfsSwpencGWKZe9QksR75f03wV0pPnEDYggc0Zbam6NAAtEwIJM4wRiDXULL3QPU11vFCZM3HXf5gO3Aq+ID4NTlaIN00elkYFnXTL5vVBs8I4PreVbneJq/Bey5MDH0296bpdxf8rCICRrGKULHF0wVZQ7RV64Gkto7QEKbvU2lqFAXBaSeVzSxLvs6DKEXlGE95mk=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Sep 2018 04:02:39.6473\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "730c8533-531c-429b-ffa6-08d6121b440e", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR07MB4902", "Subject": "[dpdk-dev] [PATCH v2 13/33] crypto/octeontx: add basic dev ops", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\n\nAdding the following dev ops,\n- dev_configure\n- dev_start\n- dev_stop\n- dev_close\n- dev_infos_get\n- stats_get\n- stats_reset\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 57 ++++++++++++++\n drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 30 ++++++++\n drivers/crypto/octeontx/otx_cryptodev_ops.c | 94 ++++++++++++++++++++++-\n drivers/crypto/octeontx/otx_cryptodev_ops.h | 4 +\n 4 files changed, 184 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\nindex a6b5bc6..d8b8872 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n@@ -2,6 +2,7 @@\n * Copyright(c) 2018 Cavium, Inc\n */\n #include <string.h>\n+#include <unistd.h>\n \n #include <rte_branch_prediction.h>\n #include <rte_common.h>\n@@ -265,3 +266,59 @@ otx_cpt_deinit_device(void *dev)\n \n \treturn 0;\n }\n+\n+int\n+otx_cpt_start_device(void *dev)\n+{\n+\tint rc;\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)dev;\n+\n+\trc = otx_cpt_send_vf_up(cptvf);\n+\tif (rc) {\n+\t\tCPT_LOG_ERR(\"Failed to mark CPT VF device %s UP, rc = %d\",\n+\t\t\t cptvf->dev_name, rc);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tif ((cptvf->vftype != SE_TYPE) &&\n+\t (cptvf->vftype != AE_TYPE)) {\n+\t\tCPT_LOG_ERR(\"Fatal error, unexpected vf type %u, for CPT VF \"\n+\t\t\t \"device %s\\n\", cptvf->vftype, cptvf->dev_name);\n+\t\treturn -ENOENT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void\n+otx_cpt_stop_device(void *dev)\n+{\n+\tint rc;\n+\tuint32_t pending, retries = 5;\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)dev;\n+\n+\t/* Wait for pending entries to complete */\n+\tpending = otx_cpt_read_vq_doorbell(cptvf);\n+\twhile (pending) {\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Waiting for pending %u cmds to complete\",\n+\t\t\t\t cptvf->dev_name, pending);\n+\t\tsleep(1);\n+\t\tpending = otx_cpt_read_vq_doorbell(cptvf);\n+\t\tretries--;\n+\t\tif (!retries)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (!retries && pending) {\n+\t\tCPT_LOG_ERR(\"%s: Timeout waiting for commands(%u)\",\n+\t\t\t cptvf->dev_name, pending);\n+\t\treturn;\n+\t}\n+\n+\trc = otx_cpt_send_vf_down(cptvf);\n+\tif (rc) {\n+\t\tCPT_LOG_ERR(\"Failed to bring down vf %s, rc %d\",\n+\t\t\t cptvf->dev_name, rc);\n+\t\treturn;\n+\t}\n+}\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\nindex 82d8255..7dbc41e 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n@@ -11,6 +11,7 @@\n #include <rte_memory.h>\n \n #include \"cpt_common.h\"\n+#include \"cpt_hw_types.h\"\n \n /* Flags to indicate the features supported */\n #define CPT_FLAG_VF_DRIVER\t\t(uint16_t)(1 << 3)\n@@ -150,4 +151,33 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);\n int\n otx_cpt_deinit_device(void *dev);\n \n+int\n+otx_cpt_start_device(void *cptvf);\n+\n+void\n+otx_cpt_stop_device(void *cptvf);\n+\n+/* Write to VQX_DOORBELL register\n+ */\n+static __rte_always_inline void\n+otx_cpt_write_vq_doorbell(struct cpt_vf *cptvf, uint32_t val)\n+{\n+\tcptx_vqx_doorbell_t vqx_dbell;\n+\n+\tvqx_dbell.u = 0;\n+\tvqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_DOORBELL(0, 0), vqx_dbell.u);\n+}\n+\n+static __rte_always_inline uint32_t\n+otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_doorbell_t vqx_dbell;\n+\n+\tvqx_dbell.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_DOORBELL(0, 0));\n+\treturn vqx_dbell.s.dbell_cnt;\n+}\n+\n #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c\nindex d109159..2bbf82f 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c\n@@ -5,6 +5,7 @@\n #include <rte_alarm.h>\n #include <rte_bus_pci.h>\n #include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n #include <rte_malloc.h>\n \n #include \"cpt_pmd_logs.h\"\n@@ -101,6 +102,97 @@ otx_cpt_periodic_alarm_stop(void *arg)\n \treturn rte_eal_alarm_cancel(otx_cpt_alarm_cb, arg);\n }\n \n+/* PMD ops */\n+\n+static int\n+otx_cpt_dev_config(struct rte_cryptodev *dev __rte_unused,\n+\t\t struct rte_cryptodev_config *config __rte_unused)\n+{\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+\treturn 0;\n+}\n+\n+static int\n+otx_cpt_dev_start(struct rte_cryptodev *c_dev)\n+{\n+\tvoid *cptvf = c_dev->data->dev_private;\n+\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+\n+\treturn otx_cpt_start_device(cptvf);\n+}\n+\n+static void\n+otx_cpt_dev_stop(struct rte_cryptodev *c_dev)\n+{\n+\tvoid *cptvf = c_dev->data->dev_private;\n+\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+\n+\totx_cpt_stop_device(cptvf);\n+}\n+\n+static int\n+otx_cpt_dev_close(struct rte_cryptodev *c_dev)\n+{\n+\tvoid *cptvf = c_dev->data->dev_private;\n+\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+\n+\totx_cpt_periodic_alarm_stop(cptvf);\n+\totx_cpt_deinit_device(cptvf);\n+\n+\treturn 0;\n+}\n+\n+static void\n+otx_cpt_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info)\n+{\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+\tif (info != NULL) {\n+\t\tinfo->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;\n+\t\tinfo->feature_flags = dev->feature_flags;\n+\t\tinfo->capabilities = otx_capabilities;\n+\t\tinfo->sym.max_nb_sessions = 0;\n+\t\tinfo->driver_id = otx_cryptodev_driver_id;\n+\t\tinfo->min_mbuf_headroom_req = OTX_CPT_MIN_HEADROOM_REQ;\n+\t\tinfo->min_mbuf_tailroom_req = OTX_CPT_MIN_TAILROOM_REQ;\n+\t}\n+}\n+\n+static void\n+otx_cpt_stats_get(struct rte_cryptodev *dev __rte_unused,\n+\t\t struct rte_cryptodev_stats *stats __rte_unused)\n+{\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+}\n+\n+static void\n+otx_cpt_stats_reset(struct rte_cryptodev *dev __rte_unused)\n+{\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+}\n+\n+static struct rte_cryptodev_ops cptvf_ops = {\n+\t/* Device related operations */\n+\t.dev_configure = otx_cpt_dev_config,\n+\t.dev_start = otx_cpt_dev_start,\n+\t.dev_stop = otx_cpt_dev_stop,\n+\t.dev_close = otx_cpt_dev_close,\n+\t.dev_infos_get = otx_cpt_dev_info_get,\n+\n+\t.stats_get = otx_cpt_stats_get,\n+\t.stats_reset = otx_cpt_stats_reset,\n+\t.queue_pair_setup = NULL,\n+\t.queue_pair_release = NULL,\n+\t.queue_pair_count = NULL,\n+\n+\t/* Crypto related operations */\n+\t.sym_session_get_size = NULL,\n+\t.sym_session_configure = NULL,\n+\t.sym_session_clear = NULL\n+};\n+\n static void\n otx_cpt_common_vars_init(struct cpt_vf *cptvf)\n {\n@@ -170,7 +262,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)\n \t/* Initialize data path variables used by common code */\n \totx_cpt_common_vars_init(cptvf);\n \n-\tc_dev->dev_ops = NULL;\n+\tc_dev->dev_ops = &cptvf_ops;\n \n \tc_dev->enqueue_burst = NULL;\n \tc_dev->dequeue_burst = NULL;\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h\nindex ac88fa5..b3efecf 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_ops.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h\n@@ -5,6 +5,10 @@\n #ifndef _OTX_CRYPTODEV_OPS_H_\n #define _OTX_CRYPTODEV_OPS_H_\n \n+#define OTX_CPT_MIN_HEADROOM_REQ\t(24)\n+#define OTX_CPT_MIN_TAILROOM_REQ\t(8)\n+#define CPT_NUM_QS_PER_VF\t\t(1)\n+\n void\n cleanup_global_resources(void);\n \n", "prefixes": [ "v2", "13/33" ] }