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GET /api/patches/44182/?format=api
{ "id": 44182, "url": "http://patches.dpdk.org/api/patches/44182/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-9-git-send-email-ajoseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536033560-21541-9-git-send-email-ajoseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536033560-21541-9-git-send-email-ajoseph@caviumnetworks.com", "date": "2018-09-04T03:58:55", "name": "[v2,08/33] crypto/octeontx: add hardware register access for misc poll", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "dae15db7a189226477968ad72fde9c7853907416", "submitter": { "id": 891, "url": "http://patches.dpdk.org/api/people/891/?format=api", "name": "Anoob Joseph", "email": "ajoseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-9-git-send-email-ajoseph@caviumnetworks.com/mbox/", "series": [ { "id": 1164, "url": "http://patches.dpdk.org/api/series/1164/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1164", "date": "2018-09-04T03:58:47", "name": "Adding Cavium's OcteonTX crypto PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/1164/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44182/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/44182/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A9C3058FA;\n\tTue, 4 Sep 2018 06:03:17 +0200 (CEST)", "from NAM01-SN1-obe.outbound.protection.outlook.com\n\t(mail-sn1nam01on0082.outbound.protection.outlook.com [104.47.32.82])\n\tby dpdk.org (Postfix) with ESMTP id 824CD2C02\n\tfor <dev@dpdk.org>; Tue, 4 Sep 2018 06:03:07 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1101.15; Tue, 4 Sep 2018 04:02:16 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=KxbTXUmRadcmtkBbCJ+oZ6wtH+3rVQah0kWQp0UkPAA=;\n\tb=btMqWmnCaRTUu8kPKwYHJMzWa3ANi8dR/jbAwDwaP0qGqj+8Jdc/kjCn/7jm5rKby4H/DZTdCtPhdGyaVCvm1UygOjiSiVjq1SPfCSNvaAaXxBJafVRy1gppKa5fllZtWHyJWKHViDAo6loOHnG4Ea2QAaYgMw5DC8RQoKJMwzA=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <ajoseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Anoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tdev@dpdk.org, Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tRagothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tSrisivasubramanian S <ssrinivasan@caviumnetworks.com>,\n\tTejasree Kondoj <kondoj.tejasree@caviumnetworks.com>", "Date": "Tue, 4 Sep 2018 09:28:55 +0530", "Message-Id": "<1536033560-21541-9-git-send-email-ajoseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "References": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:d::33) To BYAPR07MB4902.namprd07.prod.outlook.com\n\t(2603:10b6:a02:ef::25)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "d55175b0-b0ff-41b8-4ee2-08d6121b3690", "X-Microsoft-Antispam": "BCL:0; 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"dzNom8CaIbud1kq6AmnHa4/tQxTgTPrD0Vv4vUYJ9Q/E1qCg9U3AodFmImX/C6/WyLsJIIIQiAoyCWj1Ldb3Sejv21Q0AEURP15xgfGYeOyYWSDX+egdS3U4Vp6wJ++xadC8WUTXFrnNvW/wFYqMmdDW2wENfEnSoCnkuWsAeJjKAUtu5DcbduAvikeacVG2Hd+i7sB2gFM5sW2D211Upi0WUgAqS8q9ADXjTquHvC0h4dT8t8b5vdwqBQqiPK8NZuoOue+mQArK/njeiqpz2lSBq8WWeFerrHkbpNqqI22Q9SSy7RY8QboQ1jJUcfVbaJ1kwZJ5SIcFulTBLqJ2DdqI9efGoxivYn5ZtzlGyjs=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Sep 2018 04:02:16.8347\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "d55175b0-b0ff-41b8-4ee2-08d6121b3690", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR07MB4902", "Subject": "[dpdk-dev] [PATCH v2 08/33] crypto/octeontx: add hardware register\n\taccess for misc poll", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Anoob Joseph <anoob.joseph@caviumnetworks.com>\n\nAdding hardware register accesses required for misc poll\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 192 +++++++++++++++++++++-\n drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 11 ++\n 2 files changed, 202 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\nindex 211b6ee..02ec3ce 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n@@ -3,11 +3,19 @@\n */\n #include <string.h>\n \n+#include <rte_branch_prediction.h>\n #include <rte_common.h>\n \n #include \"otx_cryptodev_hw_access.h\"\n \n #include \"cpt_pmd_logs.h\"\n+#include \"cpt_hw_types.h\"\n+\n+/*\n+ * VF HAL functions\n+ * Access its own BAR0/4 registers by passing VF number as 0.\n+ * OS/PCI maps them accordingly.\n+ */\n \n static int\n otx_cpt_vf_init(struct cpt_vf *cptvf)\n@@ -22,10 +30,192 @@ otx_cpt_vf_init(struct cpt_vf *cptvf)\n \treturn ret;\n }\n \n+/*\n+ * Read Interrupt status of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static uint64_t\n+otx_cpt_read_vf_misc_intr_status(struct cpt_vf *cptvf)\n+{\n+\treturn CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), CPTX_VQX_MISC_INT(0, 0));\n+}\n+\n+/*\n+ * Clear mailbox interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_mbox_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.mbox = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear instruction NCB read error interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_irde_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.irde = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear NCB result write response error interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_nwrp_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.nwrp = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear swerr interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_swerr_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.swerr = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear hwerr interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_hwerr_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.hwerr = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear translation fault interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_fault_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\tCPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.fault = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\tCPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear doorbell overflow interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.dovf = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n void\n otx_cpt_poll_misc(struct cpt_vf *cptvf)\n {\n-\tRTE_SET_USED(cptvf);\n+\tuint64_t intr;\n+\n+\tintr = otx_cpt_read_vf_misc_intr_status(cptvf);\n+\n+\tif (!intr)\n+\t\treturn;\n+\n+\t/* Check for MISC interrupt types */\n+\tif (likely(intr & CPT_VF_INTR_MBOX_MASK)) {\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Mailbox interrupt 0x%lx on CPT VF %d\",\n+\t\t\tcptvf->dev_name, (unsigned int long)intr, cptvf->vfid);\n+\t\totx_cpt_clear_mbox_intr(cptvf);\n+\t} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {\n+\t\totx_cpt_clear_irde_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Instruction NCB read error interrupt \"\n+\t\t\t\t\"0x%lx on CPT VF %d\", cptvf->dev_name,\n+\t\t\t\t(unsigned int long)intr, cptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_NWRP_MASK)) {\n+\t\totx_cpt_clear_nwrp_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: NCB response write error interrupt 0x%lx\"\n+\t\t\t\t\" on CPT VF %d\", cptvf->dev_name,\n+\t\t\t\t(unsigned int long)intr, cptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_SWERR_MASK)) {\n+\t\totx_cpt_clear_swerr_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Software error interrupt 0x%lx on CPT VF \"\n+\t\t\t\t\"%d\", cptvf->dev_name, (unsigned int long)intr,\n+\t\t\t\tcptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_HWERR_MASK)) {\n+\t\totx_cpt_clear_hwerr_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Hardware error interrupt 0x%lx on CPT VF \"\n+\t\t\t\t\"%d\", cptvf->dev_name, (unsigned int long)intr,\n+\t\t\t\tcptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_FAULT_MASK)) {\n+\t\totx_cpt_clear_fault_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Translation fault interrupt 0x%lx on CPT VF \"\n+\t\t\t\t\"%d\", cptvf->dev_name, (unsigned int long)intr,\n+\t\t\t\tcptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_DOVF_MASK)) {\n+\t\totx_cpt_clear_dovf_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Doorbell overflow interrupt 0x%lx on CPT VF \"\n+\t\t\t\t\"%d\", cptvf->dev_name, (unsigned int long)intr,\n+\t\t\t\tcptvf->vfid);\n+\t} else\n+\t\tCPT_LOG_DP_ERR(\"%s: Unhandled interrupt 0x%lx in CPT VF %d\",\n+\t\t\t\tcptvf->dev_name, (unsigned int long)intr,\n+\t\t\t\tcptvf->vfid);\n }\n \n int\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\nindex 40db69c..f3c7a45 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n@@ -7,6 +7,7 @@\n \n #include <stdbool.h>\n \n+#include <rte_io.h>\n #include <rte_memory.h>\n \n #include \"cpt_common.h\"\n@@ -19,6 +20,16 @@\n /* Default command queue length */\n #define DEFAULT_CMD_QCHUNKS\t2\n \n+#define CPT_CSR_REG_BASE(cpt)\t\t((cpt)->reg_base)\n+\n+/* Read hw register */\n+#define CPT_READ_CSR(__hw_addr, __offset) \\\n+\trte_read64_relaxed((uint8_t *)__hw_addr + __offset)\n+\n+/* Write hw register */\n+#define CPT_WRITE_CSR(__hw_addr, __offset, __val) \\\n+\trte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))\n+\n struct command_chunk {\n \tuint8_t *head;\n \t\t/**< 128-byte aligned real_vaddr */\n", "prefixes": [ "v2", "08/33" ] }