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{
    "id": 44094,
    "url": "http://patches.dpdk.org/api/patches/44094/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180831104040.26678-2-pbhagavatula@caviumnetworks.com/",
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    "date": "2018-08-31T10:40:40",
    "name": "[2/2] app/test-eventdev: add Tx adapter support",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c68a57bf30ba20da4e13859025f7a1902dc6dcc1",
    "submitter": {
        "id": 768,
        "url": "http://patches.dpdk.org/api/people/768/?format=api",
        "name": "Pavan Nikhilesh",
        "email": "pbhagavatula@caviumnetworks.com"
    },
    "delegate": {
        "id": 310,
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        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
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    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180831104040.26678-2-pbhagavatula@caviumnetworks.com/mbox/",
    "series": [
        {
            "id": 1129,
            "url": "http://patches.dpdk.org/api/series/1129/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1129",
            "date": "2018-08-31T10:40:40",
            "name": "[1/2] app/test-eventdev: fix minor typos",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/1129/mbox/"
        }
    ],
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    "check": "fail",
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    "tags": {},
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        "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Pavan.Bhagavatula@cavium.com; ",
        "From": "Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>",
        "To": "jerin.jacob@caviumnetworks.com, santosh.shukla@caviumnetworks.com,\n\tanoob.joseph@caviumnetworks.com, nikhil.rao@intel.com",
        "Cc": "dev@dpdk.org,\n\tPavan Nikhilesh <pbhagavatula@caviumnetworks.com>",
        "Date": "Fri, 31 Aug 2018 16:10:40 +0530",
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        "Subject": "[dpdk-dev]  [PATCH 2/2] app/test-eventdev: add Tx adapter support",
        "X-BeenThere": "dev@dpdk.org",
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        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Convert existing Tx service based pipeline to Tx adapter based APIs and\nsimplify worker functions.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>\n---\n app/test-eventdev/test_pipeline_atq.c    | 216 +++++++++++---------\n app/test-eventdev/test_pipeline_common.c | 193 ++++++------------\n app/test-eventdev/test_pipeline_common.h |  43 ++--\n app/test-eventdev/test_pipeline_queue.c  | 238 ++++++++++++-----------\n 4 files changed, 322 insertions(+), 368 deletions(-)",
    "diff": "diff --git a/app/test-eventdev/test_pipeline_atq.c b/app/test-eventdev/test_pipeline_atq.c\nindex f0b2f9015..54fb9ffd1 100644\n--- a/app/test-eventdev/test_pipeline_atq.c\n+++ b/app/test-eventdev/test_pipeline_atq.c\n@@ -15,7 +15,7 @@ pipeline_atq_nb_event_queues(struct evt_options *opt)\n \treturn rte_eth_dev_count_avail();\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_single_stage_tx(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n@@ -28,23 +28,19 @@ pipeline_atq_worker_single_stage_tx(void *arg)\n \t\t\tcontinue;\n \t\t}\n \n-\t\tif (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\t\t\tpipeline_tx_pkt(ev.mbuf);\n-\t\t\tw->processed_pkts++;\n-\t\t\tcontinue;\n-\t\t}\n-\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n-\t\tpipeline_event_enqueue(dev, port, &ev);\n+\t\trte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);\n+\t\trte_event_eth_tx_adapter_enqueue(dev, port, &ev, 1);\n+\t\tw->processed_pkts++;\n \t}\n \n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_single_stage_fwd(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -54,16 +50,16 @@ pipeline_atq_worker_single_stage_fwd(void *arg)\n \t\t\tcontinue;\n \t\t}\n \n-\t\tw->processed_pkts++;\n-\t\tev.queue_id = tx_queue;\n+\t\tev.queue_id = tx_queue[ev.mbuf->port];\n \t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n \t\tpipeline_event_enqueue(dev, port, &ev);\n+\t\tw->processed_pkts++;\n \t}\n \n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_single_stage_burst_tx(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n@@ -79,27 +75,21 @@ pipeline_atq_worker_single_stage_burst_tx(void *arg)\n \n \t\tfor (i = 0; i < nb_rx; i++) {\n \t\t\trte_prefetch0(ev[i + 1].mbuf);\n-\t\t\tif (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\tpipeline_tx_pkt(ev[i].mbuf);\n-\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n-\t\t\t\tw->processed_pkts++;\n-\t\t\t} else\n-\t\t\t\tpipeline_fwd_event(&ev[i],\n-\t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n \t\t}\n \n-\t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t\trte_event_eth_tx_adapter_enqueue(dev, port, ev, nb_rx);\n+\t\tw->processed_pkts += nb_rx;\n \t}\n \n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_single_stage_burst_fwd(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -112,23 +102,22 @@ pipeline_atq_worker_single_stage_burst_fwd(void *arg)\n \n \t\tfor (i = 0; i < nb_rx; i++) {\n \t\t\trte_prefetch0(ev[i + 1].mbuf);\n-\t\t\tev[i].queue_id = tx_queue;\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n+\t\t\tev[i].queue_id = tx_queue[ev[i].mbuf->port];\n \t\t\tpipeline_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);\n-\t\t\tw->processed_pkts++;\n \t\t}\n \n \t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t\tw->processed_pkts += nb_rx;\n \t}\n \n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_multi_stage_tx(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages;\n-\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -141,13 +130,12 @@ pipeline_atq_worker_multi_stage_tx(void *arg)\n \t\tcq_id = ev.sub_event_type % nb_stages;\n \n \t\tif (cq_id == last_queue) {\n-\t\t\tif (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\tpipeline_tx_pkt(ev.mbuf);\n-\t\t\t\tw->processed_pkts++;\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n+\t\t\t/* Map to 0th queue. */\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);\n+\t\t\trte_event_eth_tx_adapter_enqueue(dev, port,\n+\t\t\t\t\t&ev, 1);\n+\t\t\tw->processed_pkts++;\n+\t\t\tcontinue;\n \t\t} else {\n \t\t\tev.sub_event_type++;\n \t\t\tpipeline_fwd_event(&ev, sched_type_list[cq_id]);\n@@ -158,12 +146,11 @@ pipeline_atq_worker_multi_stage_tx(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_multi_stage_fwd(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -176,9 +163,9 @@ pipeline_atq_worker_multi_stage_fwd(void *arg)\n \t\tcq_id = ev.sub_event_type % nb_stages;\n \n \t\tif (cq_id == last_queue) {\n-\t\t\tw->processed_pkts++;\n-\t\t\tev.queue_id = tx_queue;\n+\t\t\tev.queue_id = tx_queue[ev.mbuf->port];\n \t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n+\t\t\tw->processed_pkts++;\n \t\t} else {\n \t\t\tev.sub_event_type++;\n \t\t\tpipeline_fwd_event(&ev, sched_type_list[cq_id]);\n@@ -189,11 +176,10 @@ pipeline_atq_worker_multi_stage_fwd(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_multi_stage_burst_tx(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -209,16 +195,13 @@ pipeline_atq_worker_multi_stage_burst_tx(void *arg)\n \t\t\tcq_id = ev[i].sub_event_type % nb_stages;\n \n \t\t\tif (cq_id == last_queue) {\n-\t\t\t\tif (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\t\tpipeline_tx_pkt(ev[i].mbuf);\n-\t\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n-\t\t\t\t\tw->processed_pkts++;\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n-\n-\t\t\t\tpipeline_fwd_event(&ev[i],\n-\t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n+\t\t\t\t/* Map to 0th queue. */\n+\t\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n+\t\t\t\trte_event_eth_tx_adapter_enqueue(dev, port,\n+\t\t\t\t\t\t&ev[i], 1);\n+\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n+\t\t\t\tw->processed_pkts++;\n+\t\t\t\tcontinue;\n \t\t\t} else {\n \t\t\t\tev[i].sub_event_type++;\n \t\t\t\tpipeline_fwd_event(&ev[i],\n@@ -231,12 +214,11 @@ pipeline_atq_worker_multi_stage_burst_tx(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_multi_stage_burst_fwd(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -253,9 +235,10 @@ pipeline_atq_worker_multi_stage_burst_fwd(void *arg)\n \n \t\t\tif (cq_id == last_queue) {\n \t\t\t\tw->processed_pkts++;\n-\t\t\t\tev[i].queue_id = tx_queue;\n+\t\t\t\tev[i].queue_id = tx_queue[ev[i].mbuf->port];\n \t\t\t\tpipeline_fwd_event(&ev[i],\n \t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n+\n \t\t\t} else {\n \t\t\t\tev[i].sub_event_type++;\n \t\t\t\tpipeline_fwd_event(&ev[i],\n@@ -274,27 +257,27 @@ worker_wrapper(void *arg)\n \tstruct worker_data *w  = arg;\n \tstruct evt_options *opt = w->t->opt;\n \tconst bool burst = evt_has_burst_mode(w->dev_id);\n-\tconst bool mt_safe = !w->t->mt_unsafe;\n+\tconst bool internal_port = w->t->internal_port;\n \tconst uint8_t nb_stages = opt->nb_stages;\n \tRTE_SET_USED(opt);\n \n \tif (nb_stages == 1) {\n-\t\tif (!burst && mt_safe)\n+\t\tif (!burst && internal_port)\n \t\t\treturn pipeline_atq_worker_single_stage_tx(arg);\n-\t\telse if (!burst && !mt_safe)\n+\t\telse if (!burst && !internal_port)\n \t\t\treturn pipeline_atq_worker_single_stage_fwd(arg);\n-\t\telse if (burst && mt_safe)\n+\t\telse if (burst && internal_port)\n \t\t\treturn pipeline_atq_worker_single_stage_burst_tx(arg);\n-\t\telse if (burst && !mt_safe)\n+\t\telse if (burst && !internal_port)\n \t\t\treturn pipeline_atq_worker_single_stage_burst_fwd(arg);\n \t} else {\n-\t\tif (!burst && mt_safe)\n+\t\tif (!burst && internal_port)\n \t\t\treturn pipeline_atq_worker_multi_stage_tx(arg);\n-\t\telse if (!burst && !mt_safe)\n+\t\telse if (!burst && !internal_port)\n \t\t\treturn pipeline_atq_worker_multi_stage_fwd(arg);\n-\t\tif (burst && mt_safe)\n+\t\tif (burst && internal_port)\n \t\t\treturn pipeline_atq_worker_multi_stage_burst_tx(arg);\n-\t\telse if (burst && !mt_safe)\n+\t\telse if (burst && !internal_port)\n \t\t\treturn pipeline_atq_worker_multi_stage_burst_fwd(arg);\n \t}\n \trte_panic(\"invalid worker\\n\");\n@@ -303,10 +286,6 @@ worker_wrapper(void *arg)\n static int\n pipeline_atq_launch_lcores(struct evt_test *test, struct evt_options *opt)\n {\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\n-\tif (t->mt_unsafe)\n-\t\trte_service_component_runstate_set(t->tx_service.service_id, 1);\n \treturn pipeline_launch_lcores(test, opt, worker_wrapper);\n }\n \n@@ -317,23 +296,25 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \tint nb_ports;\n \tint nb_queues;\n \tuint8_t queue;\n-\tstruct rte_event_dev_info info;\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\tuint8_t tx_evqueue_id = 0;\n+\tuint8_t tx_evqueue_id[RTE_MAX_ETHPORTS] = {0};\n \tuint8_t queue_arr[RTE_EVENT_MAX_QUEUES_PER_DEV];\n \tuint8_t nb_worker_queues = 0;\n+\tuint8_t tx_evport_id = 0;\n+\tuint16_t prod = 0;\n+\tstruct rte_event_dev_info info;\n+\tstruct test_pipeline *t = evt_test_priv(test);\n \n \tnb_ports = evt_nr_active_lcores(opt->wlcores);\n \tnb_queues = rte_eth_dev_count_avail();\n \n-\t/* One extra port and queueu for Tx service */\n-\tif (t->mt_unsafe) {\n-\t\ttx_evqueue_id = nb_queues;\n-\t\tnb_ports++;\n-\t\tnb_queues++;\n+\t/* One queue for Tx service */\n+\tif (!t->internal_port) {\n+\t\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\t\ttx_evqueue_id[prod] = nb_queues;\n+\t\t\tnb_queues++;\n+\t\t}\n \t}\n \n-\n \trte_event_dev_info_get(opt->dev_id, &info);\n \n \tconst struct rte_event_dev_config config = {\n@@ -361,13 +342,15 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \tfor (queue = 0; queue < nb_queues; queue++) {\n \t\tq_conf.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;\n \n-\t\tif (t->mt_unsafe) {\n-\t\t\tif (queue == tx_evqueue_id) {\n-\t\t\t\tq_conf.event_queue_cfg =\n-\t\t\t\t\tRTE_EVENT_QUEUE_CFG_SINGLE_LINK;\n-\t\t\t} else {\n-\t\t\t\tqueue_arr[nb_worker_queues] = queue;\n-\t\t\t\tnb_worker_queues++;\n+\t\tif (!t->internal_port) {\n+\t\t\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\t\t\tif (queue == tx_evqueue_id[prod]) {\n+\t\t\t\t\tq_conf.event_queue_cfg =\n+\t\t\t\t\t\tRTE_EVENT_QUEUE_CFG_SINGLE_LINK;\n+\t\t\t\t} else {\n+\t\t\t\t\tqueue_arr[nb_worker_queues] = queue;\n+\t\t\t\t\tnb_worker_queues++;\n+\t\t\t\t}\n \t\t\t}\n \t\t}\n \n@@ -388,14 +371,11 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\t\t.new_event_threshold = info.max_num_events,\n \t};\n \n-\tif (t->mt_unsafe) {\n+\tif (!t->internal_port) {\n \t\tret = pipeline_event_port_setup(test, opt, queue_arr,\n \t\t\t\tnb_worker_queues, p_conf);\n \t\tif (ret)\n \t\t\treturn ret;\n-\n-\t\tret = pipeline_event_tx_service_setup(test, opt, tx_evqueue_id,\n-\t\t\t\tnb_ports - 1, p_conf);\n \t} else\n \t\tret = pipeline_event_port_setup(test, opt, NULL, nb_queues,\n \t\t\t\tp_conf);\n@@ -424,14 +404,17 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t *\tstride = 1\n \t *\n \t *\tevent queue pipelines:\n-\t *\teth0 -> q0\n-\t *\t\t  } (q3->tx) Tx service\n-\t *\teth1 -> q1\n+\t *\teth0 -> q0 \\\n+\t *\t\t    q3->tx\n+\t *\teth1 -> q1 /\n \t *\n \t *\tq0,q1 are configured as stated above.\n \t *\tq3 configured as SINGLE_LINK|ATOMIC.\n \t */\n \tret = pipeline_event_rx_adapter_setup(opt, 1, p_conf);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = pipeline_event_tx_adapter_setup(opt, p_conf);\n \tif (ret)\n \t\treturn ret;\n \n@@ -445,12 +428,59 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\t}\n \t}\n \n+\t/* Connect the tx_evqueue_id to the Tx adapter port */\n+\tif (!t->internal_port) {\n+\t\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\t\tret = rte_event_eth_tx_adapter_event_port_get(prod,\n+\t\t\t\t\t&tx_evport_id);\n+\t\t\tif (ret) {\n+\t\t\t\tevt_err(\"Unable to get Tx adapter[%d]\", prod);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tif (rte_event_port_link(opt->dev_id, tx_evport_id,\n+\t\t\t\t\t\t&tx_evqueue_id[prod],\n+\t\t\t\t\t\tNULL, 1) != 1) {\n+\t\t\t\tevt_err(\"Unable to link Tx adptr[%d] evprt[%d]\",\n+\t\t\t\t\t\tprod, tx_evport_id);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\tret = rte_eth_dev_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Ethernet dev [%d] failed to start.\"\n+\t\t\t\t\t\" Using synthetic producer\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t}\n+\n \tret = rte_event_dev_start(opt->dev_id);\n \tif (ret) {\n \t\tevt_err(\"failed to start eventdev %d\", opt->dev_id);\n \t\treturn ret;\n \t}\n \n+\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\tret = rte_event_eth_rx_adapter_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Rx adapter[%d] start failed\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret = rte_event_eth_tx_adapter_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Tx adapter[%d] start failed\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tmemcpy(t->tx_evqueue_id, tx_evqueue_id, sizeof(uint8_t) *\n+\t\t\tRTE_MAX_ETHPORTS);\n+\n \treturn 0;\n }\n \ndiff --git a/app/test-eventdev/test_pipeline_common.c b/app/test-eventdev/test_pipeline_common.c\nindex a54068df3..7f858e23f 100644\n--- a/app/test-eventdev/test_pipeline_common.c\n+++ b/app/test-eventdev/test_pipeline_common.c\n@@ -5,58 +5,6 @@\n \n #include \"test_pipeline_common.h\"\n \n-static int32_t\n-pipeline_event_tx_burst_service_func(void *args)\n-{\n-\n-\tint i;\n-\tstruct tx_service_data *tx = args;\n-\tconst uint8_t dev = tx->dev_id;\n-\tconst uint8_t port = tx->port_id;\n-\tstruct rte_event ev[BURST_SIZE + 1];\n-\n-\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);\n-\n-\tif (!nb_rx) {\n-\t\tfor (i = 0; i < tx->nb_ethports; i++)\n-\t\t\trte_eth_tx_buffer_flush(i, 0, tx->tx_buf[i]);\n-\t\treturn 0;\n-\t}\n-\n-\tfor (i = 0; i < nb_rx; i++) {\n-\t\tstruct rte_mbuf *m = ev[i].mbuf;\n-\t\trte_eth_tx_buffer(m->port, 0, tx->tx_buf[m->port], m);\n-\t}\n-\ttx->processed_pkts += nb_rx;\n-\n-\treturn 0;\n-}\n-\n-static int32_t\n-pipeline_event_tx_service_func(void *args)\n-{\n-\n-\tint i;\n-\tstruct tx_service_data *tx = args;\n-\tconst uint8_t dev = tx->dev_id;\n-\tconst uint8_t port = tx->port_id;\n-\tstruct rte_event ev;\n-\n-\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n-\n-\tif (!nb_rx) {\n-\t\tfor (i = 0; i < tx->nb_ethports; i++)\n-\t\t\trte_eth_tx_buffer_flush(i, 0, tx->tx_buf[i]);\n-\t\treturn 0;\n-\t}\n-\n-\tstruct rte_mbuf *m = ev.mbuf;\n-\trte_eth_tx_buffer(m->port, 0, tx->tx_buf[m->port], m);\n-\ttx->processed_pkts++;\n-\n-\treturn 0;\n-}\n-\n int\n pipeline_test_result(struct evt_test *test, struct evt_options *opt)\n {\n@@ -97,11 +45,8 @@ processed_pkts(struct test_pipeline *t)\n \tuint64_t total = 0;\n \n \trte_smp_rmb();\n-\tif (t->mt_unsafe)\n-\t\ttotal = t->tx_service.processed_pkts;\n-\telse\n-\t\tfor (i = 0; i < t->nb_workers; i++)\n-\t\t\ttotal += t->worker[i].processed_pkts;\n+\tfor (i = 0; i < t->nb_workers; i++)\n+\t\ttotal += t->worker[i].processed_pkts;\n \n \treturn total;\n }\n@@ -215,7 +160,6 @@ pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt)\n {\n \tuint16_t i;\n \tuint8_t nb_queues = 1;\n-\tuint8_t mt_state = 0;\n \tstruct test_pipeline *t = evt_test_priv(test);\n \tstruct rte_eth_rxconf rx_conf;\n \tstruct rte_eth_conf port_conf = {\n@@ -238,13 +182,13 @@ pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\treturn -ENODEV;\n \t}\n \n+\tt->internal_port = 0;\n \tRTE_ETH_FOREACH_DEV(i) {\n \t\tstruct rte_eth_dev_info dev_info;\n \t\tstruct rte_eth_conf local_port_conf = port_conf;\n+\t\tuint32_t caps = 0;\n \n \t\trte_eth_dev_info_get(i, &dev_info);\n-\t\tmt_state = !(dev_info.tx_offload_capa &\n-\t\t\t\tDEV_TX_OFFLOAD_MT_LOCKFREE);\n \t\trx_conf = dev_info.default_rxconf;\n \t\trx_conf.offloads = port_conf.rxmode.offloads;\n \n@@ -279,11 +223,9 @@ pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\t\treturn -EINVAL;\n \t\t}\n \n-\t\tt->mt_unsafe |= mt_state;\n-\t\tt->tx_service.tx_buf[i] =\n-\t\t\trte_malloc(NULL, RTE_ETH_TX_BUFFER_SIZE(BURST_SIZE), 0);\n-\t\tif (t->tx_service.tx_buf[i] == NULL)\n-\t\t\trte_panic(\"Unable to allocate Tx buffer memory.\");\n+\t\trte_event_eth_tx_adapter_caps_get(opt->dev_id, i, &caps);\n+\t\tif ((caps & RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT))\n+\t\t\tt->internal_port = 1;\n \t\trte_eth_promiscuous_enable(i);\n \t}\n \n@@ -295,7 +237,6 @@ pipeline_event_port_setup(struct evt_test *test, struct evt_options *opt,\n \t\tuint8_t *queue_arr, uint8_t nb_queues,\n \t\tconst struct rte_event_port_conf p_conf)\n {\n-\tint i;\n \tint ret;\n \tuint8_t port;\n \tstruct test_pipeline *t = evt_test_priv(test);\n@@ -321,10 +262,9 @@ pipeline_event_port_setup(struct evt_test *test, struct evt_options *opt,\n \t\t\t\t\t\t0) != nb_queues)\n \t\t\t\tgoto link_fail;\n \t\t} else {\n-\t\t\tfor (i = 0; i < nb_queues; i++) {\n-\t\t\t\tif (rte_event_port_link(opt->dev_id, port,\n-\t\t\t\t\t\t&queue_arr[i], NULL, 1) != 1)\n-\t\t\t\t\tgoto link_fail;\n+\t\t\tif (rte_event_port_link(opt->dev_id, port, queue_arr,\n+\t\t\t\t\tNULL, nb_queues) != nb_queues) {\n+\t\t\t\tgoto link_fail;\n \t\t\t}\n \t\t}\n \t}\n@@ -385,80 +325,64 @@ pipeline_event_rx_adapter_setup(struct evt_options *opt, uint8_t stride,\n \t\t\t}\n \t\t}\n \n-\t\tret = rte_eth_dev_start(prod);\n-\t\tif (ret) {\n-\t\t\tevt_err(\"Ethernet dev [%d] failed to start.\"\n-\t\t\t\t\t\" Using synthetic producer\", prod);\n-\t\t\treturn ret;\n-\t\t}\n-\n-\t\tret = rte_event_eth_rx_adapter_start(prod);\n-\t\tif (ret) {\n-\t\t\tevt_err(\"Rx adapter[%d] start failed\", prod);\n-\t\t\treturn ret;\n-\t\t}\n-\t\tprintf(\"%s: Port[%d] using Rx adapter[%d] started\\n\", __func__,\n-\t\t\t\tprod, prod);\n+\t\tprintf(\"%s: Port[%d] using Rx adapter[%d] configured\\n\",\n+\t\t\t\t__func__, prod, prod);\n \t}\n \n \treturn ret;\n }\n \n int\n-pipeline_event_tx_service_setup(struct evt_test *test, struct evt_options *opt,\n-\t\tuint8_t tx_queue_id, uint8_t tx_port_id,\n-\t\tconst struct rte_event_port_conf p_conf)\n+pipeline_event_tx_adapter_setup(struct evt_options *opt,\n+\t\tstruct rte_event_port_conf port_conf)\n {\n-\tint ret;\n-\tstruct rte_service_spec serv;\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\tstruct tx_service_data *tx = &t->tx_service;\n+\tint ret = 0;\n+\tuint16_t consm = 0;\n \n-\tret = rte_event_port_setup(opt->dev_id, tx_port_id, &p_conf);\n-\tif (ret) {\n-\t\tevt_err(\"failed to setup port %d\", tx_port_id);\n-\t\treturn ret;\n-\t}\n+\tRTE_ETH_FOREACH_DEV(consm) {\n+\t\tuint32_t cap;\n \n-\tif (rte_event_port_link(opt->dev_id, tx_port_id, &tx_queue_id,\n-\t\t\t\tNULL, 1) != 1) {\n-\t\tevt_err(\"failed to link queues to port %d\", tx_port_id);\n-\t\treturn -EINVAL;\n-\t}\n+\t\tret = rte_event_eth_tx_adapter_caps_get(opt->dev_id,\n+\t\t\t\tconsm, &cap);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"failed to get event tx adapter[%d] caps\",\n+\t\t\t\t\tconsm);\n+\t\t\treturn ret;\n+\t\t}\n \n-\ttx->dev_id = opt->dev_id;\n-\ttx->queue_id = tx_queue_id;\n-\ttx->port_id = tx_port_id;\n-\ttx->nb_ethports = rte_eth_dev_count_avail();\n-\ttx->t = t;\n-\n-\t/* Register Tx service */\n-\tmemset(&serv, 0, sizeof(struct rte_service_spec));\n-\tsnprintf(serv.name, sizeof(serv.name), \"Tx_service\");\n-\n-\tif (evt_has_burst_mode(opt->dev_id))\n-\t\tserv.callback = pipeline_event_tx_burst_service_func;\n-\telse\n-\t\tserv.callback = pipeline_event_tx_service_func;\n-\n-\tserv.callback_userdata = (void *)tx;\n-\tret = rte_service_component_register(&serv, &tx->service_id);\n-\tif (ret) {\n-\t\tevt_err(\"failed to register Tx service\");\n-\t\treturn ret;\n-\t}\n+\t\tret = rte_event_eth_tx_adapter_create(consm, opt->dev_id,\n+\t\t\t\t&port_conf);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"failed to create tx adapter[%d]\", consm);\n+\t\t\treturn ret;\n+\t\t}\n \n-\tret = evt_service_setup(tx->service_id);\n-\tif (ret) {\n-\t\tevt_err(\"Failed to setup service core for Tx service\\n\");\n-\t\treturn ret;\n-\t}\n+\t\tret = rte_event_eth_tx_adapter_queue_add(consm, consm, -1);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"failed to add tx queues to adapter[%d]\",\n+\t\t\t\t\tconsm);\n+\t\t\treturn ret;\n+\t\t}\n \n-\trte_service_runstate_set(tx->service_id, 1);\n+\t\tif (!(cap & RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT)) {\n+\t\t\tuint32_t service_id;\n \n-\treturn 0;\n-}\n+\t\t\trte_event_eth_tx_adapter_service_id_get(consm,\n+\t\t\t\t\t&service_id);\n+\t\t\tret = evt_service_setup(service_id);\n+\t\t\tif (ret) {\n+\t\t\t\tevt_err(\"Failed to setup service core\"\n+\t\t\t\t\t\t\" for Tx adapter\\n\");\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\tprintf(\"%s: Port[%d] using Tx adapter[%d] Configured\\n\",\n+\t\t\t\t__func__, consm, consm);\n+\t}\n \n+\treturn ret;\n+}\n \n void\n pipeline_ethdev_destroy(struct evt_test *test, struct evt_options *opt)\n@@ -466,16 +390,10 @@ pipeline_ethdev_destroy(struct evt_test *test, struct evt_options *opt)\n \tuint16_t i;\n \tRTE_SET_USED(test);\n \tRTE_SET_USED(opt);\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\n-\tif (t->mt_unsafe) {\n-\t\trte_service_component_runstate_set(t->tx_service.service_id, 0);\n-\t\trte_service_runstate_set(t->tx_service.service_id, 0);\n-\t\trte_service_component_unregister(t->tx_service.service_id);\n-\t}\n \n \tRTE_ETH_FOREACH_DEV(i) {\n \t\trte_event_eth_rx_adapter_stop(i);\n+\t\trte_event_eth_tx_adapter_stop(i);\n \t\trte_eth_dev_stop(i);\n \t}\n }\n@@ -485,7 +403,6 @@ pipeline_eventdev_destroy(struct evt_test *test, struct evt_options *opt)\n {\n \tRTE_SET_USED(test);\n \n-\trte_event_dev_stop(opt->dev_id);\n \trte_event_dev_close(opt->dev_id);\n }\n \ndiff --git a/app/test-eventdev/test_pipeline_common.h b/app/test-eventdev/test_pipeline_common.h\nindex 9cd6b905b..b8939db81 100644\n--- a/app/test-eventdev/test_pipeline_common.h\n+++ b/app/test-eventdev/test_pipeline_common.h\n@@ -14,6 +14,7 @@\n #include <rte_ethdev.h>\n #include <rte_eventdev.h>\n #include <rte_event_eth_rx_adapter.h>\n+#include <rte_event_eth_tx_adapter.h>\n #include <rte_lcore.h>\n #include <rte_malloc.h>\n #include <rte_mempool.h>\n@@ -26,6 +27,9 @@\n #include \"evt_options.h\"\n #include \"evt_test.h\"\n \n+#define PIPELINE_TX_ADPTR_ENQ 0x1\n+#define PIPELINE_TX_ADPTR_FWD 0x2\n+\n struct test_pipeline;\n \n struct worker_data {\n@@ -35,30 +39,19 @@ struct worker_data {\n \tstruct test_pipeline *t;\n } __rte_cache_aligned;\n \n-struct tx_service_data {\n-\tuint8_t dev_id;\n-\tuint8_t queue_id;\n-\tuint8_t port_id;\n-\tuint32_t service_id;\n-\tuint64_t processed_pkts;\n-\tuint16_t nb_ethports;\n-\tstruct rte_eth_dev_tx_buffer *tx_buf[RTE_MAX_ETHPORTS];\n-\tstruct test_pipeline *t;\n-} __rte_cache_aligned;\n-\n struct test_pipeline {\n \t/* Don't change the offset of \"done\". Signal handler use this memory\n \t * to terminate all lcores work.\n \t */\n \tint done;\n \tuint8_t nb_workers;\n-\tuint8_t mt_unsafe;\n+\tuint8_t internal_port;\n+\tuint8_t tx_evqueue_id[RTE_MAX_ETHPORTS];\n \tenum evt_test_result result;\n \tuint32_t nb_flows;\n \tuint64_t outstand_pkts;\n \tstruct rte_mempool *pool;\n \tstruct worker_data worker[EVT_MAX_PORTS];\n-\tstruct tx_service_data tx_service;\n \tstruct evt_options *opt;\n \tuint8_t sched_type_list[EVT_MAX_STAGES] __rte_cache_aligned;\n } __rte_cache_aligned;\n@@ -70,7 +63,7 @@ struct test_pipeline {\n \tstruct test_pipeline *t = w->t;   \\\n \tconst uint8_t dev = w->dev_id;    \\\n \tconst uint8_t port = w->port_id;  \\\n-\tstruct rte_event ev\n+\tstruct rte_event ev __rte_cache_aligned\n \n #define PIPELINE_WORKER_SINGLE_STAGE_BURST_INIT \\\n \tint i;                                  \\\n@@ -78,7 +71,7 @@ struct test_pipeline {\n \tstruct test_pipeline *t = w->t;         \\\n \tconst uint8_t dev = w->dev_id;          \\\n \tconst uint8_t port = w->port_id;        \\\n-\tstruct rte_event ev[BURST_SIZE + 1]\n+\tstruct rte_event ev[BURST_SIZE + 1] __rte_cache_aligned\n \n #define PIPELINE_WORKER_MULTI_STAGE_INIT                         \\\n \tstruct worker_data *w  = arg;                            \\\n@@ -88,10 +81,11 @@ struct test_pipeline {\n \tconst uint8_t port = w->port_id;                         \\\n \tconst uint8_t last_queue = t->opt->nb_stages - 1;        \\\n \tuint8_t *const sched_type_list = &t->sched_type_list[0]; \\\n-\tstruct rte_event ev\n+\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\t \\\n+\tstruct rte_event ev __rte_cache_aligned\n \n #define PIPELINE_WORKER_MULTI_STAGE_BURST_INIT                   \\\n-\tint i;                                  \\\n+\tint i;                                                   \\\n \tstruct worker_data *w  = arg;                            \\\n \tstruct test_pipeline *t = w->t;                          \\\n \tuint8_t cq_id;                                           \\\n@@ -99,7 +93,8 @@ struct test_pipeline {\n \tconst uint8_t port = w->port_id;                         \\\n \tconst uint8_t last_queue = t->opt->nb_stages - 1;        \\\n \tuint8_t *const sched_type_list = &t->sched_type_list[0]; \\\n-\tstruct rte_event ev[BURST_SIZE + 1]\n+\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\t \\\n+\tstruct rte_event ev[BURST_SIZE + 1] __rte_cache_aligned\n \n static __rte_always_inline void\n pipeline_fwd_event(struct rte_event *ev, uint8_t sched)\n@@ -130,13 +125,6 @@ pipeline_event_enqueue_burst(const uint8_t dev, const uint8_t port,\n \t}\n }\n \n-static __rte_always_inline void\n-pipeline_tx_pkt(struct rte_mbuf *mbuf)\n-{\n-\twhile (rte_eth_tx_burst(mbuf->port, 0, &mbuf, 1) != 1)\n-\t\trte_pause();\n-}\n-\n static inline int\n pipeline_nb_event_ports(struct evt_options *opt)\n {\n@@ -149,9 +137,8 @@ int pipeline_test_setup(struct evt_test *test, struct evt_options *opt);\n int pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt);\n int pipeline_event_rx_adapter_setup(struct evt_options *opt, uint8_t stride,\n \t\tstruct rte_event_port_conf prod_conf);\n-int pipeline_event_tx_service_setup(struct evt_test *test,\n-\t\tstruct evt_options *opt, uint8_t tx_queue_id,\n-\t\tuint8_t tx_port_id, const struct rte_event_port_conf p_conf);\n+int pipeline_event_tx_adapter_setup(struct evt_options *opt,\n+\t\tstruct rte_event_port_conf prod_conf);\n int pipeline_mempool_setup(struct evt_test *test, struct evt_options *opt);\n int pipeline_event_port_setup(struct evt_test *test, struct evt_options *opt,\n \t\tuint8_t *queue_arr, uint8_t nb_queues,\ndiff --git a/app/test-eventdev/test_pipeline_queue.c b/app/test-eventdev/test_pipeline_queue.c\nindex 2e0d93d99..e1153573b 100644\n--- a/app/test-eventdev/test_pipeline_queue.c\n+++ b/app/test-eventdev/test_pipeline_queue.c\n@@ -15,7 +15,7 @@ pipeline_queue_nb_event_queues(struct evt_options *opt)\n \treturn (eth_count * opt->nb_stages) + eth_count;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_single_stage_tx(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n@@ -29,9 +29,12 @@ pipeline_queue_worker_single_stage_tx(void *arg)\n \t\t}\n \n \t\tif (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\t\t\tpipeline_tx_pkt(ev.mbuf);\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);\n+\t\t\trte_event_eth_tx_adapter_enqueue(dev, port,\n+\t\t\t\t\t&ev, 1);\n \t\t\tw->processed_pkts++;\n \t\t} else {\n+\n \t\t\tev.queue_id++;\n \t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n \t\t\tpipeline_event_enqueue(dev, port, &ev);\n@@ -41,11 +44,11 @@ pipeline_queue_worker_single_stage_tx(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_single_stage_fwd(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -55,7 +58,8 @@ pipeline_queue_worker_single_stage_fwd(void *arg)\n \t\t\tcontinue;\n \t\t}\n \n-\t\tev.queue_id = tx_queue;\n+\t\tev.queue_id = tx_queue[ev.mbuf->port];\n+\t\trte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);\n \t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n \t\tpipeline_event_enqueue(dev, port, &ev);\n \t\tw->processed_pkts++;\n@@ -64,7 +68,7 @@ pipeline_queue_worker_single_stage_fwd(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_single_stage_burst_tx(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n@@ -81,8 +85,9 @@ pipeline_queue_worker_single_stage_burst_tx(void *arg)\n \t\tfor (i = 0; i < nb_rx; i++) {\n \t\t\trte_prefetch0(ev[i + 1].mbuf);\n \t\t\tif (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\tpipeline_tx_pkt(ev[i].mbuf);\n+\t\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n+\t\t\t\trte_event_eth_tx_adapter_enqueue(dev, port,\n+\t\t\t\t\t\t&ev[i], 1);\n \t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n \t\t\t\tw->processed_pkts++;\n \t\t\t} else {\n@@ -98,11 +103,11 @@ pipeline_queue_worker_single_stage_burst_tx(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_single_stage_burst_fwd(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -115,23 +120,24 @@ pipeline_queue_worker_single_stage_burst_fwd(void *arg)\n \n \t\tfor (i = 0; i < nb_rx; i++) {\n \t\t\trte_prefetch0(ev[i + 1].mbuf);\n-\t\t\tev[i].queue_id = tx_queue;\n+\t\t\tev[i].queue_id = tx_queue[ev[i].mbuf->port];\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n \t\t\tpipeline_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);\n-\t\t\tw->processed_pkts++;\n \t\t}\n \n \t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t\tw->processed_pkts += nb_rx;\n \t}\n \n \treturn 0;\n }\n \n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_multi_stage_tx(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -143,18 +149,16 @@ pipeline_queue_worker_multi_stage_tx(void *arg)\n \n \t\tcq_id = ev.queue_id % nb_stages;\n \n-\t\tif (cq_id >= last_queue) {\n-\t\t\tif (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\tpipeline_tx_pkt(ev.mbuf);\n-\t\t\t\tw->processed_pkts++;\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t\tev.queue_id += (cq_id == last_queue) ? 1 : 0;\n-\t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n+\t\tif (ev.queue_id == tx_queue[ev.mbuf->port]) {\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);\n+\t\t\trte_event_eth_tx_adapter_enqueue(dev, port, &ev, 1);\n+\t\t\tw->processed_pkts++;\n+\t\t\tcontinue;\n \t\t} else {\n \t\t\tev.queue_id++;\n-\t\t\tpipeline_fwd_event(&ev, sched_type_list[cq_id]);\n+\t\t\tpipeline_fwd_event(&ev, cq_id != last_queue ?\n+\t\t\t\t\tsched_type_list[cq_id] :\n+\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n \t\t}\n \n \t\tpipeline_event_enqueue(dev, port, &ev);\n@@ -162,12 +166,11 @@ pipeline_queue_worker_multi_stage_tx(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_multi_stage_fwd(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -180,7 +183,8 @@ pipeline_queue_worker_multi_stage_fwd(void *arg)\n \t\tcq_id = ev.queue_id % nb_stages;\n \n \t\tif (cq_id == last_queue) {\n-\t\t\tev.queue_id = tx_queue;\n+\t\t\tev.queue_id = tx_queue[ev.mbuf->port];\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);\n \t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n \t\t\tw->processed_pkts++;\n \t\t} else {\n@@ -193,11 +197,11 @@ pipeline_queue_worker_multi_stage_fwd(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_multi_stage_burst_tx(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -212,22 +216,19 @@ pipeline_queue_worker_multi_stage_burst_tx(void *arg)\n \t\t\trte_prefetch0(ev[i + 1].mbuf);\n \t\t\tcq_id = ev[i].queue_id % nb_stages;\n \n-\t\t\tif (cq_id >= last_queue) {\n-\t\t\t\tif (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\t\tpipeline_tx_pkt(ev[i].mbuf);\n-\t\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n-\t\t\t\t\tw->processed_pkts++;\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n+\t\t\tif (ev[i].queue_id == tx_queue[ev[i].mbuf->port]) {\n+\t\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n+\t\t\t\trte_event_eth_tx_adapter_enqueue(dev, port,\n+\t\t\t\t\t\t&ev[i], 1);\n+\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n+\t\t\t\tw->processed_pkts++;\n+\t\t\t\tcontinue;\n \n-\t\t\t\tev[i].queue_id += (cq_id == last_queue) ? 1 : 0;\n-\t\t\t\tpipeline_fwd_event(&ev[i],\n-\t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n \t\t\t} else {\n \t\t\t\tev[i].queue_id++;\n-\t\t\t\tpipeline_fwd_event(&ev[i],\n-\t\t\t\t\t\tsched_type_list[cq_id]);\n+\t\t\t\tpipeline_fwd_event(&ev[i], cq_id != last_queue ?\n+\t\t\t\t\t\tsched_type_list[cq_id] :\n+\t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n \t\t\t}\n \n \t\t}\n@@ -237,12 +238,11 @@ pipeline_queue_worker_multi_stage_burst_tx(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_multi_stage_burst_fwd(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -258,7 +258,8 @@ pipeline_queue_worker_multi_stage_burst_fwd(void *arg)\n \t\t\tcq_id = ev[i].queue_id % nb_stages;\n \n \t\t\tif (cq_id == last_queue) {\n-\t\t\t\tev[i].queue_id = tx_queue;\n+\t\t\t\tev[i].queue_id = tx_queue[ev[i].mbuf->port];\n+\t\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n \t\t\t\tpipeline_fwd_event(&ev[i],\n \t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n \t\t\t\tw->processed_pkts++;\n@@ -280,28 +281,28 @@ worker_wrapper(void *arg)\n \tstruct worker_data *w  = arg;\n \tstruct evt_options *opt = w->t->opt;\n \tconst bool burst = evt_has_burst_mode(w->dev_id);\n-\tconst bool mt_safe = !w->t->mt_unsafe;\n+\tconst bool internal_port = w->t->internal_port;\n \tconst uint8_t nb_stages = opt->nb_stages;\n \tRTE_SET_USED(opt);\n \n \tif (nb_stages == 1) {\n-\t\tif (!burst && mt_safe)\n+\t\tif (!burst && internal_port)\n \t\t\treturn pipeline_queue_worker_single_stage_tx(arg);\n-\t\telse if (!burst && !mt_safe)\n+\t\telse if (!burst && !internal_port)\n \t\t\treturn pipeline_queue_worker_single_stage_fwd(arg);\n-\t\telse if (burst && mt_safe)\n+\t\telse if (burst && internal_port)\n \t\t\treturn pipeline_queue_worker_single_stage_burst_tx(arg);\n-\t\telse if (burst && !mt_safe)\n+\t\telse if (burst && !internal_port)\n \t\t\treturn pipeline_queue_worker_single_stage_burst_fwd(\n \t\t\t\t\targ);\n \t} else {\n-\t\tif (!burst && mt_safe)\n+\t\tif (!burst && internal_port)\n \t\t\treturn pipeline_queue_worker_multi_stage_tx(arg);\n-\t\telse if (!burst && !mt_safe)\n+\t\telse if (!burst && !internal_port)\n \t\t\treturn pipeline_queue_worker_multi_stage_fwd(arg);\n-\t\telse if (burst && mt_safe)\n+\t\telse if (burst && internal_port)\n \t\t\treturn pipeline_queue_worker_multi_stage_burst_tx(arg);\n-\t\telse if (burst && !mt_safe)\n+\t\telse if (burst && !internal_port)\n \t\t\treturn pipeline_queue_worker_multi_stage_burst_fwd(arg);\n \n \t}\n@@ -311,10 +312,6 @@ worker_wrapper(void *arg)\n static int\n pipeline_queue_launch_lcores(struct evt_test *test, struct evt_options *opt)\n {\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\n-\tif (t->mt_unsafe)\n-\t\trte_service_component_runstate_set(t->tx_service.service_id, 1);\n \treturn pipeline_launch_lcores(test, opt, worker_wrapper);\n }\n \n@@ -326,25 +323,21 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \tint nb_queues;\n \tint nb_stages = opt->nb_stages;\n \tuint8_t queue;\n-\tstruct rte_event_dev_info info;\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\tuint8_t tx_evqueue_id = 0;\n+\tuint8_t tx_evport_id = 0;\n+\tuint8_t tx_evqueue_id[RTE_MAX_ETHPORTS] = {0};\n \tuint8_t queue_arr[RTE_EVENT_MAX_QUEUES_PER_DEV];\n \tuint8_t nb_worker_queues = 0;\n+\tuint16_t prod = 0;\n+\tstruct rte_event_dev_info info;\n+\tstruct test_pipeline *t = evt_test_priv(test);\n \n \tnb_ports = evt_nr_active_lcores(opt->wlcores);\n \tnb_queues = rte_eth_dev_count_avail() * (nb_stages);\n \n-\t/* Extra port for Tx service. */\n-\tif (t->mt_unsafe) {\n-\t\ttx_evqueue_id = nb_queues;\n-\t\tnb_ports++;\n-\t\tnb_queues++;\n-\t} else\n-\t\tnb_queues += rte_eth_dev_count_avail();\n+\t/* Extra queue for Tx service. */\n+\tnb_queues += rte_eth_dev_count_avail();\n \n \trte_event_dev_info_get(opt->dev_id, &info);\n-\n \tconst struct rte_event_dev_config config = {\n \t\t\t.nb_event_queues = nb_queues,\n \t\t\t.nb_event_ports = nb_ports,\n@@ -370,24 +363,19 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \tfor (queue = 0; queue < nb_queues; queue++) {\n \t\tuint8_t slot;\n \n-\t\tif (!t->mt_unsafe) {\n-\t\t\tslot = queue % (nb_stages + 1);\n-\t\t\tq_conf.schedule_type = slot == nb_stages ?\n-\t\t\t\tRTE_SCHED_TYPE_ATOMIC :\n-\t\t\t\topt->sched_type_list[slot];\n-\t\t} else {\n-\t\t\tslot = queue % nb_stages;\n-\n-\t\t\tif (queue == tx_evqueue_id) {\n-\t\t\t\tq_conf.schedule_type = RTE_SCHED_TYPE_ATOMIC;\n+\t\tq_conf.event_queue_cfg = 0;\n+\t\tslot = queue % (nb_stages + 1);\n+\t\tif (slot == nb_stages) {\n+\t\t\tq_conf.schedule_type = RTE_SCHED_TYPE_ATOMIC;\n+\t\t\tif (!t->internal_port) {\n \t\t\t\tq_conf.event_queue_cfg =\n \t\t\t\t\tRTE_EVENT_QUEUE_CFG_SINGLE_LINK;\n-\t\t\t} else {\n-\t\t\t\tq_conf.schedule_type =\n-\t\t\t\t\topt->sched_type_list[slot];\n-\t\t\t\tqueue_arr[nb_worker_queues] = queue;\n-\t\t\t\tnb_worker_queues++;\n \t\t\t}\n+\t\t\ttx_evqueue_id[prod++] = queue;\n+\t\t} else {\n+\t\t\tq_conf.schedule_type = opt->sched_type_list[slot];\n+\t\t\tqueue_arr[nb_worker_queues] = queue;\n+\t\t\tnb_worker_queues++;\n \t\t}\n \n \t\tret = rte_event_queue_setup(opt->dev_id, queue, &q_conf);\n@@ -407,19 +395,11 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\t\t.new_event_threshold = info.max_num_events,\n \t};\n \n-\t/*\n-\t * If tx is multi thread safe then allow workers to do Tx else use Tx\n-\t * service to Tx packets.\n-\t */\n-\tif (t->mt_unsafe) {\n+\tif (!t->internal_port) {\n \t\tret = pipeline_event_port_setup(test, opt, queue_arr,\n \t\t\t\tnb_worker_queues, p_conf);\n \t\tif (ret)\n \t\t\treturn ret;\n-\n-\t\tret = pipeline_event_tx_service_setup(test, opt, tx_evqueue_id,\n-\t\t\t\tnb_ports - 1, p_conf);\n-\n \t} else\n \t\tret = pipeline_event_port_setup(test, opt, NULL, nb_queues,\n \t\t\t\tp_conf);\n@@ -431,7 +411,6 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t *\n \t * eth_dev_count = 2, nb_stages = 2.\n \t *\n-\t * Multi thread safe :\n \t *\tqueues = 6\n \t *\tstride = 3\n \t *\n@@ -439,21 +418,14 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t *\teth0 -> q0 -> q1 -> (q2->tx)\n \t *\teth1 -> q3 -> q4 -> (q5->tx)\n \t *\n-\t *\tq2, q5 configured as ATOMIC\n-\t *\n-\t * Multi thread unsafe :\n-\t *\tqueues = 5\n-\t *\tstride = 2\n+\t *\tq2, q5 configured as ATOMIC | SINGLE_LINK\n \t *\n-\t *\tevent queue pipelines:\n-\t *\teth0 -> q0 -> q1\n-\t *\t\t\t} (q4->tx) Tx service\n-\t *\teth1 -> q2 -> q3\n-\t *\n-\t *\tq4 configured as SINGLE_LINK|ATOMIC\n \t */\n-\tret = pipeline_event_rx_adapter_setup(opt,\n-\t\t\tt->mt_unsafe ? nb_stages : nb_stages + 1, p_conf);\n+\tret = pipeline_event_rx_adapter_setup(opt, nb_stages + 1, p_conf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = pipeline_event_tx_adapter_setup(opt, p_conf);\n \tif (ret)\n \t\treturn ret;\n \n@@ -467,12 +439,60 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\t}\n \t}\n \n+\t/* Connect the tx_evqueue_id to the Tx adapter port */\n+\tif (!t->internal_port) {\n+\t\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\t\tret = rte_event_eth_tx_adapter_event_port_get(prod,\n+\t\t\t\t\t&tx_evport_id);\n+\t\t\tif (ret) {\n+\t\t\t\tevt_err(\"Unable to get Tx adptr[%d] evprt[%d]\",\n+\t\t\t\t\t\tprod, tx_evport_id);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tif (rte_event_port_link(opt->dev_id, tx_evport_id,\n+\t\t\t\t\t\t&tx_evqueue_id[prod],\n+\t\t\t\t\t\tNULL, 1) != 1) {\n+\t\t\t\tevt_err(\"Unable to link Tx adptr[%d] evprt[%d]\",\n+\t\t\t\t\t\tprod, tx_evport_id);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\tret = rte_eth_dev_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Ethernet dev [%d] failed to start.\"\n+\t\t\t\t\t\" Using synthetic producer\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t}\n+\n \tret = rte_event_dev_start(opt->dev_id);\n \tif (ret) {\n \t\tevt_err(\"failed to start eventdev %d\", opt->dev_id);\n \t\treturn ret;\n \t}\n \n+\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\tret = rte_event_eth_rx_adapter_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Rx adapter[%d] start failed\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret = rte_event_eth_tx_adapter_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Tx adapter[%d] start failed\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tmemcpy(t->tx_evqueue_id, tx_evqueue_id, sizeof(uint8_t) *\n+\t\t\tRTE_MAX_ETHPORTS);\n+\n \treturn 0;\n }\n \n",
    "prefixes": [
        "2/2"
    ]
}