Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/43184/?format=api
{ "id": 43184, "url": "http://patches.dpdk.org/api/patches/43184/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180718123524.75449-1-ferruh.yigit@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180718123524.75449-1-ferruh.yigit@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180718123524.75449-1-ferruh.yigit@intel.com", "date": "2018-07-18T12:35:22", "name": "[1/3] net/ixgbe: remove redundant queue id checks", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b87a36ac603265d75edacc7510594298870cd94e", "submitter": { "id": 324, "url": "http://patches.dpdk.org/api/people/324/?format=api", "name": "Ferruh Yigit", "email": "ferruh.yigit@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180718123524.75449-1-ferruh.yigit@intel.com/mbox/", "series": [ { "id": 655, "url": "http://patches.dpdk.org/api/series/655/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=655", "date": "2018-07-18T12:35:22", "name": "[1/3] net/ixgbe: remove redundant queue id checks", "version": 1, "mbox": "http://patches.dpdk.org/series/655/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/43184/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/43184/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 04E651C01;\n\tWed, 18 Jul 2018 13:35:46 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id 28A7F160\n\tfor <dev@dpdk.org>; Wed, 18 Jul 2018 13:35:43 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t18 Jul 2018 04:35:41 -0700", "from silpixa00399752.ir.intel.com (HELO\n\tsilpixa00399752.ger.corp.intel.com) ([10.237.222.212])\n\tby FMSMGA003.fm.intel.com with ESMTP; 18 Jul 2018 04:35:40 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.51,370,1526367600\"; d=\"scan'208\";a=\"65575028\"", "From": "Ferruh Yigit <ferruh.yigit@intel.com>", "To": "Wenzhuo Lu <wenzhuo.lu@intel.com>,\n\tKonstantin Ananyev <konstantin.ananyev@intel.com>", "Cc": "dev@dpdk.org, Ferruh Yigit <ferruh.yigit@intel.com>,\n\tKeith Wiles <keith.wiles@intel.com>", "Date": "Wed, 18 Jul 2018 13:35:22 +0100", "Message-Id": "<20180718123524.75449-1-ferruh.yigit@intel.com>", "X-Mailer": "git-send-email 2.17.1", "Subject": "[dpdk-dev] [PATCH 1/3] net/ixgbe: remove redundant queue id checks", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "remove queue id checks from dev_ops\nixgbe_dev_[rx/tx]_queue_[start/stop]\n\nqueue id checks already done by ethdev APIs that are calling these\ndev_ops\n\nSigned-off-by: Ferruh Yigit <ferruh.yigit@intel.com>\n---\nCc: Keith Wiles <keith.wiles@intel.com>\n---\n drivers/net/ixgbe/ixgbe_rxtx.c | 139 +++++++++++++++------------------\n 1 file changed, 63 insertions(+), 76 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex 354181664..f82b74a9a 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -5176,34 +5176,30 @@ ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \tPMD_INIT_FUNC_TRACE();\n \thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n-\tif (rx_queue_id < dev->data->nb_rx_queues) {\n-\t\trxq = dev->data->rx_queues[rx_queue_id];\n-\n-\t\t/* Allocate buffers for descriptor rings */\n-\t\tif (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {\n-\t\t\tPMD_INIT_LOG(ERR, \"Could not alloc mbuf for queue:%d\",\n-\t\t\t\t rx_queue_id);\n-\t\t\treturn -1;\n-\t\t}\n-\t\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n-\t\trxdctl |= IXGBE_RXDCTL_ENABLE;\n-\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);\n+\trxq = dev->data->rx_queues[rx_queue_id];\n \n-\t\t/* Wait until RX Enable ready */\n-\t\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n-\t\tdo {\n-\t\t\trte_delay_ms(1);\n-\t\t\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n-\t\t} while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));\n-\t\tif (!poll_ms)\n-\t\t\tPMD_INIT_LOG(ERR, \"Could not enable Rx Queue %d\",\n-\t\t\t\t rx_queue_id);\n-\t\trte_wmb();\n-\t\tIXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);\n-\t\tIXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);\n-\t\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n-\t} else\n+\t/* Allocate buffers for descriptor rings */\n+\tif (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Could not alloc mbuf for queue:%d\",\n+\t\t\t rx_queue_id);\n \t\treturn -1;\n+\t}\n+\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n+\trxdctl |= IXGBE_RXDCTL_ENABLE;\n+\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);\n+\n+\t/* Wait until RX Enable ready */\n+\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n+\tdo {\n+\t\trte_delay_ms(1);\n+\t\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n+\t} while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));\n+\tif (!poll_ms)\n+\t\tPMD_INIT_LOG(ERR, \"Could not enable Rx Queue %d\", rx_queue_id);\n+\trte_wmb();\n+\tIXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);\n+\tIXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);\n+\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n \n \treturn 0;\n }\n@@ -5224,30 +5220,26 @@ ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \tPMD_INIT_FUNC_TRACE();\n \thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n-\tif (rx_queue_id < dev->data->nb_rx_queues) {\n-\t\trxq = dev->data->rx_queues[rx_queue_id];\n+\trxq = dev->data->rx_queues[rx_queue_id];\n+\n+\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n+\trxdctl &= ~IXGBE_RXDCTL_ENABLE;\n+\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);\n \n+\t/* Wait until RX Enable bit clear */\n+\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n+\tdo {\n+\t\trte_delay_ms(1);\n \t\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n-\t\trxdctl &= ~IXGBE_RXDCTL_ENABLE;\n-\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);\n+\t} while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE));\n+\tif (!poll_ms)\n+\t\tPMD_INIT_LOG(ERR, \"Could not disable Rx Queue %d\", rx_queue_id);\n \n-\t\t/* Wait until RX Enable bit clear */\n-\t\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n-\t\tdo {\n-\t\t\trte_delay_ms(1);\n-\t\t\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n-\t\t} while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE));\n-\t\tif (!poll_ms)\n-\t\t\tPMD_INIT_LOG(ERR, \"Could not disable Rx Queue %d\",\n-\t\t\t\t rx_queue_id);\n-\n-\t\trte_delay_us(RTE_IXGBE_WAIT_100_US);\n+\trte_delay_us(RTE_IXGBE_WAIT_100_US);\n \n-\t\tixgbe_rx_queue_release_mbufs(rxq);\n-\t\tixgbe_reset_rx_queue(adapter, rxq);\n-\t\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n-\t} else\n-\t\treturn -1;\n+\tixgbe_rx_queue_release_mbufs(rxq);\n+\tixgbe_reset_rx_queue(adapter, rxq);\n+\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n \n \treturn 0;\n }\n@@ -5267,30 +5259,27 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \tPMD_INIT_FUNC_TRACE();\n \thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n-\tif (tx_queue_id < dev->data->nb_tx_queues) {\n-\t\ttxq = dev->data->tx_queues[tx_queue_id];\n-\t\ttxdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));\n-\t\ttxdctl |= IXGBE_TXDCTL_ENABLE;\n-\t\tIXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\ttxdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));\n+\ttxdctl |= IXGBE_TXDCTL_ENABLE;\n+\tIXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);\n \n-\t\t/* Wait until TX Enable ready */\n-\t\tif (hw->mac.type == ixgbe_mac_82599EB) {\n-\t\t\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n-\t\t\tdo {\n-\t\t\t\trte_delay_ms(1);\n-\t\t\t\ttxdctl = IXGBE_READ_REG(hw,\n-\t\t\t\t\tIXGBE_TXDCTL(txq->reg_idx));\n-\t\t\t} while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));\n-\t\t\tif (!poll_ms)\n-\t\t\t\tPMD_INIT_LOG(ERR, \"Could not enable \"\n-\t\t\t\t\t \"Tx Queue %d\", tx_queue_id);\n-\t\t}\n-\t\trte_wmb();\n-\t\tIXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);\n-\t\tIXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);\n-\t\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n-\t} else\n-\t\treturn -1;\n+\t/* Wait until TX Enable ready */\n+\tif (hw->mac.type == ixgbe_mac_82599EB) {\n+\t\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n+\t\tdo {\n+\t\t\trte_delay_ms(1);\n+\t\t\ttxdctl = IXGBE_READ_REG(hw,\n+\t\t\t\tIXGBE_TXDCTL(txq->reg_idx));\n+\t\t} while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));\n+\t\tif (!poll_ms)\n+\t\t\tPMD_INIT_LOG(ERR, \"Could not enable Tx Queue %d\",\n+\t\t\t\ttx_queue_id);\n+\t}\n+\trte_wmb();\n+\tIXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);\n+\tIXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);\n+\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n \n \treturn 0;\n }\n@@ -5310,9 +5299,6 @@ ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \tPMD_INIT_FUNC_TRACE();\n \thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n-\tif (tx_queue_id >= dev->data->nb_tx_queues)\n-\t\treturn -1;\n-\n \ttxq = dev->data->tx_queues[tx_queue_id];\n \n \t/* Wait until TX queue is empty */\n@@ -5326,8 +5312,9 @@ ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \t\t\t\t\t IXGBE_TDT(txq->reg_idx));\n \t\t} while (--poll_ms && (txtdh != txtdt));\n \t\tif (!poll_ms)\n-\t\t\tPMD_INIT_LOG(ERR, \"Tx Queue %d is not empty \"\n-\t\t\t\t \"when stopping.\", tx_queue_id);\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t\"Tx Queue %d is not empty when stopping.\",\n+\t\t\t\ttx_queue_id);\n \t}\n \n \ttxdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));\n@@ -5343,8 +5330,8 @@ ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \t\t\t\t\t\tIXGBE_TXDCTL(txq->reg_idx));\n \t\t} while (--poll_ms && (txdctl & IXGBE_TXDCTL_ENABLE));\n \t\tif (!poll_ms)\n-\t\t\tPMD_INIT_LOG(ERR, \"Could not disable \"\n-\t\t\t\t \"Tx Queue %d\", tx_queue_id);\n+\t\t\tPMD_INIT_LOG(ERR, \"Could not disable Tx Queue %d\",\n+\t\t\t\ttx_queue_id);\n \t}\n \n \tif (txq->ops != NULL) {\n", "prefixes": [ "1/3" ] }