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GET /api/patches/41478/?format=api
{ "id": 41478, "url": "http://patches.dpdk.org/api/patches/41478/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180625142057.6296-1-olivier.matz@6wind.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180625142057.6296-1-olivier.matz@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180625142057.6296-1-olivier.matz@6wind.com", "date": "2018-06-25T14:20:57", "name": "[RFC] net/ixgbe: fix Tx descriptor status api", "commit_ref": null, "pull_url": null, "state": "rfc", "archived": true, "hash": "a5e788ff4bb1005089c73fcd51ab8523d971239e", "submitter": { "id": 8, "url": "http://patches.dpdk.org/api/people/8/?format=api", "name": "Olivier Matz", "email": "olivier.matz@6wind.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180625142057.6296-1-olivier.matz@6wind.com/mbox/", "series": [ { "id": 224, "url": "http://patches.dpdk.org/api/series/224/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=224", "date": "2018-06-25T14:20:57", "name": "[RFC] net/ixgbe: fix Tx descriptor status api", "version": 1, "mbox": "http://patches.dpdk.org/series/224/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/41478/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/41478/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 22FE844CF;\n\tMon, 25 Jun 2018 16:21:19 +0200 (CEST)", "from proxy.6wind.com (host.76.145.23.62.rev.coltfrance.com\n\t[62.23.145.76]) by dpdk.org (Postfix) with ESMTP id 1F7BF44BE\n\tfor <dev@dpdk.org>; Mon, 25 Jun 2018 16:21:17 +0200 (CEST)", "from glumotte.dev.6wind.com. (unknown [10.16.0.195])\n\tby proxy.6wind.com (Postfix) with ESMTP id 491E4194915;\n\tMon, 25 Jun 2018 16:16:13 +0200 (CEST)" ], "From": "Olivier Matz <olivier.matz@6wind.com>", "To": "Zhao1@6wind.com, Wei <wei.zhao1@intel.com>, Zhang@6wind.com,\n\tQi Z <qi.z.zhang@intel.com>", "Cc": "dev@dpdk.org, Lu@6wind.com, Wenzhuo <wenzhuo.lu@intel.com>", "Date": "Mon, 25 Jun 2018 16:20:57 +0200", "Message-Id": "<20180625142057.6296-1-olivier.matz@6wind.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<A2573D2ACFCADC41BB3BE09C6DE313CA07DFF08A@PGSMSX103.gar.corp.intel.com>", "References": "<A2573D2ACFCADC41BB3BE09C6DE313CA07DFF08A@PGSMSX103.gar.corp.intel.com>", "Subject": "[dpdk-dev] [RFC] net/ixgbe: fix Tx descriptor status api", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The Tx descriptor status api was not behaving as expected. This API is\nused to inspect the content of the descriptors in the Tx ring to\ndetermine the length of the Tx queue.\n\nSince the software advances the tail pointer and the hardware advances\nthe head pointer, the Tx queue is located before txq->tx_tail in the\nring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20)\nshould inspect the 20th descriptor before the tail, not after.\n\nAs before, we still need to take care about only checking descriptors\nthat have the RS bit.\n\nAdditionally, we can avoid an access to the ring if offset is greater or\nequal to nb_tx_desc - nb_tx_free.\n\nFixes: a2919e13d95e (\"net/ixgbe: implement descriptor status API\")\nSigned-off-by: Olivier Matz <olivier.matz@6wind.com>\nSigned-off-by: Didier Pallard <didier.pallard@6wind.com>\n---\n\nHi Wei, Hi Qi,\n\nWe also recently found some issues in Tx descriptor status API for ixgbe,\ni40, e1000, igb. I'm preparing a clean patchset for all of them.\n\nHere is already the patch for ixgbe, please let me know what you think.\n\nThe API comment of rte_eth_tx_descriptor_status() is incorrect and should\nbe fixed too. The reference descriptor (when offset = 0) is not where the\nnext packet will be sent, but where the latest packet has been enqueued.\n\nRegards,\nOlivier\n\n\n\n drivers/net/ixgbe/ixgbe_rxtx.c | 45 +++++++++++++++++++++++++++++++-----------\n drivers/net/ixgbe/ixgbe_rxtx.h | 1 +\n 2 files changed, 34 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex 3e13d26ae..384587cc6 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -2606,10 +2606,15 @@ ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,\n \t hw->mac.type == ixgbe_mac_X540_vf ||\n \t hw->mac.type == ixgbe_mac_X550_vf ||\n \t hw->mac.type == ixgbe_mac_X550EM_x_vf ||\n-\t hw->mac.type == ixgbe_mac_X550EM_a_vf)\n+\t hw->mac.type == ixgbe_mac_X550EM_a_vf) {\n \t\ttxq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));\n-\telse\n+\t\ttxq->tdh_reg_addr = IXGBE_PCI_REG_ADDR(hw,\n+\t\t\t\tIXGBE_VFTDH(queue_idx));\n+\t} else {\n \t\ttxq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));\n+\t\ttxq->tdh_reg_addr = IXGBE_PCI_REG_ADDR(hw,\n+\t\t\t\tIXGBE_TDH(txq->reg_idx));\n+\t}\n \n \ttxq->tx_ring_phys_addr = tz->iova;\n \ttxq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;\n@@ -3140,22 +3145,38 @@ ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)\n {\n \tstruct ixgbe_tx_queue *txq = tx_queue;\n \tvolatile uint32_t *status;\n-\tuint32_t desc;\n+\tint32_t desc, dd;\n \n \tif (unlikely(offset >= txq->nb_tx_desc))\n \t\treturn -EINVAL;\n+\tif (offset >= txq->nb_tx_desc - txq->nb_tx_free)\n+\t\treturn RTE_ETH_TX_DESC_DONE;\n+\n+\tdesc = txq->tx_tail - offset - 1;\n+\tif (desc < 0)\n+\t\tdesc += txq->nb_tx_desc;\n \n-\tdesc = txq->tx_tail + offset;\n-\t/* go to next desc that has the RS bit */\n-\tdesc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *\n-\t\ttxq->tx_rs_thresh;\n-\tif (desc >= txq->nb_tx_desc) {\n-\t\tdesc -= txq->nb_tx_desc;\n-\t\tif (desc >= txq->nb_tx_desc)\n-\t\t\tdesc -= txq->nb_tx_desc;\n+\t/* offset is too small, no other way than reading PCI reg */\n+\tif (unlikely(offset < txq->tx_rs_thresh)) {\n+\t\tint16_t tx_head, queue_size;\n+\t\ttx_head = ixgbe_read_addr(txq->tdh_reg_addr);\n+\t\tqueue_size = txq->tx_tail - tx_head;\n+\t\tif (queue_size < 0)\n+\t\t\tqueue_size += txq->nb_tx_desc;\n+\t\treturn queue_size > offset ? RTE_ETH_TX_DESC_FULL :\n+\t\t\tRTE_ETH_TX_DESC_DONE;\n \t}\n \n-\tstatus = &txq->tx_ring[desc].wb.status;\n+\t/* index of the dd bit to look at */\n+\tdd = (desc / txq->tx_rs_thresh + 1) * txq->tx_rs_thresh - 1;\n+\n+\t/* In full featured mode, RS bit is only set in the last descriptor */\n+\t/* of a multisegments packet */\n+\tif (!((txq->offloads == 0) &&\n+\t (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)))\n+\t\tdd = txq->sw_ring[dd].last_id;\n+\n+\tstatus = &txq->tx_ring[dd].wb.status;\n \tif (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))\n \t\treturn RTE_ETH_TX_DESC_DONE;\n \ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxtx.h\nindex 39378f754..384f6324d 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.h\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.h\n@@ -201,6 +201,7 @@ struct ixgbe_tx_queue {\n \t\tstruct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for vector PMD */\n \t};\n \tvolatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */\n+\tvolatile uint32_t *tdh_reg_addr; /**< Address of TDH register. */\n \tuint16_t nb_tx_desc; /**< number of TX descriptors. */\n \tuint16_t tx_tail; /**< current value of TDT reg. */\n \t/**< Start freeing TX buffers if there are less free descriptors than\n", "prefixes": [ "RFC" ] }