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GET /api/patches/40704/?format=api
{ "id": 40704, "url": "http://patches.dpdk.org/api/patches/40704/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1528339208-89160-3-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1528339208-89160-3-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1528339208-89160-3-git-send-email-beilei.xing@intel.com", "date": "2018-06-07T02:40:08", "name": "[dpdk-dev,2/2] net/i40e: remove summarized global register change info", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9b8c841025d67623cc09848562904209d4392ff4", "submitter": { "id": 410, "url": "http://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1528339208-89160-3-git-send-email-beilei.xing@intel.com/mbox/", "series": [ { "id": 22, "url": "http://patches.dpdk.org/api/series/22/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22", "date": "2018-06-07T02:40:06", "name": "net/i40e: print real global changes", "version": 1, "mbox": "http://patches.dpdk.org/series/22/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/40704/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/40704/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B0A401B3D5;\n\tThu, 7 Jun 2018 04:40:29 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby dpdk.org (Postfix) with ESMTP id 4B50B1B2A7\n\tfor <dev@dpdk.org>; Thu, 7 Jun 2018 04:40:24 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t06 Jun 2018 19:40:24 -0700", "from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52])\n\tby fmsmga006.fm.intel.com with ESMTP; 06 Jun 2018 19:40:23 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.49,485,1520924400\"; d=\"scan'208\";a=\"235341820\"", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "qi.z.zhang@intel.com", "Cc": "dev@dpdk.org", "Date": "Thu, 7 Jun 2018 10:40:08 +0800", "Message-Id": "<1528339208-89160-3-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1528339208-89160-1-git-send-email-beilei.xing@intel.com>", "References": "<1528339208-89160-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH 2/2] net/i40e: remove summarized global register\n\tchange info", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The summarized global register change info will be logged\nno matter if there's real global register change. Since\nonly real changes are logged now, there's no need to\nsummarize global register change info, otherwise will\ncause misunderstanding.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 43 ++++++++++-------------------------------\n drivers/net/i40e/i40e_ethdev.h | 43 -----------------------------------------\n drivers/net/i40e/i40e_fdir.c | 1 -\n drivers/net/i40e/i40e_flow.c | 1 -\n drivers/net/i40e/rte_pmd_i40e.c | 3 ---\n 5 files changed, 10 insertions(+), 81 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex e81b47e..29eeb92 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -734,7 +734,6 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)\n \t */\n \tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);\n \tI40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);\n-\ti40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);\n }\n \n static inline void i40e_config_automask(struct i40e_pf *pf)\n@@ -1306,7 +1305,6 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)\n \t\tPMD_INIT_LOG(DEBUG,\n \t\t\t \"Global register 0x%08x is changed with 0x28\",\n \t\t\t I40E_GLQF_L3_MAP(40));\n-\t\ti40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);\n \t}\n \n \t/* Need the special FW version to support floating VEB */\n@@ -1593,7 +1591,6 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)\n \tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);\n \tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);\n \tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);\n-\ti40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);\n }\n \n static int\n@@ -3508,8 +3505,6 @@ i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,\n \t\t \"Global register 0x%08x is changed with value 0x%08x\",\n \t\t I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);\n \n-\ti40e_global_cfg_warning(I40E_WARNING_TPID);\n-\n \treturn 0;\n }\n \n@@ -3804,7 +3799,6 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n \t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,\n \t\t\t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t\t\t << I40E_KILOSHIFT);\n-\t\ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n \t} else {\n \t\tPMD_DRV_LOG(ERR,\n \t\t\t \"Water marker configuration is not supported.\");\n@@ -7617,14 +7611,13 @@ i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)\n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n \tif (!status && (filter_replace.old_filter_type !=\n-\t\t\tfilter_replace.new_filter_type)) {\n-\t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n+\t\t\tfilter_replace.new_filter_type))\n \t\tPMD_DRV_LOG(WARNING, \"i40e device %s changed cloud l1 type.\"\n \t\t\t \" original: 0x%x, new: 0x%x\",\n \t\t\t dev->device->name,\n \t\t\t filter_replace.old_filter_type,\n \t\t\t filter_replace.new_filter_type);\n-\t}\n+\n \treturn status;\n }\n \n@@ -7693,14 +7686,13 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)\n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n \tif (!status && (filter_replace.old_filter_type !=\n-\t\t\tfilter_replace.new_filter_type)) {\n-\t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n+\t\t\tfilter_replace.new_filter_type))\n \t\tPMD_DRV_LOG(WARNING, \"i40e device %s changed cloud filter type.\"\n \t\t\t \" original: 0x%x, new: 0x%x\",\n \t\t\t dev->device->name,\n \t\t\t filter_replace.old_filter_type,\n \t\t\t filter_replace.new_filter_type);\n-\t}\n+\n \treturn status;\n }\n \n@@ -7782,14 +7774,13 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf)\n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n \tif (!status && (filter_replace.old_filter_type !=\n-\t\t\tfilter_replace.new_filter_type)) {\n-\t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n+\t\t\tfilter_replace.new_filter_type))\n \t\tPMD_DRV_LOG(WARNING, \"i40e device %s changed cloud l1 type.\"\n \t\t\t \" original: 0x%x, new: 0x%x\",\n \t\t\t dev->device->name,\n \t\t\t filter_replace.old_filter_type,\n \t\t\t filter_replace.new_filter_type);\n-\t}\n+\n \treturn status;\n }\n \n@@ -7856,14 +7847,13 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)\n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n \tif (!status && (filter_replace.old_filter_type !=\n-\t\t\tfilter_replace.new_filter_type)) {\n-\t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n+\t\t\tfilter_replace.new_filter_type))\n \t\tPMD_DRV_LOG(WARNING, \"i40e device %s changed cloud filter type.\"\n \t\t\t \" original: 0x%x, new: 0x%x\",\n \t\t\t dev->device->name,\n \t\t\t filter_replace.old_filter_type,\n \t\t\t filter_replace.new_filter_type);\n-\t}\n+\n \treturn status;\n }\n \n@@ -8423,7 +8413,6 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)\n \t\tPMD_DRV_LOG(DEBUG, \"Global register 0x%08x is changed \"\n \t\t\t \"with value 0x%08x\",\n \t\t\t I40E_GL_PRS_FVBM(2), reg);\n-\t\ti40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);\n \t} else {\n \t\tret = 0;\n \t}\n@@ -8689,7 +8678,6 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t\t\t\t\t\t I40E_GLQF_HSYM(j),\n \t\t\t\t\t\t\t reg);\n \t\t\t}\n-\t\t\ti40e_global_cfg_warning(I40E_WARNING_HSYM);\n \t\t}\n \t}\n \n@@ -8715,7 +8703,6 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\tgoto out;\n \n \ti40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);\n-\ti40e_global_cfg_warning(I40E_WARNING_QF_CTL);\n \n out:\n \tI40E_WRITE_FLUSH(hw);\n@@ -9392,12 +9379,6 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\t\tpf->hash_input_set[pctype] = input_set;\n \t\tpf->fdir.input_set[pctype] = input_set;\n \t}\n-\n-\tif (!pf->support_multi_driver) {\n-\t\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n-\t\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n-\t\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n-\t}\n }\n \n int\n@@ -9463,7 +9444,6 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,\n \ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n \t\t\t\t (uint32_t)((inset_reg >>\n \t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n \n \tfor (i = 0; i < num; i++)\n \t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n@@ -9472,7 +9452,6 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,\n \tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n \t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n \t\t\t\t\t 0);\n-\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n \tI40E_WRITE_FLUSH(hw);\n \n \tpf->hash_input_set[pctype] = input_set;\n@@ -9553,7 +9532,6 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n \t\t\t\t\t\t 0);\n-\t\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n \t} else {\n \t\tPMD_DRV_LOG(ERR, \"FDIR bit mask is not supported.\");\n \t}\n@@ -12314,14 +12292,13 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf)\n \tret = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t&filter_replace_buf);\n \tif (!ret && (filter_replace.old_filter_type !=\n-\t\t filter_replace.new_filter_type)) {\n-\t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n+\t\t filter_replace.new_filter_type))\n \t\tPMD_DRV_LOG(WARNING, \"i40e device %s changed cloud filter type.\"\n \t\t\t \" original: 0x%x, new: 0x%x\",\n \t\t\t dev->device->name,\n \t\t\t filter_replace.old_filter_type,\n \t\t\t filter_replace.new_filter_type);\n-\t}\n+\n \treturn ret;\n }\n \ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 0bf3330..12f2f75 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -1133,22 +1133,6 @@ struct i40e_valid_pattern {\n \tparse_filter_t parse_filter;\n };\n \n-enum I40E_WARNING_IDX {\n-\tI40E_WARNING_DIS_FLX_PLD,\n-\tI40E_WARNING_ENA_FLX_PLD,\n-\tI40E_WARNING_QINQ_PARSER,\n-\tI40E_WARNING_QINQ_CLOUD_FILTER,\n-\tI40E_WARNING_TPID,\n-\tI40E_WARNING_FLOW_CTL,\n-\tI40E_WARNING_GRE_KEY_LEN,\n-\tI40E_WARNING_QF_CTL,\n-\tI40E_WARNING_HASH_INSET,\n-\tI40E_WARNING_HSYM,\n-\tI40E_WARNING_HASH_MSK,\n-\tI40E_WARNING_FD_MSK,\n-\tI40E_WARNING_RPL_CLD_FILTER,\n-};\n-\n int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);\n int i40e_vsi_release(struct i40e_vsi *vsi);\n struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,\n@@ -1370,33 +1354,6 @@ i40e_calc_itr_interval(int16_t interval, bool is_pf, bool is_multi_drv)\n \treturn interval / 2;\n }\n \n-static inline void\n-i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)\n-{\n-\tconst char *warning;\n-\tstatic const char *const warning_list[] = {\n-\t\t[I40E_WARNING_DIS_FLX_PLD] = \"disable FDIR flexible payload\",\n-\t\t[I40E_WARNING_ENA_FLX_PLD] = \"enable FDIR flexible payload\",\n-\t\t[I40E_WARNING_QINQ_PARSER] = \"support QinQ parser\",\n-\t\t[I40E_WARNING_QINQ_CLOUD_FILTER] = \"support QinQ cloud filter\",\n-\t\t[I40E_WARNING_TPID] = \"support TPID configuration\",\n-\t\t[I40E_WARNING_FLOW_CTL] = \"configure water marker\",\n-\t\t[I40E_WARNING_GRE_KEY_LEN] = \"support GRE key length setting\",\n-\t\t[I40E_WARNING_QF_CTL] = \"support hash function setting\",\n-\t\t[I40E_WARNING_HASH_INSET] = \"configure hash input set\",\n-\t\t[I40E_WARNING_HSYM] = \"set symmetric hash\",\n-\t\t[I40E_WARNING_HASH_MSK] = \"configure hash mask\",\n-\t\t[I40E_WARNING_FD_MSK] = \"configure fdir mask\",\n-\t\t[I40E_WARNING_RPL_CLD_FILTER] = \"replace cloud filter\",\n-\t};\n-\n-\twarning = warning_list[idx];\n-\n-\tRTE_LOG(WARNING, PMD,\n-\t\t\"Global register is changed during %s\\n\",\n-\t\twarning);\n-}\n-\n #define I40E_VALID_FLOW(flow_type) \\\n \t((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \\\n \t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \\\ndiff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c\nindex a4a61d1..d41601a 100644\n--- a/drivers/net/i40e/i40e_fdir.c\n+++ b/drivers/net/i40e/i40e_fdir.c\n@@ -526,7 +526,6 @@ i40e_set_flx_pld_cfg(struct i40e_pf *pf,\n \t\t\t (num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |\n \t\t\t (layer_idx * I40E_MAX_FLXPLD_FIED);\n \t\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);\n-\t\ti40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);\n \t}\n \n \tfor (i = 0; i < num; i++) {\ndiff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c\nindex 89de6a5..c67b264 100644\n--- a/drivers/net/i40e/i40e_flow.c\n+++ b/drivers/net/i40e/i40e_flow.c\n@@ -2263,7 +2263,6 @@ i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,\n \t\t\t (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |\n \t\t\t (layer_idx * I40E_MAX_FLXPLD_FIED);\n \t\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);\n-\t\ti40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);\n \t}\n \n \t/* Set flex pit */\ndiff --git a/drivers/net/i40e/rte_pmd_i40e.c b/drivers/net/i40e/rte_pmd_i40e.c\nindex 612eb6d..271bd17 100644\n--- a/drivers/net/i40e/rte_pmd_i40e.c\n+++ b/drivers/net/i40e/rte_pmd_i40e.c\n@@ -3170,8 +3170,6 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype,\n \t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n \t\t\t\t\t\t mask_reg[i]);\n-\t\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n-\t\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n \t\tbreak;\n \tcase INSET_FDIR:\n \t\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),\n@@ -3183,7 +3181,6 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype,\n \t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n \t\t\t\t\t\t mask_reg[i]);\n-\t\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n \t\tbreak;\n \tcase INSET_FDIR_FLX:\n \t\ti40e_check_write_reg(hw, I40E_PRTQF_FD_FLXINSET(pctype),\n", "prefixes": [ "dpdk-dev", "2/2" ] }