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{
    "id": 35306,
    "url": "http://patches.dpdk.org/api/patches/35306/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-4-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1519112078-20113-4-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1519112078-20113-4-git-send-email-arybchenko@solarflare.com",
    "date": "2018-02-20T07:33:21",
    "name": "[dpdk-dev,03/80] net/sfc/base: update autogenerated headers from firmwaresrc",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "8f33d8a565bfde87ddb5997772b604eb875e92b1",
    "submitter": {
        "id": 607,
        "url": "http://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-4-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/35306/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/35306/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 274FF1B040;\n\tTue, 20 Feb 2018 16:04:39 +0100 (CET)",
            "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id D064C1B306\n\tfor <dev@dpdk.org>; Tue, 20 Feb 2018 08:35:42 +0100 (CET)",
            "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\tB7B3DB00053 for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:37 +0000 (UTC)",
            "from sfocexch01r.SolarFlarecom.com (10.20.40.34) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 19 Feb 2018 23:35:33 -0800",
            "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tsfocexch01r.SolarFlarecom.com (10.20.40.34) with Microsoft SMTP\n\tServer (TLS) id 15.0.1044.25; Mon, 19 Feb 2018 23:35:13 -0800",
            "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 19 Feb 2018 23:35:13 -0800",
            "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZCss024847 for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:12 GMT",
            "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZBtF020529 for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:12 GMT"
        ],
        "X-Virus-Scanned": "Proofpoint Essentials engine",
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<dev@dpdk.org>",
        "Date": "Tue, 20 Feb 2018 07:33:21 +0000",
        "Message-ID": "<1519112078-20113-4-git-send-email-arybchenko@solarflare.com>",
        "X-Mailer": "git-send-email 1.8.2.3",
        "In-Reply-To": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>",
        "References": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-MDID": "1519112138-G+FPTVL9d4RN",
        "X-Mailman-Approved-At": "Tue, 20 Feb 2018 16:04:37 +0100",
        "Subject": "[dpdk-dev] [PATCH 03/80] net/sfc/base: update autogenerated headers\n\tfrom firmwaresrc",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Pick up Medford2 interfaces.\n\nSplit AOE operations out into own header.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_tlv_layout.h   |   85 +-\n drivers/net/sfc/base/efx_lic.c           |    3 +\n drivers/net/sfc/base/efx_regs_mcdi.h     | 5736 +++++++++++++++++-------------\n drivers/net/sfc/base/efx_regs_mcdi_aoe.h | 2913 +++++++++++++++\n 4 files changed, 6196 insertions(+), 2541 deletions(-)\n create mode 100644 drivers/net/sfc/base/efx_regs_mcdi_aoe.h",
    "diff": "diff --git a/drivers/net/sfc/base/ef10_tlv_layout.h b/drivers/net/sfc/base/ef10_tlv_layout.h\nindex 2473a66..b649008 100644\n--- a/drivers/net/sfc/base/ef10_tlv_layout.h\n+++ b/drivers/net/sfc/base/ef10_tlv_layout.h\n@@ -525,6 +525,17 @@ struct tlv_pcie_config_r2 {\n  * number of externally visible ports (and, hence, PF to port mapping), so must\n  * be done at boot time.\n  *\n+ * Port mode naming convention is\n+ *\n+ * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width]\n+ *\n+ * Port lane width determines the capabilities (speeds) of the ports, subject\n+ * to architecture capabilities (e.g. 25G support) and switch bandwidth\n+ * constraints:\n+ *  - single lane ports can do 25G/10G/1G\n+ *  - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)\n+ *  - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)\n+\n  * This tag supercedes tlv_global_port_config.\n  */\n \n@@ -535,18 +546,68 @@ struct tlv_global_port_mode {\n   uint32_t length;\n   uint32_t port_mode;\n #define TLV_PORT_MODE_DEFAULT           (0xffffffff) /* Default for given platform */\n-#define TLV_PORT_MODE_10G                        (0) /* 10G, single SFP/10G-KR */\n-#define TLV_PORT_MODE_40G                        (1) /* 40G, single QSFP/40G-KR */\n-#define TLV_PORT_MODE_10G_10G                    (2) /* 2x10G, dual SFP/10G-KR or single QSFP */\n-#define TLV_PORT_MODE_40G_40G                    (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */\n-#define TLV_PORT_MODE_10G_10G_10G_10G            (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport) */\n-#define TLV_PORT_MODE_10G_10G_10G_10G_Q1         (4) /* 4x10G, single QSFP, cage 0 (Medford) */\n-#define TLV_PORT_MODE_10G_10G_10G_10G_Q          (5) /* 4x10G, single QSFP, cage 0 (Medford) OBSOLETE DO NOT USE */\n-#define TLV_PORT_MODE_40G_10G_10G                (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */\n-#define TLV_PORT_MODE_10G_10G_40G                (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */\n-#define TLV_PORT_MODE_10G_10G_10G_10G_Q2         (8) /* 4x10G, single QSFP, cage 1 (Medford) */\n-#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2      (9) /* 2x10G + 2x10G, dual QSFP (Medford) */\n-#define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2\n+#define TLV_PORT_MODE_1x1_NA                     (0) /* Single 10G/25G on mdi0 */\n+#define TLV_PORT_MODE_1x4_NA                     (1) /* Single 100G/40G on mdi0 */\n+#define TLV_PORT_MODE_NA_1x4                     (22) /* Single 100G/40G on mdi1 */\n+#define TLV_PORT_MODE_1x2_NA                     (10) /* Single 50G on mdi0 */\n+#define TLV_PORT_MODE_NA_1x2                     (11) /* Single 50G on mdi1 */\n+#define TLV_PORT_MODE_1x1_1x1                    (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */\n+#define TLV_PORT_MODE_1x4_1x4                    (3) /* Single 40G on mdi0, single 40G on mdi1 */\n+#define TLV_PORT_MODE_2x1_2x1                    (4) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 - WARNING: bug3720: On Newport only, this is actually Quad 10G on mdi0 */\n+#define TLV_PORT_MODE_4x1_NA                     (5) /* Quad 10G/25G on mdi0 */\n+#define TLV_PORT_MODE_NA_4x1                     (8) /* Quad 10G/25G on mdi1 */\n+#define TLV_PORT_MODE_1x4_2x1                    (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */\n+#define TLV_PORT_MODE_2x1_1x4                    (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */\n+#define TLV_PORT_MODE_1x2_1x2                    (12) /* Single 50G on mdi0, single 50G on mdi1 */\n+#define TLV_PORT_MODE_2x2_NA                     (13) /* Dual 50G on mdi0 */\n+#define TLV_PORT_MODE_NA_2x2                     (14) /* Dual 50G on mdi1 */\n+#define TLV_PORT_MODE_1x4_1x2                    (15) /* Single 40G on mdi0, single 50G on mdi1 */\n+#define TLV_PORT_MODE_1x2_1x4                    (16) /* Single 50G on mdi0, single 40G on mdi1 */\n+#define TLV_PORT_MODE_1x2_2x1                    (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */\n+#define TLV_PORT_MODE_2x1_1x2                    (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */\n+#define TLV_PORT_MODE_2x1_2x1_LL                 (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */\n+#define TLV_PORT_MODE_4x1_NA_LL                  (20) /* Quad 10G/25G on mdi0, low-latency PCS */\n+#define TLV_PORT_MODE_NA_4x1_LL                  (21) /* Quad 10G/25G on mdi1, low-latency PCS */\n+#define TLV_PORT_MODE_1x1_NA_LL                  (23) /* Single 10G/25G on mdi0, low-latency PCS */\n+#define TLV_PORT_MODE_1x1_1x1_LL                 (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */\n+#define TLV_PORT_MODE_BUG63720_DO_NOT_USE        (9) /* bug63720: Do not use */\n+#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL\n+\n+/* Deprecated aliases */\n+#define TLV_PORT_MODE_10G                        TLV_PORT_MODE_1x1_NA\n+#define TLV_PORT_MODE_40G                        TLV_PORT_MODE_1x4_NA\n+#define TLV_PORT_MODE_10G_10G                    TLV_PORT_MODE_1x1_1x1\n+#define TLV_PORT_MODE_40G_40G                    TLV_PORT_MODE_1x4_1x4\n+#define TLV_PORT_MODE_10G_10G_10G_10G            TLV_PORT_MODE_2x1_2x1\n+#define TLV_PORT_MODE_10G_10G_10G_10G_Q1         TLV_PORT_MODE_2x1_2x1 /* bug63720: Do not use */\n+#define TLV_PORT_MODE_10G_10G_10G_10G_Q          TLV_PORT_MODE_4x1_NA\n+#define TLV_PORT_MODE_40G_10G_10G                TLV_PORT_MODE_1x4_2x1\n+#define TLV_PORT_MODE_10G_10G_40G                TLV_PORT_MODE_2x1_1x4\n+#define TLV_PORT_MODE_10G_10G_10G_10G_Q2         TLV_PORT_MODE_NA_4x1\n+#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2      TLV_PORT_MODE_BUG63720_DO_NOT_USE /* bug63720: Do not use */\n+#define TLV_PORT_MODE_25G                        TLV_PORT_MODE_1x1_NA     /* Single 25G on mdi0 */\n+#define TLV_PORT_MODE_100G_Q1                    TLV_PORT_MODE_1x4_NA     /* Single 100G on mdi0 */\n+#define TLV_PORT_MODE_100G_Q2                    TLV_PORT_MODE_NA_1x4     /* Single 100G on mdi1 */\n+#define TLV_PORT_MODE_50G_Q1                     TLV_PORT_MODE_1x2_NA     /* Single 50G on mdi0 */\n+#define TLV_PORT_MODE_50G_Q2                     TLV_PORT_MODE_NA_1x2     /* Single 50G on mdi1 */\n+#define TLV_PORT_MODE_25G_25G                    TLV_PORT_MODE_1x1_1x1    /* Single 25G on mdi0, single 25G on mdi1 */\n+#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2      TLV_PORT_MODE_2x1_2x1    /* Dual 25G on mdi0, dual 25G on mdi1 */\n+#define TLV_PORT_MODE_25G_25G_25G_25G_Q1         TLV_PORT_MODE_4x1_NA     /* Quad 25G on mdi0 */\n+#define TLV_PORT_MODE_25G_25G_25G_25G_Q2         TLV_PORT_MODE_NA_4x1     /* Quad 25G on mdi1 */\n+#define TLV_PORT_MODE_40G_25G_25G                TLV_PORT_MODE_1x4_2x1    /* Single 40G on mdi0, dual 25G on mdi1 */\n+#define TLV_PORT_MODE_25G_25G_40G                TLV_PORT_MODE_2x1_1x4    /* Dual 25G on mdi0, single 40G on mdi1 */\n+#define TLV_PORT_MODE_50G_50G_Q1_Q2              TLV_PORT_MODE_1x2_1x2    /* Single 50G on mdi0, single 50G on mdi1 */\n+#define TLV_PORT_MODE_50G_50G_Q1                 TLV_PORT_MODE_2x2_NA     /* Dual 50G on mdi0 */\n+#define TLV_PORT_MODE_50G_50G_Q2                 TLV_PORT_MODE_NA_2x2     /* Dual 50G on mdi1 */\n+#define TLV_PORT_MODE_40G_50G                    TLV_PORT_MODE_1x4_1x2    /* Single 40G on mdi0, single 50G on mdi1 */\n+#define TLV_PORT_MODE_50G_40G                    TLV_PORT_MODE_1x2_1x4    /* Single 50G on mdi0, single 40G on mdi1 */\n+#define TLV_PORT_MODE_50G_25G_25G                TLV_PORT_MODE_1x2_2x1    /* Single 50G on mdi0, dual 25G on mdi1 */\n+#define TLV_PORT_MODE_25G_25G_50G                TLV_PORT_MODE_2x1_1x2    /* Dual 25G on mdi0, single 50G on mdi1 */\n+#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2_LL   TLV_PORT_MODE_2x1_2x1_LL /* Dual 25G on mdi0, dual 25G on mdi1, low-latency PCS */\n+#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_LL      TLV_PORT_MODE_4x1_NA_LL  /* Quad 25G on mdi0, low-latency PCS */\n+#define TLV_PORT_MODE_25G_25G_25G_25G_Q2_LL      TLV_PORT_MODE_NA_4x1_LL  /* Quad 25G on mdi1, low-latency PCS */\n+#define TLV_PORT_MODE_25G_LL                     TLV_PORT_MODE_1x1_NA_LL  /* Single 10G/25G on mdi0, low-latency PCS */\n+#define TLV_PORT_MODE_25G_25G_LL                 TLV_PORT_MODE_1x1_1x1_LL /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */\n };\n \n /* Type of the v-switch created implicitly by the firmware */\ndiff --git a/drivers/net/sfc/base/efx_lic.c b/drivers/net/sfc/base/efx_lic.c\nindex ad4d221..bfad0cd 100644\n--- a/drivers/net/sfc/base/efx_lic.c\n+++ b/drivers/net/sfc/base/efx_lic.c\n@@ -10,6 +10,9 @@\n #if EFSYS_OPT_LICENSING\n \n #include \"ef10_tlv_layout.h\"\n+#if EFSYS_OPT_SIENA\n+#include \"efx_regs_mcdi_aoe.h\"\n+#endif\n \n #if EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON\n \ndiff --git a/drivers/net/sfc/base/efx_regs_mcdi.h b/drivers/net/sfc/base/efx_regs_mcdi.h\nindex 7389877..984c5c9 100644\n--- a/drivers/net/sfc/base/efx_regs_mcdi.h\n+++ b/drivers/net/sfc/base/efx_regs_mcdi.h\n@@ -291,6 +291,14 @@\n /* This command needs to be processed in the background but there were no\n  * resources to do so. Send it again after a command has completed. */\n #define MC_CMD_ERR_QUEUE_FULL 0x1017\n+/* The operation could not be completed because the PCIe link has gone\n+ * away.  This error code is never expected to be returned over the TLP\n+ * transport. */\n+#define MC_CMD_ERR_NO_PCIE 0x1018\n+/* The operation could not be completed because the datapath has gone\n+ * away.  This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the\n+ * datapath absence may be temporary*/\n+#define MC_CMD_ERR_NO_DATAPATH 0x1019\n \n #define MC_CMD_ERR_CODE_OFST 0\n \n@@ -376,6 +384,7 @@\n /* enum: Fatal. */\n #define\tMCDI_EVENT_LEVEL_FATAL 0x3\n #define\tMCDI_EVENT_DATA_OFST 0\n+#define\tMCDI_EVENT_DATA_LEN 4\n #define\tMCDI_EVENT_CMDDONE_SEQ_LBN 0\n #define\tMCDI_EVENT_CMDDONE_SEQ_WIDTH 8\n #define\tMCDI_EVENT_CMDDONE_DATALEN_LBN 8\n@@ -394,6 +403,12 @@\n #define\tMCDI_EVENT_LINKCHANGE_SPEED_10G  0x3\n /* enum: 40Gbs */\n #define\tMCDI_EVENT_LINKCHANGE_SPEED_40G  0x4\n+/* enum: 25Gbs */\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_25G  0x5\n+/* enum: 50Gbs */\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_50G  0x6\n+/* enum: 100Gbs */\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_100G  0x7\n #define\tMCDI_EVENT_LINKCHANGE_FCNTL_LBN 20\n #define\tMCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4\n #define\tMCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24\n@@ -482,8 +497,23 @@\n #define\tMCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf\n /* enum: Notify that the attempt to run FPGA Controller firmware timedout */\n #define\tMCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10\n+/* enum: Failure to probe one or more FPGA boot flash chips */\n+#define\tMCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11\n+/* enum: FPGA boot-flash contains an invalid image header */\n+#define\tMCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12\n+/* enum: Failed to program clocks required by the FPGA */\n+#define\tMCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13\n+/* enum: Notify that FPGA Controller is alive to serve MCDI requests */\n+#define\tMCDI_EVENT_AOE_FC_RUNNING 0x14\n #define\tMCDI_EVENT_AOE_ERR_DATA_LBN 8\n #define\tMCDI_EVENT_AOE_ERR_DATA_WIDTH 8\n+#define\tMCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8\n+#define\tMCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8\n+/* enum: FC Assert happened, but the register information is not available */\n+#define\tMCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0\n+/* enum: The register information for FC Assert is ready for readinng by driver\n+ */\n+#define\tMCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1\n #define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8\n #define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8\n /* enum: Reading from NV failed */\n@@ -536,6 +566,22 @@\n #define\tMCDI_EVENT_MUM_WATCHDOG 0x3\n #define\tMCDI_EVENT_MUM_ERR_DATA_LBN 8\n #define\tMCDI_EVENT_MUM_ERR_DATA_WIDTH 8\n+#define\tMCDI_EVENT_DBRET_SEQ_LBN 0\n+#define\tMCDI_EVENT_DBRET_SEQ_WIDTH 8\n+#define\tMCDI_EVENT_SUC_ERR_TYPE_LBN 0\n+#define\tMCDI_EVENT_SUC_ERR_TYPE_WIDTH 8\n+/* enum: Corrupted or bad SUC application. */\n+#define\tMCDI_EVENT_SUC_BAD_APP 0x1\n+/* enum: SUC application reported an assert. */\n+#define\tMCDI_EVENT_SUC_ASSERT 0x2\n+/* enum: SUC application reported an exception. */\n+#define\tMCDI_EVENT_SUC_EXCEPTION 0x3\n+/* enum: SUC watchdog timer expired. */\n+#define\tMCDI_EVENT_SUC_WATCHDOG 0x4\n+#define\tMCDI_EVENT_SUC_ERR_ADDRESS_LBN 8\n+#define\tMCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24\n+#define\tMCDI_EVENT_SUC_ERR_DATA_LBN 8\n+#define\tMCDI_EVENT_SUC_ERR_DATA_WIDTH 24\n #define\tMCDI_EVENT_DATA_LBN 0\n #define\tMCDI_EVENT_DATA_WIDTH 32\n #define\tMCDI_EVENT_SRC_LBN 36\n@@ -608,73 +654,99 @@\n  * been processed and it may now resend the command\n  */\n #define\tMCDI_EVENT_CODE_PROXY_RESPONSE 0x1d\n+/* enum: MCDI command accepted. New commands can be issued but this command is\n+ * not done yet.\n+ */\n+#define\tMCDI_EVENT_CODE_DBRET 0x1e\n+/* enum: The MC has detected a fault on the SUC */\n+#define\tMCDI_EVENT_CODE_SUC 0x1f\n /* enum: Artificial event generated by host and posted via MC for test\n  * purposes.\n  */\n #define\tMCDI_EVENT_CODE_TESTGEN  0xfa\n #define\tMCDI_EVENT_CMDDONE_DATA_OFST 0\n+#define\tMCDI_EVENT_CMDDONE_DATA_LEN 4\n #define\tMCDI_EVENT_CMDDONE_DATA_LBN 0\n #define\tMCDI_EVENT_CMDDONE_DATA_WIDTH 32\n #define\tMCDI_EVENT_LINKCHANGE_DATA_OFST 0\n+#define\tMCDI_EVENT_LINKCHANGE_DATA_LEN 4\n #define\tMCDI_EVENT_LINKCHANGE_DATA_LBN 0\n #define\tMCDI_EVENT_LINKCHANGE_DATA_WIDTH 32\n #define\tMCDI_EVENT_SENSOREVT_DATA_OFST 0\n+#define\tMCDI_EVENT_SENSOREVT_DATA_LEN 4\n #define\tMCDI_EVENT_SENSOREVT_DATA_LBN 0\n #define\tMCDI_EVENT_SENSOREVT_DATA_WIDTH 32\n #define\tMCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0\n+#define\tMCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4\n #define\tMCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0\n #define\tMCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32\n #define\tMCDI_EVENT_TX_ERR_DATA_OFST 0\n+#define\tMCDI_EVENT_TX_ERR_DATA_LEN 4\n #define\tMCDI_EVENT_TX_ERR_DATA_LBN 0\n #define\tMCDI_EVENT_TX_ERR_DATA_WIDTH 32\n /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of\n  * timestamp\n  */\n #define\tMCDI_EVENT_PTP_SECONDS_OFST 0\n+#define\tMCDI_EVENT_PTP_SECONDS_LEN 4\n #define\tMCDI_EVENT_PTP_SECONDS_LBN 0\n #define\tMCDI_EVENT_PTP_SECONDS_WIDTH 32\n /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of\n  * timestamp\n  */\n #define\tMCDI_EVENT_PTP_MAJOR_OFST 0\n+#define\tMCDI_EVENT_PTP_MAJOR_LEN 4\n #define\tMCDI_EVENT_PTP_MAJOR_LBN 0\n #define\tMCDI_EVENT_PTP_MAJOR_WIDTH 32\n /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field\n  * of timestamp\n  */\n #define\tMCDI_EVENT_PTP_NANOSECONDS_OFST 0\n+#define\tMCDI_EVENT_PTP_NANOSECONDS_LEN 4\n #define\tMCDI_EVENT_PTP_NANOSECONDS_LBN 0\n #define\tMCDI_EVENT_PTP_NANOSECONDS_WIDTH 32\n /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of\n  * timestamp\n  */\n #define\tMCDI_EVENT_PTP_MINOR_OFST 0\n+#define\tMCDI_EVENT_PTP_MINOR_LEN 4\n #define\tMCDI_EVENT_PTP_MINOR_LBN 0\n #define\tMCDI_EVENT_PTP_MINOR_WIDTH 32\n /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet\n  */\n #define\tMCDI_EVENT_PTP_UUID_OFST 0\n+#define\tMCDI_EVENT_PTP_UUID_LEN 4\n #define\tMCDI_EVENT_PTP_UUID_LBN 0\n #define\tMCDI_EVENT_PTP_UUID_WIDTH 32\n #define\tMCDI_EVENT_RX_ERR_DATA_OFST 0\n+#define\tMCDI_EVENT_RX_ERR_DATA_LEN 4\n #define\tMCDI_EVENT_RX_ERR_DATA_LBN 0\n #define\tMCDI_EVENT_RX_ERR_DATA_WIDTH 32\n #define\tMCDI_EVENT_PAR_ERR_DATA_OFST 0\n+#define\tMCDI_EVENT_PAR_ERR_DATA_LEN 4\n #define\tMCDI_EVENT_PAR_ERR_DATA_LBN 0\n #define\tMCDI_EVENT_PAR_ERR_DATA_WIDTH 32\n #define\tMCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0\n+#define\tMCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4\n #define\tMCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0\n #define\tMCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32\n #define\tMCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0\n+#define\tMCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4\n #define\tMCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0\n #define\tMCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32\n /* For CODE_PTP_TIME events, the major value of the PTP clock */\n #define\tMCDI_EVENT_PTP_TIME_MAJOR_OFST 0\n+#define\tMCDI_EVENT_PTP_TIME_MAJOR_LEN 4\n #define\tMCDI_EVENT_PTP_TIME_MAJOR_LBN 0\n #define\tMCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32\n /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */\n #define\tMCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36\n #define\tMCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8\n+/* For CODE_PTP_TIME events, most significant bits of the minor value of the\n+ * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.\n+ */\n+#define\tMCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36\n+#define\tMCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8\n /* For CODE_PTP_TIME events where report sync status is enabled, indicates\n  * whether the NIC clock has ever been set\n  */\n@@ -690,10 +762,17 @@\n  */\n #define\tMCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38\n #define\tMCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6\n+/* For CODE_PTP_TIME events, most significant bits of the minor value of the\n+ * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.\n+ */\n+#define\tMCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38\n+#define\tMCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6\n #define\tMCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0\n+#define\tMCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4\n #define\tMCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0\n #define\tMCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32\n #define\tMCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0\n+#define\tMCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4\n #define\tMCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0\n #define\tMCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32\n /* Zero means that the request has been completed or authorized, and the driver\n@@ -702,6 +781,10 @@\n  */\n #define\tMCDI_EVENT_PROXY_RESPONSE_RC_LBN 36\n #define\tMCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8\n+#define\tMCDI_EVENT_DBRET_DATA_OFST 0\n+#define\tMCDI_EVENT_DBRET_DATA_LEN 4\n+#define\tMCDI_EVENT_DBRET_DATA_LBN 0\n+#define\tMCDI_EVENT_DBRET_DATA_WIDTH 32\n \n /* FCDI_EVENT structuredef */\n #define\tFCDI_EVENT_LEN 8\n@@ -718,6 +801,7 @@\n /* enum: Fatal. */\n #define\tFCDI_EVENT_LEVEL_FATAL 0x3\n #define\tFCDI_EVENT_DATA_OFST 0\n+#define\tFCDI_EVENT_DATA_LEN 4\n #define\tFCDI_EVENT_LINK_STATE_STATUS_LBN 0\n #define\tFCDI_EVENT_LINK_STATE_STATUS_WIDTH 1\n #define\tFCDI_EVENT_LINK_DOWN 0x0 /* enum */\n@@ -757,6 +841,7 @@\n #define\tFCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */\n #define\tFCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */\n #define\tFCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0\n+#define\tFCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4\n #define\tFCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0\n #define\tFCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32\n #define\tFCDI_EVENT_ASSERT_TYPE_LBN 36\n@@ -764,12 +849,15 @@\n #define\tFCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36\n #define\tFCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8\n #define\tFCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0\n+#define\tFCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4\n #define\tFCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0\n #define\tFCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32\n #define\tFCDI_EVENT_LINK_STATE_DATA_OFST 0\n+#define\tFCDI_EVENT_LINK_STATE_DATA_LEN 4\n #define\tFCDI_EVENT_LINK_STATE_DATA_LBN 0\n #define\tFCDI_EVENT_LINK_STATE_DATA_WIDTH 32\n #define\tFCDI_EVENT_PTP_STATE_OFST 0\n+#define\tFCDI_EVENT_PTP_STATE_LEN 4\n #define\tFCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */\n #define\tFCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */\n #define\tFCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */\n@@ -778,6 +866,7 @@\n #define\tFCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36\n #define\tFCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8\n #define\tFCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0\n+#define\tFCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4\n #define\tFCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0\n #define\tFCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32\n /* Index of MC port being referred to */\n@@ -785,9 +874,11 @@\n #define\tFCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8\n /* FC Port index that matches the MC port index in SRC */\n #define\tFCDI_EVENT_PORT_CONFIG_DATA_OFST 0\n+#define\tFCDI_EVENT_PORT_CONFIG_DATA_LEN 4\n #define\tFCDI_EVENT_PORT_CONFIG_DATA_LBN 0\n #define\tFCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32\n #define\tFCDI_EVENT_BOOT_RESULT_OFST 0\n+#define\tFCDI_EVENT_BOOT_RESULT_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */\n #define\tFCDI_EVENT_BOOT_RESULT_LBN 0\n@@ -804,14 +895,17 @@\n #define\tFCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))\n /* Number of timestamps following */\n #define\tFCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0\n+#define\tFCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4\n #define\tFCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0\n #define\tFCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32\n /* Seconds field of a timestamp record */\n #define\tFCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8\n+#define\tFCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4\n #define\tFCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64\n #define\tFCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32\n /* Nanoseconds field of a timestamp record */\n #define\tFCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12\n+#define\tFCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4\n #define\tFCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96\n #define\tFCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32\n /* Timestamp records comprising the event */\n@@ -839,6 +933,7 @@\n /* enum: Fatal. */\n #define\tMUM_EVENT_LEVEL_FATAL 0x3\n #define\tMUM_EVENT_DATA_OFST 0\n+#define\tMUM_EVENT_DATA_LEN 4\n #define\tMUM_EVENT_SENSOR_ID_LBN 0\n #define\tMUM_EVENT_SENSOR_ID_WIDTH 8\n /*             Enum values, see field(s): */\n@@ -876,18 +971,23 @@\n /* enum: Link fault has been asserted, or has cleared. */\n #define\tMUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4\n #define\tMUM_EVENT_SENSOR_DATA_OFST 0\n+#define\tMUM_EVENT_SENSOR_DATA_LEN 4\n #define\tMUM_EVENT_SENSOR_DATA_LBN 0\n #define\tMUM_EVENT_SENSOR_DATA_WIDTH 32\n #define\tMUM_EVENT_PORT_PHY_FLAGS_OFST 0\n+#define\tMUM_EVENT_PORT_PHY_FLAGS_LEN 4\n #define\tMUM_EVENT_PORT_PHY_FLAGS_LBN 0\n #define\tMUM_EVENT_PORT_PHY_FLAGS_WIDTH 32\n #define\tMUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0\n+#define\tMUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4\n #define\tMUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0\n #define\tMUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32\n #define\tMUM_EVENT_PORT_PHY_CAPS_OFST 0\n+#define\tMUM_EVENT_PORT_PHY_CAPS_LEN 4\n #define\tMUM_EVENT_PORT_PHY_CAPS_LBN 0\n #define\tMUM_EVENT_PORT_PHY_CAPS_WIDTH 32\n #define\tMUM_EVENT_PORT_PHY_TECH_OFST 0\n+#define\tMUM_EVENT_PORT_PHY_TECH_LEN 4\n #define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */\n #define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */\n #define\tMUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */\n@@ -911,7 +1011,9 @@\n \n /***********************************/\n /* MC_CMD_READ32\n- * Read multiple 32byte words from MC memory.\n+ * Read multiple 32byte words from MC memory. Note - this command really\n+ * belongs to INSECURE category but is required by shmboot. The command handler\n+ * has additional checks to reject insecure calls.\n  */\n #define\tMC_CMD_READ32 0x1\n #undef\tMC_CMD_0x1_PRIVILEGE_CTG\n@@ -921,7 +1023,9 @@\n /* MC_CMD_READ32_IN msgrequest */\n #define\tMC_CMD_READ32_IN_LEN 8\n #define\tMC_CMD_READ32_IN_ADDR_OFST 0\n+#define\tMC_CMD_READ32_IN_ADDR_LEN 4\n #define\tMC_CMD_READ32_IN_NUMWORDS_OFST 4\n+#define\tMC_CMD_READ32_IN_NUMWORDS_LEN 4\n \n /* MC_CMD_READ32_OUT msgresponse */\n #define\tMC_CMD_READ32_OUT_LENMIN 4\n@@ -940,13 +1044,14 @@\n #define\tMC_CMD_WRITE32 0x2\n #undef\tMC_CMD_0x2_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_WRITE32_IN msgrequest */\n #define\tMC_CMD_WRITE32_IN_LENMIN 8\n #define\tMC_CMD_WRITE32_IN_LENMAX 252\n #define\tMC_CMD_WRITE32_IN_LEN(num) (4+4*(num))\n #define\tMC_CMD_WRITE32_IN_ADDR_OFST 0\n+#define\tMC_CMD_WRITE32_IN_ADDR_LEN 4\n #define\tMC_CMD_WRITE32_IN_BUFFER_OFST 4\n #define\tMC_CMD_WRITE32_IN_BUFFER_LEN 4\n #define\tMC_CMD_WRITE32_IN_BUFFER_MINNUM 1\n@@ -958,7 +1063,9 @@\n \n /***********************************/\n /* MC_CMD_COPYCODE\n- * Copy MC code between two locations and jump.\n+ * Copy MC code between two locations and jump. Note - this command really\n+ * belongs to INSECURE category but is required by shmboot. The command handler\n+ * has additional checks to reject insecure calls.\n  */\n #define\tMC_CMD_COPYCODE 0x3\n #undef\tMC_CMD_0x3_PRIVILEGE_CTG\n@@ -974,6 +1081,7 @@\n  * is a bitfield, with each bit as documented below.\n  */\n #define\tMC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0\n+#define\tMC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4\n /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */\n #define\tMC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000\n /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and\n@@ -999,9 +1107,12 @@\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1\n /* Destination address */\n #define\tMC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4\n+#define\tMC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4\n #define\tMC_CMD_COPYCODE_IN_NUMWORDS_OFST 8\n+#define\tMC_CMD_COPYCODE_IN_NUMWORDS_LEN 4\n /* Address of where to jump after copy. */\n #define\tMC_CMD_COPYCODE_IN_JUMP_OFST 12\n+#define\tMC_CMD_COPYCODE_IN_JUMP_LEN 4\n /* enum: Control should return to the caller rather than jumping */\n #define\tMC_CMD_COPYCODE_JUMP_NONE 0x1\n \n@@ -1016,12 +1127,13 @@\n #define\tMC_CMD_SET_FUNC 0x4\n #undef\tMC_CMD_0x4_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_SET_FUNC_IN msgrequest */\n #define\tMC_CMD_SET_FUNC_IN_LEN 4\n /* Set function */\n #define\tMC_CMD_SET_FUNC_IN_FUNC_OFST 0\n+#define\tMC_CMD_SET_FUNC_IN_FUNC_LEN 4\n \n /* MC_CMD_SET_FUNC_OUT msgresponse */\n #define\tMC_CMD_SET_FUNC_OUT_LEN 0\n@@ -1034,7 +1146,7 @@\n #define\tMC_CMD_GET_BOOT_STATUS 0x5\n #undef\tMC_CMD_0x5_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n \n /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */\n #define\tMC_CMD_GET_BOOT_STATUS_IN_LEN 0\n@@ -1043,9 +1155,11 @@\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_LEN 8\n /* ?? */\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4\n /* enum: indicates that the MC wasn't flash booted */\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL  0xdeadbeef\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1\n@@ -1069,11 +1183,13 @@\n #define\tMC_CMD_GET_ASSERTS_IN_LEN 4\n /* Set to clear assertion */\n #define\tMC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0\n+#define\tMC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4\n \n /* MC_CMD_GET_ASSERTS_OUT msgresponse */\n #define\tMC_CMD_GET_ASSERTS_OUT_LEN 140\n /* Assertion status flag. */\n #define\tMC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0\n+#define\tMC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4\n /* enum: No assertions have failed. */\n #define\tMC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1\n /* enum: A system-level assertion has failed. */\n@@ -1086,6 +1202,7 @@\n #define\tMC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5\n /* Failing PC value */\n #define\tMC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4\n+#define\tMC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4\n /* Saved GP regs */\n #define\tMC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8\n #define\tMC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4\n@@ -1096,7 +1213,9 @@\n #define\tMC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057\n /* Failing thread address */\n #define\tMC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132\n+#define\tMC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4\n #define\tMC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136\n+#define\tMC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4\n \n \n /***********************************/\n@@ -1113,12 +1232,14 @@\n #define\tMC_CMD_LOG_CTRL_IN_LEN 8\n /* Log destination */\n #define\tMC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0\n+#define\tMC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4\n /* enum: UART. */\n #define\tMC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1\n /* enum: Event queue. */\n #define\tMC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2\n /* Legacy argument. Must be zero. */\n #define\tMC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4\n+#define\tMC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4\n \n /* MC_CMD_LOG_CTRL_OUT msgresponse */\n #define\tMC_CMD_LOG_CTRL_OUT_LEN 0\n@@ -1140,23 +1261,29 @@\n #define\tMC_CMD_GET_VERSION_EXT_IN_LEN 4\n /* placeholder, set to 0 */\n #define\tMC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0\n+#define\tMC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4\n \n /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */\n #define\tMC_CMD_GET_VERSION_V0_OUT_LEN 4\n #define\tMC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0\n+#define\tMC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4\n /* enum: Reserved version number to indicate \"any\" version. */\n #define\tMC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff\n /* enum: Bootrom version value for Siena. */\n #define\tMC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000\n /* enum: Bootrom version value for Huntington. */\n #define\tMC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001\n+/* enum: Bootrom version value for Medford2. */\n+#define\tMC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002\n \n /* MC_CMD_GET_VERSION_OUT msgresponse */\n #define\tMC_CMD_GET_VERSION_OUT_LEN 32\n /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */\n+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */\n /*            Enum values, see field(s): */\n /*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */\n #define\tMC_CMD_GET_VERSION_OUT_PCOL_OFST 4\n+#define\tMC_CMD_GET_VERSION_OUT_PCOL_LEN 4\n /* 128bit mask of functions supported by the current firmware */\n #define\tMC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8\n #define\tMC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16\n@@ -1168,9 +1295,11 @@\n /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */\n #define\tMC_CMD_GET_VERSION_EXT_OUT_LEN 48\n /*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */\n+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */\n /*            Enum values, see field(s): */\n /*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */\n #define\tMC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4\n /* 128bit mask of functions supported by the current firmware */\n #define\tMC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8\n #define\tMC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16\n@@ -1184,2421 +1313,6 @@\n \n \n /***********************************/\n-/* MC_CMD_FC\n- * Perform an FC operation\n- */\n-#define\tMC_CMD_FC 0x9\n-\n-/* MC_CMD_FC_IN msgrequest */\n-#define\tMC_CMD_FC_IN_LEN 4\n-#define\tMC_CMD_FC_IN_OP_HDR_OFST 0\n-#define\tMC_CMD_FC_IN_OP_LBN 0\n-#define\tMC_CMD_FC_IN_OP_WIDTH 8\n-/* enum: NULL MCDI command to FC. */\n-#define\tMC_CMD_FC_OP_NULL 0x1\n-/* enum: Unused opcode */\n-#define\tMC_CMD_FC_OP_UNUSED 0x2\n-/* enum: MAC driver commands */\n-#define\tMC_CMD_FC_OP_MAC 0x3\n-/* enum: Read FC memory */\n-#define\tMC_CMD_FC_OP_READ32 0x4\n-/* enum: Write to FC memory */\n-#define\tMC_CMD_FC_OP_WRITE32 0x5\n-/* enum: Read FC memory */\n-#define\tMC_CMD_FC_OP_TRC_READ 0x6\n-/* enum: Write to FC memory */\n-#define\tMC_CMD_FC_OP_TRC_WRITE 0x7\n-/* enum: FC firmware Version */\n-#define\tMC_CMD_FC_OP_GET_VERSION 0x8\n-/* enum: Read FC memory */\n-#define\tMC_CMD_FC_OP_TRC_RX_READ 0x9\n-/* enum: Write to FC memory */\n-#define\tMC_CMD_FC_OP_TRC_RX_WRITE 0xa\n-/* enum: SFP parameters */\n-#define\tMC_CMD_FC_OP_SFP 0xb\n-/* enum: DDR3 test */\n-#define\tMC_CMD_FC_OP_DDR_TEST 0xc\n-/* enum: Get Crash context from FC */\n-#define\tMC_CMD_FC_OP_GET_ASSERT 0xd\n-/* enum: Get FPGA Build registers */\n-#define\tMC_CMD_FC_OP_FPGA_BUILD 0xe\n-/* enum: Read map support commands */\n-#define\tMC_CMD_FC_OP_READ_MAP 0xf\n-/* enum: FC Capabilities */\n-#define\tMC_CMD_FC_OP_CAPABILITIES 0x10\n-/* enum: FC Global flags */\n-#define\tMC_CMD_FC_OP_GLOBAL_FLAGS 0x11\n-/* enum: FC IO using relative addressing modes */\n-#define\tMC_CMD_FC_OP_IO_REL 0x12\n-/* enum: FPGA link information */\n-#define\tMC_CMD_FC_OP_UHLINK 0x13\n-/* enum: Configure loopbacks and link on FPGA ports */\n-#define\tMC_CMD_FC_OP_SET_LINK 0x14\n-/* enum: Licensing operations relating to AOE */\n-#define\tMC_CMD_FC_OP_LICENSE 0x15\n-/* enum: Startup information to the FC */\n-#define\tMC_CMD_FC_OP_STARTUP 0x16\n-/* enum: Configure a DMA read */\n-#define\tMC_CMD_FC_OP_DMA 0x17\n-/* enum: Configure a timed read */\n-#define\tMC_CMD_FC_OP_TIMED_READ 0x18\n-/* enum: Control UART logging */\n-#define\tMC_CMD_FC_OP_LOG 0x19\n-/* enum: Get the value of a given clock_id */\n-#define\tMC_CMD_FC_OP_CLOCK 0x1a\n-/* enum: DDR3/QDR3 parameters */\n-#define\tMC_CMD_FC_OP_DDR 0x1b\n-/* enum: PTP and timestamp control */\n-#define\tMC_CMD_FC_OP_TIMESTAMP 0x1c\n-/* enum: Commands for SPI Flash interface */\n-#define\tMC_CMD_FC_OP_SPI 0x1d\n-/* enum: Commands for diagnostic components */\n-#define\tMC_CMD_FC_OP_DIAG 0x1e\n-/* enum: External AOE port. */\n-#define\tMC_CMD_FC_IN_PORT_EXT_OFST 0x0\n-/* enum: Internal AOE port. */\n-#define\tMC_CMD_FC_IN_PORT_INT_OFST 0x40\n-\n-/* MC_CMD_FC_IN_NULL msgrequest */\n-#define\tMC_CMD_FC_IN_NULL_LEN 4\n-#define\tMC_CMD_FC_IN_CMD_OFST 0\n-\n-/* MC_CMD_FC_IN_PHY msgrequest */\n-#define\tMC_CMD_FC_IN_PHY_LEN 5\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/* FC PHY driver operation code */\n-#define\tMC_CMD_FC_IN_PHY_OP_OFST 4\n-#define\tMC_CMD_FC_IN_PHY_OP_LEN 1\n-/* enum: PHY init handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_INIT 0x1\n-/* enum: PHY reconfigure handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2\n-/* enum: PHY reboot handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_REBOOT 0x3\n-/* enum: PHY get_supported_cap handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4\n-/* enum: PHY get_config handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5\n-/* enum: PHY get_media_info handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6\n-/* enum: PHY set_led handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_SET_LED 0x7\n-/* enum: PHY lasi_interrupt handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8\n-/* enum: PHY check_link handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9\n-/* enum: PHY fill_stats handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa\n-/* enum: PHY bpx_link_state_changed handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb\n-/* enum: PHY get_state handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_GET_STATE 0xc\n-/* enum: PHY start_bist handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_START_BIST 0xd\n-/* enum: PHY poll_bist handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe\n-/* enum: PHY nvram_test handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf\n-/* enum: PHY relinquish handler */\n-#define\tMC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10\n-/* enum: PHY read connection from FC - may be not required */\n-#define\tMC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11\n-/* enum: PHY read flags from FC - may be not required */\n-#define\tMC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12\n-\n-/* MC_CMD_FC_IN_PHY_INIT msgrequest */\n-#define\tMC_CMD_FC_IN_PHY_INIT_LEN 4\n-#define\tMC_CMD_FC_IN_PHY_CMD_OFST 0\n-\n-/* MC_CMD_FC_IN_MAC msgrequest */\n-#define\tMC_CMD_FC_IN_MAC_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_MAC_HEADER_OFST 4\n-#define\tMC_CMD_FC_IN_MAC_OP_LBN 0\n-#define\tMC_CMD_FC_IN_MAC_OP_WIDTH 8\n-/* enum: MAC reconfigure handler */\n-#define\tMC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1\n-/* enum: MAC Set command - same as MC_CMD_SET_MAC */\n-#define\tMC_CMD_FC_OP_MAC_OP_SET_LINK 0x2\n-/* enum: MAC statistics */\n-#define\tMC_CMD_FC_OP_MAC_OP_GET_STATS 0x3\n-/* enum: MAC RX statistics */\n-#define\tMC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6\n-/* enum: MAC TX statistics */\n-#define\tMC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7\n-/* enum: MAC Read status */\n-#define\tMC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8\n-#define\tMC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8\n-#define\tMC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8\n-/* enum: External FPGA port. */\n-#define\tMC_CMD_FC_PORT_EXT 0x0\n-/* enum: Internal Siena-facing FPGA ports. */\n-#define\tMC_CMD_FC_PORT_INT 0x1\n-#define\tMC_CMD_FC_IN_MAC_PORT_IDX_LBN 16\n-#define\tMC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8\n-#define\tMC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24\n-#define\tMC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8\n-/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are\n- * irrelevant. Port number is derived from pci_fn; passed in FC header.\n- */\n-#define\tMC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0\n-/* enum: Override default port number. Port number determined by fields\n- * PORT_TYPE and PORT_IDX.\n- */\n-#define\tMC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1\n-\n-/* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */\n-#define\tMC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n-\n-/* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_LEN 32\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n-/* MTU size */\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8\n-/* Drain Tx FIFO */\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1\n-#define\tMC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28\n-\n-/* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */\n-#define\tMC_CMD_FC_IN_MAC_READ_STATUS_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n-\n-/* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */\n-#define\tMC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n-\n-/* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */\n-#define\tMC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n-\n-/* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */\n-#define\tMC_CMD_FC_IN_MAC_GET_STATS_LEN 20\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n-/* MC Statistics index */\n-#define\tMC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8\n-#define\tMC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12\n-#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0\n-#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1\n-#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1\n-#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1\n-#define\tMC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2\n-#define\tMC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1\n-/* Number of statistics to read */\n-#define\tMC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16\n-#define\tMC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */\n-#define\tMC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */\n-\n-/* MC_CMD_FC_IN_READ32 msgrequest */\n-#define\tMC_CMD_FC_IN_READ32_LEN 16\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_READ32_ADDR_HI_OFST 4\n-#define\tMC_CMD_FC_IN_READ32_ADDR_LO_OFST 8\n-#define\tMC_CMD_FC_IN_READ32_NUMWORDS_OFST 12\n-\n-/* MC_CMD_FC_IN_WRITE32 msgrequest */\n-#define\tMC_CMD_FC_IN_WRITE32_LENMIN 16\n-#define\tMC_CMD_FC_IN_WRITE32_LENMAX 252\n-#define\tMC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num))\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4\n-#define\tMC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8\n-#define\tMC_CMD_FC_IN_WRITE32_BUFFER_OFST 12\n-#define\tMC_CMD_FC_IN_WRITE32_BUFFER_LEN 4\n-#define\tMC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1\n-#define\tMC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60\n-\n-/* MC_CMD_FC_IN_TRC_READ msgrequest */\n-#define\tMC_CMD_FC_IN_TRC_READ_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_TRC_READ_TRC_OFST 4\n-#define\tMC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8\n-\n-/* MC_CMD_FC_IN_TRC_WRITE msgrequest */\n-#define\tMC_CMD_FC_IN_TRC_WRITE_LEN 28\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4\n-#define\tMC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8\n-#define\tMC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12\n-#define\tMC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4\n-#define\tMC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4\n-\n-/* MC_CMD_FC_IN_GET_VERSION msgrequest */\n-#define\tMC_CMD_FC_IN_GET_VERSION_LEN 4\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-\n-/* MC_CMD_FC_IN_TRC_RX_READ msgrequest */\n-#define\tMC_CMD_FC_IN_TRC_RX_READ_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4\n-#define\tMC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8\n-\n-/* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */\n-#define\tMC_CMD_FC_IN_TRC_RX_WRITE_LEN 20\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4\n-#define\tMC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8\n-#define\tMC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12\n-#define\tMC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4\n-#define\tMC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2\n-\n-/* MC_CMD_FC_IN_SFP msgrequest */\n-#define\tMC_CMD_FC_IN_SFP_LEN 28\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/* Link speed is 100, 1000, 10000, 40000 */\n-#define\tMC_CMD_FC_IN_SFP_SPEED_OFST 4\n-/* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */\n-#define\tMC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8\n-/* Not relevant for cards with QSFP modules. For older cards, true if module is\n- * a dual speed SFP+ module.\n- */\n-#define\tMC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12\n-/* True if an SFP Module is present (other fields valid when true) */\n-#define\tMC_CMD_FC_IN_SFP_PRESENT_OFST 16\n-/* The type of the SFP+ Module. For later cards with QSFP modules, this field\n- * is unused and the type is communicated by other means.\n- */\n-#define\tMC_CMD_FC_IN_SFP_TYPE_OFST 20\n-/* Capabilities corresponding to 1 bits. */\n-#define\tMC_CMD_FC_IN_SFP_CAPS_OFST 24\n-\n-/* MC_CMD_FC_IN_DDR_TEST msgrequest */\n-#define\tMC_CMD_FC_IN_DDR_TEST_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4\n-#define\tMC_CMD_FC_IN_DDR_TEST_OP_LBN 0\n-#define\tMC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8\n-/* enum: DRAM Test Start */\n-#define\tMC_CMD_FC_OP_DDR_TEST_START 0x1\n-/* enum: DRAM Test Poll */\n-#define\tMC_CMD_FC_OP_DDR_TEST_POLL 0x2\n-\n-/* MC_CMD_FC_IN_DDR_TEST_START msgrequest */\n-#define\tMC_CMD_FC_IN_DDR_TEST_START_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */\n-#define\tMC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8\n-#define\tMC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0\n-#define\tMC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1\n-#define\tMC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1\n-#define\tMC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1\n-#define\tMC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2\n-#define\tMC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1\n-#define\tMC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3\n-#define\tMC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1\n-\n-/* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */\n-#define\tMC_CMD_FC_IN_DDR_TEST_POLL_LEN 12\n-#define\tMC_CMD_FC_IN_DDR_TEST_CMD_OFST 0\n-/*            MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */\n-/* Clear previous test result and prepare for restarting DDR test */\n-#define\tMC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8\n-\n-/* MC_CMD_FC_IN_GET_ASSERT msgrequest */\n-#define\tMC_CMD_FC_IN_GET_ASSERT_LEN 4\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-\n-/* MC_CMD_FC_IN_FPGA_BUILD msgrequest */\n-#define\tMC_CMD_FC_IN_FPGA_BUILD_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/* FPGA build info operation code */\n-#define\tMC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4\n-/* enum: Get the build registers */\n-#define\tMC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1\n-/* enum: Get the services registers */\n-#define\tMC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2\n-/* enum: Get the BSP version */\n-#define\tMC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3\n-/* enum: Get build register for V2 (SFA974X) */\n-#define\tMC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4\n-/* enum: GEt the services register for V2 (SFA974X) */\n-#define\tMC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5\n-\n-/* MC_CMD_FC_IN_READ_MAP msgrequest */\n-#define\tMC_CMD_FC_IN_READ_MAP_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_READ_MAP_HEADER_OFST 4\n-#define\tMC_CMD_FC_IN_READ_MAP_OP_LBN 0\n-#define\tMC_CMD_FC_IN_READ_MAP_OP_WIDTH 8\n-/* enum: Get the number of map regions */\n-#define\tMC_CMD_FC_OP_READ_MAP_COUNT 0x1\n-/* enum: Get the specified map */\n-#define\tMC_CMD_FC_OP_READ_MAP_INDEX 0x2\n-\n-/* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */\n-#define\tMC_CMD_FC_IN_READ_MAP_COUNT_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */\n-\n-/* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */\n-#define\tMC_CMD_FC_IN_READ_MAP_INDEX_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */\n-#define\tMC_CMD_FC_IN_MAP_INDEX_OFST 8\n-\n-/* MC_CMD_FC_IN_CAPABILITIES msgrequest */\n-#define\tMC_CMD_FC_IN_CAPABILITIES_LEN 4\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-\n-/* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5\n-#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1\n-\n-/* MC_CMD_FC_IN_IO_REL msgrequest */\n-#define\tMC_CMD_FC_IN_IO_REL_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_IO_REL_HEADER_OFST 4\n-#define\tMC_CMD_FC_IN_IO_REL_OP_LBN 0\n-#define\tMC_CMD_FC_IN_IO_REL_OP_WIDTH 8\n-/* enum: Get the base address that the FC applies to relative commands */\n-#define\tMC_CMD_FC_IN_IO_REL_GET_ADDR 0x1\n-/* enum: Read data */\n-#define\tMC_CMD_FC_IN_IO_REL_READ32 0x2\n-/* enum: Write data */\n-#define\tMC_CMD_FC_IN_IO_REL_WRITE32 0x3\n-#define\tMC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8\n-#define\tMC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8\n-/* enum: Application address space */\n-#define\tMC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1\n-/* enum: Flash address space */\n-#define\tMC_CMD_FC_COMP_TYPE_FLASH 0x2\n-\n-/* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */\n-#define\tMC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */\n-\n-/* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */\n-#define\tMC_CMD_FC_IN_IO_REL_READ32_LEN 20\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */\n-#define\tMC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8\n-#define\tMC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12\n-#define\tMC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16\n-\n-/* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */\n-#define\tMC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20\n-#define\tMC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252\n-#define\tMC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num))\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */\n-#define\tMC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8\n-#define\tMC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12\n-#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16\n-#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4\n-#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1\n-#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59\n-\n-/* MC_CMD_FC_IN_UHLINK msgrequest */\n-#define\tMC_CMD_FC_IN_UHLINK_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_UHLINK_HEADER_OFST 4\n-#define\tMC_CMD_FC_IN_UHLINK_OP_LBN 0\n-#define\tMC_CMD_FC_IN_UHLINK_OP_WIDTH 8\n-/* enum: Get PHY configuration info */\n-#define\tMC_CMD_FC_OP_UHLINK_PHY 0x1\n-/* enum: Get MAC configuration info */\n-#define\tMC_CMD_FC_OP_UHLINK_MAC 0x2\n-/* enum: Get Rx eye table */\n-#define\tMC_CMD_FC_OP_UHLINK_RX_EYE 0x3\n-/* enum: Get Rx eye plot */\n-#define\tMC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4\n-/* enum: Get Rx eye plot */\n-#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5\n-/* enum: Retune Rx settings */\n-#define\tMC_CMD_FC_OP_UHLINK_RX_TUNE 0x6\n-/* enum: Set loopback mode on fpga port */\n-#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7\n-/* enum: Get loopback mode config state on fpga port */\n-#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8\n-#define\tMC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8\n-#define\tMC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8\n-#define\tMC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16\n-#define\tMC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8\n-#define\tMC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24\n-#define\tMC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8\n-/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are\n- * irrelevant. Port number is derived from pci_fn; passed in FC header.\n- */\n-#define\tMC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0\n-/* enum: Override default port number. Port number determined by fields\n- * PORT_TYPE and PORT_IDX.\n- */\n-#define\tMC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1\n-\n-/* MC_CMD_FC_OP_UHLINK_PHY msgrequest */\n-#define\tMC_CMD_FC_OP_UHLINK_PHY_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n-\n-/* MC_CMD_FC_OP_UHLINK_MAC msgrequest */\n-#define\tMC_CMD_FC_OP_UHLINK_MAC_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n-\n-/* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */\n-#define\tMC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n-#define\tMC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8\n-#define\tMC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */\n-\n-/* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */\n-#define\tMC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n-\n-/* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */\n-#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n-#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8\n-#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12\n-#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16\n-#define\tMC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */\n-\n-/* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */\n-#define\tMC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n-\n-/* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */\n-#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n-#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8\n-#define\tMC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */\n-#define\tMC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */\n-#define\tMC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */\n-#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12\n-#define\tMC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */\n-#define\tMC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */\n-\n-/* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */\n-#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n-#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8\n-\n-/* MC_CMD_FC_IN_SET_LINK msgrequest */\n-#define\tMC_CMD_FC_IN_SET_LINK_LEN 16\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */\n-#define\tMC_CMD_FC_IN_SET_LINK_MODE_OFST 4\n-#define\tMC_CMD_FC_IN_SET_LINK_SPEED_OFST 8\n-#define\tMC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12\n-#define\tMC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0\n-#define\tMC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1\n-#define\tMC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1\n-#define\tMC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1\n-#define\tMC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2\n-#define\tMC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1\n-\n-/* MC_CMD_FC_IN_LICENSE msgrequest */\n-#define\tMC_CMD_FC_IN_LICENSE_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_LICENSE_OP_OFST 4\n-#define\tMC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */\n-#define\tMC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */\n-\n-/* MC_CMD_FC_IN_STARTUP msgrequest */\n-#define\tMC_CMD_FC_IN_STARTUP_LEN 40\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_STARTUP_BASE_OFST 4\n-#define\tMC_CMD_FC_IN_STARTUP_LENGTH_OFST 8\n-/* Length of identifier */\n-#define\tMC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12\n-/* Identifier for AOE FPGA */\n-#define\tMC_CMD_FC_IN_STARTUP_ID_OFST 16\n-#define\tMC_CMD_FC_IN_STARTUP_ID_LEN 1\n-#define\tMC_CMD_FC_IN_STARTUP_ID_NUM 24\n-\n-/* MC_CMD_FC_IN_DMA msgrequest */\n-#define\tMC_CMD_FC_IN_DMA_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DMA_OP_OFST 4\n-#define\tMC_CMD_FC_IN_DMA_STOP  0x0 /* enum */\n-#define\tMC_CMD_FC_IN_DMA_READ  0x1 /* enum */\n-\n-/* MC_CMD_FC_IN_DMA_STOP msgrequest */\n-#define\tMC_CMD_FC_IN_DMA_STOP_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_DMA_OP_OFST 4 */\n-/* FC supplied handle */\n-#define\tMC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8\n-\n-/* MC_CMD_FC_IN_DMA_READ msgrequest */\n-#define\tMC_CMD_FC_IN_DMA_READ_LEN 16\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_DMA_OP_OFST 4 */\n-#define\tMC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8\n-#define\tMC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12\n-\n-/* MC_CMD_FC_IN_TIMED_READ msgrequest */\n-#define\tMC_CMD_FC_IN_TIMED_READ_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_TIMED_READ_OP_OFST 4\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET  0x0 /* enum */\n-#define\tMC_CMD_FC_IN_TIMED_READ_GET  0x1 /* enum */\n-#define\tMC_CMD_FC_IN_TIMED_READ_CLEAR  0x2 /* enum */\n-\n-/* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_LEN 52\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */\n-/* Host supplied handle (unique) */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8\n-/* Address into which to transfer data in host */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16\n-/* AOE address from which to transfer data */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24\n-/* Length of AOE transfer (total) */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28\n-/* Length of host transfer (total) */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32\n-/* Offset back from aoe_address to apply operation to */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36\n-/* Data to apply at offset */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_NONE  0x0 /* enum */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_READ  0x1 /* enum */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_WRITE  0x2 /* enum */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_READWRITE  0x3 /* enum */\n-/* Period at which reads are performed (100ms units) */\n-#define\tMC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48\n-\n-/* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */\n-#define\tMC_CMD_FC_IN_TIMED_READ_GET_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */\n-/* FC supplied handle */\n-#define\tMC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8\n-\n-/* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */\n-#define\tMC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */\n-/* FC supplied handle */\n-#define\tMC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8\n-\n-/* MC_CMD_FC_IN_LOG msgrequest */\n-#define\tMC_CMD_FC_IN_LOG_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_LOG_OP_OFST 4\n-#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE  0x0 /* enum */\n-#define\tMC_CMD_FC_IN_LOG_JTAG_UART  0x1 /* enum */\n-\n-/* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */\n-#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_LOG_OP_OFST 4 */\n-/* Partition offset into flash */\n-#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8\n-/* Partition length */\n-#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12\n-/* Partition erase size */\n-#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16\n-\n-/* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */\n-#define\tMC_CMD_FC_IN_LOG_JTAG_UART_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_LOG_OP_OFST 4 */\n-/* Enable/disable printing to JTAG UART */\n-#define\tMC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8\n-\n-/* MC_CMD_FC_IN_CLOCK msgrequest */\n-#define\tMC_CMD_FC_IN_CLOCK_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_CLOCK_OP_OFST 4\n-#define\tMC_CMD_FC_IN_CLOCK_GET_TIME  0x0 /* enum */\n-#define\tMC_CMD_FC_IN_CLOCK_SET_TIME  0x1 /* enum */\n-/* Perform a clock operation */\n-#define\tMC_CMD_FC_IN_CLOCK_ID_OFST 8\n-#define\tMC_CMD_FC_IN_CLOCK_STATS  0x0 /* enum */\n-#define\tMC_CMD_FC_IN_CLOCK_MAC  0x1 /* enum */\n-\n-/* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */\n-#define\tMC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */\n-/* Retrieve the clock value of the specified clock */\n-/*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */\n-\n-/* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */\n-#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */\n-/*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */\n-#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12\n-#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8\n-#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12\n-#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16\n-/* Set the clock value of the specified clock */\n-#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20\n-\n-/* MC_CMD_FC_IN_DDR msgrequest */\n-#define\tMC_CMD_FC_IN_DDR_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DDR_OP_OFST 4\n-#define\tMC_CMD_FC_IN_DDR_SET_SPD  0x0 /* enum */\n-#define\tMC_CMD_FC_IN_DDR_GET_STATUS  0x1 /* enum */\n-#define\tMC_CMD_FC_IN_DDR_SET_INFO  0x2 /* enum */\n-#define\tMC_CMD_FC_IN_DDR_BANK_OFST 8\n-#define\tMC_CMD_FC_IN_DDR_BANK_B0  0x0 /* enum */\n-#define\tMC_CMD_FC_IN_DDR_BANK_B1  0x1 /* enum */\n-#define\tMC_CMD_FC_IN_DDR_BANK_T0  0x2 /* enum */\n-#define\tMC_CMD_FC_IN_DDR_BANK_T1  0x3 /* enum */\n-#define\tMC_CMD_FC_IN_DDR_NUM_BANKS  0x4 /* enum */\n-\n-/* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */\n-#define\tMC_CMD_FC_IN_DDR_SET_SPD_LEN 148\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_DDR_OP_OFST 4 */\n-/* Affected bank */\n-/*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */\n-/* Flags */\n-#define\tMC_CMD_FC_IN_DDR_FLAGS_OFST 12\n-#define\tMC_CMD_FC_IN_DDR_SET_SPD_ACTIVE  0x1 /* enum */\n-/* 128-byte page of serial presence detect data read from module's EEPROM */\n-#define\tMC_CMD_FC_IN_DDR_SPD_OFST 16\n-#define\tMC_CMD_FC_IN_DDR_SPD_LEN 1\n-#define\tMC_CMD_FC_IN_DDR_SPD_NUM 128\n-/* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */\n-#define\tMC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144\n-\n-/* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */\n-#define\tMC_CMD_FC_IN_DDR_SET_INFO_LEN 16\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_DDR_OP_OFST 4 */\n-/* Affected bank */\n-/*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */\n-/* Size of DDR */\n-#define\tMC_CMD_FC_IN_DDR_SIZE_OFST 12\n-\n-/* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */\n-#define\tMC_CMD_FC_IN_DDR_GET_STATUS_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/*            MC_CMD_FC_IN_DDR_OP_OFST 4 */\n-/* Affected bank */\n-/*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */\n-\n-/* MC_CMD_FC_IN_TIMESTAMP msgrequest */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/* FC timestamp operation code */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_OP_OFST 4\n-/* enum: Read transmit timestamp(s) */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0\n-/* enum: Read snapshot timestamps */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1\n-/* enum: Clear all transmit timestamps */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2\n-\n-/* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4\n-/* Control filtering of the returned timestamp and sequence number specified\n- * here\n- */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8\n-/* enum: Return most recent timestamp. No filtering */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0\n-/* enum: Match timestamp against the PTP clock ID, port number and sequence\n- * number specified\n- */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1\n-/* Clock identity of PTP packet for which timestamp required */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16\n-/* Port number of PTP packet for which timestamp required */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20\n-/* Sequence number of PTP packet for which timestamp required */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24\n-\n-/* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4\n-\n-/* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4\n-\n-/* MC_CMD_FC_IN_SPI msgrequest */\n-#define\tMC_CMD_FC_IN_SPI_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/* Basic commands for SPI Flash. */\n-#define\tMC_CMD_FC_IN_SPI_OP_OFST 4\n-/* enum: SPI Flash read */\n-#define\tMC_CMD_FC_IN_SPI_READ 0x0\n-/* enum: SPI Flash write */\n-#define\tMC_CMD_FC_IN_SPI_WRITE 0x1\n-/* enum: SPI Flash erase */\n-#define\tMC_CMD_FC_IN_SPI_ERASE 0x2\n-\n-/* MC_CMD_FC_IN_SPI_READ msgrequest */\n-#define\tMC_CMD_FC_IN_SPI_READ_LEN 16\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_SPI_READ_OP_OFST 4\n-#define\tMC_CMD_FC_IN_SPI_READ_ADDR_OFST 8\n-#define\tMC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12\n-\n-/* MC_CMD_FC_IN_SPI_WRITE msgrequest */\n-#define\tMC_CMD_FC_IN_SPI_WRITE_LENMIN 16\n-#define\tMC_CMD_FC_IN_SPI_WRITE_LENMAX 252\n-#define\tMC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num))\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_SPI_WRITE_OP_OFST 4\n-#define\tMC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8\n-#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12\n-#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4\n-#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1\n-#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60\n-\n-/* MC_CMD_FC_IN_SPI_ERASE msgrequest */\n-#define\tMC_CMD_FC_IN_SPI_ERASE_LEN 16\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_SPI_ERASE_OP_OFST 4\n-#define\tMC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8\n-#define\tMC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12\n-\n-/* MC_CMD_FC_IN_DIAG msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_LEN 8\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-/* Operation code indicating component type */\n-#define\tMC_CMD_FC_IN_DIAG_OP_OFST 4\n-/* enum: Power noise generator. */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE 0x0\n-/* enum: DDR soak test component. */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK 0x1\n-/* enum: Diagnostics datapath control component. */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2\n-\n-/* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4\n-/* Sub-opcode describing the operation to be carried out */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8\n-/* enum: Read the configuration (the 32-bit values in each of the clock enable\n- * count and toggle count registers)\n- */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0\n-/* enum: Write a new configuration to the clock enable count and toggle count\n- * registers\n- */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1\n-\n-/* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8\n-\n-/* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8\n-/* The 32-bit value to be written to the toggle count register */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12\n-/* The 32-bit value to be written to the clock enable count register */\n-#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16\n-\n-/* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4\n-/* Sub-opcode describing the operation to be carried out */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8\n-/* enum: Starts DDR soak test on selected banks */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0\n-/* enum: Read status of DDR soak test */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1\n-/* enum: Stop test */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2\n-/* enum: Set or clear bit that triggers fake errors. These cause subsequent\n- * tests to fail until the bit is cleared.\n- */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3\n-\n-/* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8\n-/* Mask of DDR banks to be tested */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12\n-/* Pattern to use in the soak test */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */\n-/* Either multiple automatic tests until a STOP command is issued, or one\n- * single test\n- */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */\n-\n-/* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8\n-/* DDR bank to read status from */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12\n-#define\tMC_CMD_FC_DDR_BANK0 0x0 /* enum */\n-#define\tMC_CMD_FC_DDR_BANK1 0x1 /* enum */\n-#define\tMC_CMD_FC_DDR_BANK2 0x2 /* enum */\n-#define\tMC_CMD_FC_DDR_BANK3 0x3 /* enum */\n-#define\tMC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */\n-\n-/* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8\n-/* Mask of DDR banks to be tested */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12\n-\n-/* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8\n-/* Mask of DDR banks to set/clear error flag on */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */\n-#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */\n-\n-/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4\n-/* Sub-opcode describing the operation to be carried out */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8\n-/* enum: Set a known datapath configuration */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0\n-/* enum: Apply raw config to datapath control registers */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1\n-\n-/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8\n-/* Datapath configuration identifier */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */\n-\n-/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24\n-/*            MC_CMD_FC_IN_CMD_OFST 0 */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8\n-/* Value to write into control register 1 */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12\n-/* Value to write into control register 2 */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16\n-/* Value to write into control register 3 */\n-#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20\n-\n-/* MC_CMD_FC_OUT msgresponse */\n-#define\tMC_CMD_FC_OUT_LEN 0\n-\n-/* MC_CMD_FC_OUT_NULL msgresponse */\n-#define\tMC_CMD_FC_OUT_NULL_LEN 0\n-\n-/* MC_CMD_FC_OUT_READ32 msgresponse */\n-#define\tMC_CMD_FC_OUT_READ32_LENMIN 4\n-#define\tMC_CMD_FC_OUT_READ32_LENMAX 252\n-#define\tMC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num))\n-#define\tMC_CMD_FC_OUT_READ32_BUFFER_OFST 0\n-#define\tMC_CMD_FC_OUT_READ32_BUFFER_LEN 4\n-#define\tMC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1\n-#define\tMC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63\n-\n-/* MC_CMD_FC_OUT_WRITE32 msgresponse */\n-#define\tMC_CMD_FC_OUT_WRITE32_LEN 0\n-\n-/* MC_CMD_FC_OUT_TRC_READ msgresponse */\n-#define\tMC_CMD_FC_OUT_TRC_READ_LEN 16\n-#define\tMC_CMD_FC_OUT_TRC_READ_DATA_OFST 0\n-#define\tMC_CMD_FC_OUT_TRC_READ_DATA_LEN 4\n-#define\tMC_CMD_FC_OUT_TRC_READ_DATA_NUM 4\n-\n-/* MC_CMD_FC_OUT_TRC_WRITE msgresponse */\n-#define\tMC_CMD_FC_OUT_TRC_WRITE_LEN 0\n-\n-/* MC_CMD_FC_OUT_GET_VERSION msgresponse */\n-#define\tMC_CMD_FC_OUT_GET_VERSION_LEN 12\n-#define\tMC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0\n-#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4\n-#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8\n-#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4\n-#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8\n-\n-/* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */\n-#define\tMC_CMD_FC_OUT_TRC_RX_READ_LEN 8\n-#define\tMC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0\n-#define\tMC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4\n-#define\tMC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2\n-\n-/* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */\n-#define\tMC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0\n-\n-/* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */\n-#define\tMC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0\n-\n-/* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */\n-#define\tMC_CMD_FC_OUT_MAC_SET_LINK_LEN 0\n-\n-/* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */\n-#define\tMC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4\n-#define\tMC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0\n-\n-/* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */\n-#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3)\n-#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0\n-#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8\n-#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0\n-#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4\n-#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS\n-#define\tMC_CMD_FC_MAC_RX_STATS_OCTETS  0x0 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_OCTETS_OK  0x1 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS  0x2 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES  0x3 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_FRAMES_OK  0x4 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_CRC_ERRORS  0x5 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_VLAN_OK  0x6 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_ERRORS  0x7 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_UCAST_PKTS  0x8 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_MULTICAST_PKTS  0x9 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_BROADCAST_PKTS  0xa /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_DROP_EVENTS  0xb /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_PKTS  0xc /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS  0xd /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_64  0xe /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_65_127  0xf /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_128_255  0x10 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_256_511  0x11 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_512_1023  0x12 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518  0x13 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX  0x14 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS  0x15 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_JABBERS  0x16 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_STATS_FRAGMENTS  0x17 /* enum */\n-#define\tMC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES  0x18 /* enum */\n-/* enum: (Last entry) */\n-#define\tMC_CMD_FC_MAC_RX_NSTATS  0x19\n-\n-/* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */\n-#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3)\n-#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0\n-#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8\n-#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0\n-#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4\n-#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS\n-#define\tMC_CMD_FC_MAC_TX_STATS_OCTETS  0x0 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_OCTETS_OK  0x1 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS  0x2 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES  0x3 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_FRAMES_OK  0x4 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_CRC_ERRORS  0x5 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_VLAN_OK  0x6 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_ERRORS  0x7 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_UCAST_PKTS  0x8 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_MULTICAST_PKTS  0x9 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_BROADCAST_PKTS  0xa /* enum */\n-#define\tMC_CMD_FC_MAC_TX_STATS_DROP_EVENTS  0xb /* enum */\n-#define\tMC_CMD_FC_MAC_TX_STATS_PKTS  0xc /* enum */\n-#define\tMC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS  0xd /* enum */\n-#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_64  0xe /* enum */\n-#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_65_127  0xf /* enum */\n-#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_128_255  0x10 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_256_511  0x11 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_512_1023  0x12 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518  0x13 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU  0x14 /* enum */\n-#define\tMC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES  0x15 /* enum */\n-/* enum: (Last entry) */\n-#define\tMC_CMD_FC_MAC_TX_NSTATS  0x16\n-\n-/* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */\n-#define\tMC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3)\n-/* MAC Statistics */\n-#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0\n-#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8\n-#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0\n-#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4\n-#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK\n-\n-/* MC_CMD_FC_OUT_MAC msgresponse */\n-#define\tMC_CMD_FC_OUT_MAC_LEN 0\n-\n-/* MC_CMD_FC_OUT_SFP msgresponse */\n-#define\tMC_CMD_FC_OUT_SFP_LEN 0\n-\n-/* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */\n-#define\tMC_CMD_FC_OUT_DDR_TEST_START_LEN 0\n-\n-/* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8\n-/* enum: Test not yet initiated */\n-#define\tMC_CMD_FC_OP_DDR_TEST_NONE 0x0\n-/* enum: Test is in progress */\n-#define\tMC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1\n-/* enum: Timed completed */\n-#define\tMC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2\n-/* enum: Test did not complete in specified time */\n-#define\tMC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1\n-/* Test result from FPGA */\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */\n-#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */\n-\n-/* MC_CMD_FC_OUT_DDR_TEST msgresponse */\n-#define\tMC_CMD_FC_OUT_DDR_TEST_LEN 0\n-\n-/* MC_CMD_FC_OUT_GET_ASSERT msgresponse */\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_LEN 144\n-/* Assertion status flag. */\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8\n-/* enum: No crash data available */\n-#define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0\n-/* enum: New crash data available */\n-#define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1\n-/* enum: Crash data has been sent */\n-#define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8\n-/* enum: No crash has been recorded. */\n-#define\tMC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0\n-/* enum: Crash due to exception. */\n-#define\tMC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1\n-/* enum: Crash due to assertion. */\n-#define\tMC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2\n-/* Failing PC value */\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4\n-/* Saved GP regs */\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31\n-/* Exception Type */\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132\n-/* Instruction at which exception occurred */\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136\n-/* BAD Address that triggered address-based exception */\n-#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140\n-\n-/* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_LEN 32\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4\n-/* Build timestamp (seconds since epoch) */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8\n-#define\tMC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */\n-#define\tMC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1\n-#define\tMC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */\n-#define\tMC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16\n-\n-/* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4\n-/* Build timestamp (seconds since epoch) */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4\n-#define\tMC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */\n-#define\tMC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */\n-#define\tMC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */\n-#define\tMC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */\n-#define\tMC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */\n-#define\tMC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */\n-#define\tMC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */\n-#define\tMC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1\n-/*               MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */\n-/*               MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16\n-\n-/* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_LEN 32\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4\n-/* Build timestamp (seconds since epoch) */\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16\n-\n-/* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4\n-/* Build timestamp (seconds since epoch) */\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1\n-/*               MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */\n-/*               MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0\n-#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16\n-\n-/* MC_CMD_FC_OUT_BSP_VERSION msgresponse */\n-#define\tMC_CMD_FC_OUT_BSP_VERSION_LEN 4\n-/* Qsys system ID */\n-#define\tMC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0\n-#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12\n-#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4\n-#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4\n-#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8\n-#define\tMC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0\n-#define\tMC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4\n-\n-/* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */\n-#define\tMC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4\n-/* Number of maps */\n-#define\tMC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0\n-\n-/* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164\n-/* Index of the map */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0\n-/* Options for the map */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8  0x0 /* enum */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16  0x1 /* enum */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32  0x2 /* enum */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64  0x3 /* enum */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK  0x3 /* enum */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC  0x4 /* enum */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM  0x8 /* enum */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ  0x10 /* enum */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE  0x20 /* enum */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE  0x0 /* enum */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED  0x40 /* enum */\n-/* Address of start of map */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12\n-/* Length of address map */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20\n-/* Component information field */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24\n-/* License expiry data for map */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32\n-/* Name of the component */\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1\n-#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128\n-\n-/* MC_CMD_FC_OUT_READ_MAP msgresponse */\n-#define\tMC_CMD_FC_OUT_READ_MAP_LEN 0\n-\n-/* MC_CMD_FC_OUT_CAPABILITIES msgresponse */\n-#define\tMC_CMD_FC_OUT_CAPABILITIES_LEN 8\n-/* Number of internal ports */\n-#define\tMC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0\n-/* Number of external ports */\n-#define\tMC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4\n-\n-/* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */\n-#define\tMC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4\n-#define\tMC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0\n-\n-/* MC_CMD_FC_OUT_IO_REL msgresponse */\n-#define\tMC_CMD_FC_OUT_IO_REL_LEN 0\n-\n-/* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */\n-#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8\n-#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0\n-#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4\n-\n-/* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */\n-#define\tMC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4\n-#define\tMC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252\n-#define\tMC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num))\n-#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0\n-#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4\n-#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1\n-#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63\n-\n-/* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */\n-#define\tMC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0\n-\n-/* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_LEN 48\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16\n-/* Transceiver Transmit settings */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16\n-/* Transceiver Receive settings */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16\n-/* Rx eye opening */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16\n-/* PCS status word */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16\n-/* Link status word */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1\n-/* Current SFp parameters applied */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20\n-/* Link speed is 100, 1000, 10000 */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24\n-/* Length of copper cable - zero when not relevant */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28\n-/* True if a dual speed SFP+ module */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32\n-/* True if an SFP Module is present (other fields valid when true) */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36\n-/* The type of the SFP+ Module */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40\n-/* PHY config flags */\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2\n-#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1\n-\n-/* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */\n-#define\tMC_CMD_FC_OUT_UHLINK_MAC_LEN 20\n-/* MAC configuration applied */\n-#define\tMC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0\n-/* MTU size */\n-#define\tMC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4\n-/* IF Mode status */\n-#define\tMC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8\n-/* MAC address configured */\n-#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12\n-#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8\n-#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12\n-#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16\n-\n-/* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */\n-#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)\n-/* Rx Eye measurements */\n-#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0\n-#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4\n-#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK\n-\n-/* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */\n-#define\tMC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0\n-\n-/* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */\n-#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3)\n-/* Has the eye plot dump completed and data returned is valid? */\n-#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0\n-/* Rx Eye binary plot */\n-#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4\n-#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8\n-#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4\n-#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8\n-#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK\n-\n-/* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */\n-#define\tMC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0\n-\n-/* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */\n-#define\tMC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0\n-\n-/* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */\n-#define\tMC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4\n-#define\tMC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0\n-\n-/* MC_CMD_FC_OUT_UHLINK msgresponse */\n-#define\tMC_CMD_FC_OUT_UHLINK_LEN 0\n-\n-/* MC_CMD_FC_OUT_SET_LINK msgresponse */\n-#define\tMC_CMD_FC_OUT_SET_LINK_LEN 0\n-\n-/* MC_CMD_FC_OUT_LICENSE msgresponse */\n-#define\tMC_CMD_FC_OUT_LICENSE_LEN 12\n-/* Count of valid keys */\n-#define\tMC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0\n-/* Count of invalid keys */\n-#define\tMC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4\n-/* Count of blacklisted keys */\n-#define\tMC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8\n-\n-/* MC_CMD_FC_OUT_STARTUP msgresponse */\n-#define\tMC_CMD_FC_OUT_STARTUP_LEN 4\n-/* Capabilities of the FPGA/FC */\n-#define\tMC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0\n-#define\tMC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0\n-#define\tMC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1\n-\n-/* MC_CMD_FC_OUT_DMA_READ msgresponse */\n-#define\tMC_CMD_FC_OUT_DMA_READ_LENMIN 1\n-#define\tMC_CMD_FC_OUT_DMA_READ_LENMAX 252\n-#define\tMC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num))\n-/* The data read */\n-#define\tMC_CMD_FC_OUT_DMA_READ_DATA_OFST 0\n-#define\tMC_CMD_FC_OUT_DMA_READ_DATA_LEN 1\n-#define\tMC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1\n-#define\tMC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252\n-\n-/* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_SET_LEN 4\n-/* Timer handle */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0\n-\n-/* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_LEN 52\n-/* Host supplied handle (unique) */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0\n-/* Address into which to transfer data in host */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8\n-/* AOE address from which to transfer data */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16\n-/* Length of AOE transfer (total) */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20\n-/* Length of host transfer (total) */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24\n-/* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32\n-/* When active, start read time */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40\n-/* When active, end read time */\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44\n-#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48\n-\n-/* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */\n-#define\tMC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0\n-\n-/* MC_CMD_FC_OUT_LOG msgresponse */\n-#define\tMC_CMD_FC_OUT_LOG_LEN 0\n-\n-/* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */\n-#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24\n-#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0\n-#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4\n-#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8\n-#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4\n-#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8\n-#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12\n-#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16\n-#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20\n-\n-/* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */\n-#define\tMC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0\n-\n-/* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */\n-#define\tMC_CMD_FC_OUT_DDR_SET_SPD_LEN 0\n-\n-/* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */\n-#define\tMC_CMD_FC_OUT_DDR_SET_INFO_LEN 0\n-\n-/* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */\n-#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4\n-#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0\n-#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0\n-#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1\n-#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1\n-\n-/* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4\n-\n-/* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num))\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0\n-#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31\n-\n-/* MC_CMD_FC_OUT_SPI_READ msgresponse */\n-#define\tMC_CMD_FC_OUT_SPI_READ_LENMIN 4\n-#define\tMC_CMD_FC_OUT_SPI_READ_LENMAX 252\n-#define\tMC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num))\n-#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0\n-#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4\n-#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1\n-#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63\n-\n-/* MC_CMD_FC_OUT_SPI_WRITE msgresponse */\n-#define\tMC_CMD_FC_OUT_SPI_WRITE_LEN 0\n-\n-/* MC_CMD_FC_OUT_SPI_ERASE msgresponse */\n-#define\tMC_CMD_FC_OUT_SPI_ERASE_LEN 0\n-\n-/* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */\n-#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8\n-/* The 32-bit value read from the toggle count register */\n-#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0\n-/* The 32-bit value read from the clock enable count register */\n-#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4\n-\n-/* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */\n-#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0\n-\n-/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0\n-\n-/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8\n-/* DDR soak test status word; bits [4:0] are relevant. */\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1\n-/* DDR soak test error count */\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4\n-\n-/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0\n-\n-/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */\n-#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0\n-\n-/* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */\n-#define\tMC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0\n-\n-/* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */\n-#define\tMC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0\n-\n-\n-/***********************************/\n-/* MC_CMD_AOE\n- * AOE operations on MC\n- */\n-#define\tMC_CMD_AOE 0xa\n-\n-/* MC_CMD_AOE_IN msgrequest */\n-#define\tMC_CMD_AOE_IN_LEN 4\n-#define\tMC_CMD_AOE_IN_OP_HDR_OFST 0\n-#define\tMC_CMD_AOE_IN_OP_LBN 0\n-#define\tMC_CMD_AOE_IN_OP_WIDTH 8\n-/* enum: FPGA and CPLD information */\n-#define\tMC_CMD_AOE_OP_INFO 0x1\n-/* enum: Currents and voltages read from MCP3424s; DEBUG */\n-#define\tMC_CMD_AOE_OP_CURRENTS 0x2\n-/* enum: Temperatures at locations around the PCB; DEBUG */\n-#define\tMC_CMD_AOE_OP_TEMPERATURES 0x3\n-/* enum: Set CPLD to idle */\n-#define\tMC_CMD_AOE_OP_CPLD_IDLE 0x4\n-/* enum: Read from CPLD register */\n-#define\tMC_CMD_AOE_OP_CPLD_READ 0x5\n-/* enum: Write to CPLD register */\n-#define\tMC_CMD_AOE_OP_CPLD_WRITE 0x6\n-/* enum: Execute CPLD instruction */\n-#define\tMC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7\n-/* enum: Reprogram the CPLD on the AOE device */\n-#define\tMC_CMD_AOE_OP_CPLD_REPROGRAM 0x8\n-/* enum: AOE power control */\n-#define\tMC_CMD_AOE_OP_POWER 0x9\n-/* enum: AOE image loading */\n-#define\tMC_CMD_AOE_OP_LOAD 0xa\n-/* enum: Fan monitoring */\n-#define\tMC_CMD_AOE_OP_FAN_CONTROL 0xb\n-/* enum: Fan failures since last reset */\n-#define\tMC_CMD_AOE_OP_FAN_FAILURES 0xc\n-/* enum: Get generic AOE MAC statistics */\n-#define\tMC_CMD_AOE_OP_MAC_STATS 0xd\n-/* enum: Retrieve PHY specific information */\n-#define\tMC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe\n-/* enum: Write a number of JTAG primitive commands, return will give data */\n-#define\tMC_CMD_AOE_OP_JTAG_WRITE 0xf\n-/* enum: Control access to the FPGA via the Siena JTAG Chain */\n-#define\tMC_CMD_AOE_OP_FPGA_ACCESS 0x10\n-/* enum: Set the MTU offset between Siena and AOE MACs */\n-#define\tMC_CMD_AOE_OP_SET_MTU_OFFSET 0x11\n-/* enum: How link state is handled */\n-#define\tMC_CMD_AOE_OP_LINK_STATE 0x12\n-/* enum: How Siena MAC statistics are reported (deprecated - use\n- * MC_CMD_AOE_OP_ASIC_STATS)\n- */\n-#define\tMC_CMD_AOE_OP_SIENA_STATS 0x13\n-/* enum: How native ASIC MAC statistics are reported - replaces the deprecated\n- * command MC_CMD_AOE_OP_SIENA_STATS\n- */\n-#define\tMC_CMD_AOE_OP_ASIC_STATS 0x13\n-/* enum: DDR memory information */\n-#define\tMC_CMD_AOE_OP_DDR 0x14\n-/* enum: FC control */\n-#define\tMC_CMD_AOE_OP_FC 0x15\n-/* enum: DDR ECC status reads */\n-#define\tMC_CMD_AOE_OP_DDR_ECC_STATUS 0x16\n-/* enum: Commands for MC-SPI Master emulation */\n-#define\tMC_CMD_AOE_OP_MC_SPI_MASTER 0x17\n-/* enum: Commands for FC boot control */\n-#define\tMC_CMD_AOE_OP_FC_BOOT 0x18\n-\n-/* MC_CMD_AOE_OUT msgresponse */\n-#define\tMC_CMD_AOE_OUT_LEN 0\n-\n-/* MC_CMD_AOE_IN_INFO msgrequest */\n-#define\tMC_CMD_AOE_IN_INFO_LEN 4\n-#define\tMC_CMD_AOE_IN_CMD_OFST 0\n-\n-/* MC_CMD_AOE_IN_CURRENTS msgrequest */\n-#define\tMC_CMD_AOE_IN_CURRENTS_LEN 4\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-\n-/* MC_CMD_AOE_IN_TEMPERATURES msgrequest */\n-#define\tMC_CMD_AOE_IN_TEMPERATURES_LEN 4\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-\n-/* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */\n-#define\tMC_CMD_AOE_IN_CPLD_IDLE_LEN 4\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-\n-/* MC_CMD_AOE_IN_CPLD_READ msgrequest */\n-#define\tMC_CMD_AOE_IN_CPLD_READ_LEN 12\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-#define\tMC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4\n-#define\tMC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8\n-\n-/* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */\n-#define\tMC_CMD_AOE_IN_CPLD_WRITE_LEN 16\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-#define\tMC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4\n-#define\tMC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8\n-#define\tMC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12\n-\n-/* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */\n-#define\tMC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-#define\tMC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4\n-\n-/* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */\n-#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4\n-/* enum: Reprogram CPLD, poll for completion */\n-#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1\n-/* enum: Reprogram CPLD, send event on completion */\n-#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3\n-/* enum: Get status of reprogramming operation */\n-#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4\n-\n-/* MC_CMD_AOE_IN_POWER msgrequest */\n-#define\tMC_CMD_AOE_IN_POWER_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* Turn on or off AOE power */\n-#define\tMC_CMD_AOE_IN_POWER_OP_OFST 4\n-/* enum: Turn off FPGA power */\n-#define\tMC_CMD_AOE_IN_POWER_OFF  0x0\n-/* enum: Turn on FPGA power */\n-#define\tMC_CMD_AOE_IN_POWER_ON  0x1\n-/* enum: Clear peak power measurement */\n-#define\tMC_CMD_AOE_IN_POWER_CLEAR  0x2\n-/* enum: Show current power in sensors output */\n-#define\tMC_CMD_AOE_IN_POWER_SHOW_CURRENT  0x3\n-/* enum: Show peak power in sensors output */\n-#define\tMC_CMD_AOE_IN_POWER_SHOW_PEAK  0x4\n-/* enum: Show current DDR current */\n-#define\tMC_CMD_AOE_IN_POWER_DDR_LAST  0x5\n-/* enum: Show peak DDR current */\n-#define\tMC_CMD_AOE_IN_POWER_DDR_PEAK  0x6\n-/* enum: Clear peak DDR current */\n-#define\tMC_CMD_AOE_IN_POWER_DDR_CLEAR  0x7\n-\n-/* MC_CMD_AOE_IN_LOAD msgrequest */\n-#define\tMC_CMD_AOE_IN_LOAD_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence\n- */\n-#define\tMC_CMD_AOE_IN_LOAD_IMAGE_OFST 4\n-\n-/* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */\n-#define\tMC_CMD_AOE_IN_FAN_CONTROL_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* If non zero report measured fan RPM rather than nominal */\n-#define\tMC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4\n-\n-/* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */\n-#define\tMC_CMD_AOE_IN_FAN_FAILURES_LEN 4\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-\n-/* MC_CMD_AOE_IN_MAC_STATS msgrequest */\n-#define\tMC_CMD_AOE_IN_MAC_STATS_LEN 24\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* AOE port */\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4\n-/* Host memory address for statistics */\n-#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8\n-#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8\n-#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8\n-#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12\n-#define\tMC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16\n-#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0\n-#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1\n-#define\tMC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1\n-#define\tMC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16\n-#define\tMC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16\n-/* Length of DMA data (optional) */\n-#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20\n-\n-/* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */\n-#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* AOE port */\n-#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4\n-#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8\n-\n-/* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */\n-#define\tMC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12\n-#define\tMC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252\n-#define\tMC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num))\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4\n-#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8\n-#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4\n-#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1\n-#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61\n-\n-/* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */\n-#define\tMC_CMD_AOE_IN_FPGA_ACCESS_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* Enable or disable access */\n-#define\tMC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4\n-/* enum: Enable access */\n-#define\tMC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1\n-/* enum: Disable access */\n-#define\tMC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2\n-\n-/* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */\n-#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */\n-#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4\n-/* enum: Apply to all external ports */\n-#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000\n-/* enum: Apply to all internal ports */\n-#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000\n-/* The MTU offset to be applied to the external ports */\n-#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8\n-\n-/* MC_CMD_AOE_IN_LINK_STATE msgrequest */\n-#define\tMC_CMD_AOE_IN_LINK_STATE_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-#define\tMC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4\n-#define\tMC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0\n-#define\tMC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8\n-/* enum: AOE and associated external port */\n-#define\tMC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE  0x0\n-/* enum: AOE and OR of all external ports */\n-#define\tMC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED  0x1\n-/* enum: Individual ports */\n-#define\tMC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC  0x2\n-/* enum: Configure link state mode on given AOE port */\n-#define\tMC_CMD_AOE_IN_LINK_STATE_CUSTOM  0x3\n-#define\tMC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8\n-#define\tMC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8\n-/* enum: No-op */\n-#define\tMC_CMD_AOE_IN_LINK_STATE_OP_NONE  0x0\n-/* enum: logical OR of all SFP ports link status */\n-#define\tMC_CMD_AOE_IN_LINK_STATE_OP_OR  0x1\n-/* enum: logical AND of all SFP ports link status */\n-#define\tMC_CMD_AOE_IN_LINK_STATE_OP_AND  0x2\n-#define\tMC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16\n-#define\tMC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16\n-\n-/* MC_CMD_AOE_IN_SIENA_STATS msgrequest */\n-#define\tMC_CMD_AOE_IN_SIENA_STATS_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* How MAC statistics are reported */\n-#define\tMC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4\n-/* enum: Statistics from Siena (default) */\n-#define\tMC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA  0x0\n-/* enum: Statistics from AOE external ports */\n-#define\tMC_CMD_AOE_IN_SIENA_STATS_STATS_AOE  0x1\n-\n-/* MC_CMD_AOE_IN_ASIC_STATS msgrequest */\n-#define\tMC_CMD_AOE_IN_ASIC_STATS_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* How MAC statistics are reported */\n-#define\tMC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4\n-/* enum: Statistics from the ASIC (default) */\n-#define\tMC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC  0x0\n-/* enum: Statistics from AOE external ports */\n-#define\tMC_CMD_AOE_IN_ASIC_STATS_STATS_AOE  0x1\n-\n-/* MC_CMD_AOE_IN_DDR msgrequest */\n-#define\tMC_CMD_AOE_IN_DDR_LEN 12\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-#define\tMC_CMD_AOE_IN_DDR_BANK_OFST 4\n-/*            Enum values, see field(s): */\n-/*               MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */\n-/* Page index of SPD data */\n-#define\tMC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8\n-\n-/* MC_CMD_AOE_IN_FC msgrequest */\n-#define\tMC_CMD_AOE_IN_FC_LEN 4\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-\n-/* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */\n-#define\tMC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-#define\tMC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4\n-/*            Enum values, see field(s): */\n-/*               MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */\n-\n-/* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* Basic commands for MC SPI Master emulation. */\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4\n-/* enum: MC SPI read */\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0\n-/* enum: MC SPI write */\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1\n-\n-/* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8\n-\n-/* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8\n-#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12\n-\n-/* MC_CMD_AOE_IN_FC_BOOT msgrequest */\n-#define\tMC_CMD_AOE_IN_FC_BOOT_LEN 8\n-/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n-/* FC boot control flags */\n-#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4\n-#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0\n-#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1\n-\n-/* MC_CMD_AOE_OUT_INFO msgresponse */\n-#define\tMC_CMD_AOE_OUT_INFO_LEN 44\n-/* JTAG IDCODE of CPLD */\n-#define\tMC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0\n-/* Version of CPLD */\n-#define\tMC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4\n-/* JTAG IDCODE of FPGA */\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8\n-/* JTAG USERCODE of FPGA */\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12\n-/* FPGA type - read from CPLD straps */\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2   0x1 /* enum */\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2   0x2 /* enum */\n-/* FPGA state (debug) */\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20\n-/* FPGA image - partition from which loaded */\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24\n-/* FC state */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28\n-/* enum: Set if watchdog working */\n-#define\tMC_CMD_AOE_OUT_INFO_WATCHDOG 0x1\n-/* enum: Set if MC-FC communications working */\n-#define\tMC_CMD_AOE_OUT_INFO_COMMS 0x2\n-/* Random pieces of information */\n-#define\tMC_CMD_AOE_OUT_INFO_FLAGS_OFST 32\n-/* enum: Power to FPGA supplied by PEG connector, not PCIe bus */\n-#define\tMC_CMD_AOE_OUT_INFO_PEG_POWER            0x1\n-/* enum: CPLD apparently good */\n-#define\tMC_CMD_AOE_OUT_INFO_CPLD_GOOD            0x2\n-/* enum: FPGA working normally */\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_GOOD            0x4\n-/* enum: FPGA is powered */\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_POWER           0x8\n-/* enum: Board has incompatible SODIMMs fitted */\n-#define\tMC_CMD_AOE_OUT_INFO_BAD_SODIMM           0x10\n-/* enum: Board has ByteBlaster connected */\n-#define\tMC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER      0x20\n-/* enum: FPGA Boot flash has an invalid header. */\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR    0x40\n-/* enum: FPGA Application flash is accessible. */\n-#define\tMC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD  0x80\n-/* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */\n-#define\tMC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36\n-#define\tMC_CMD_AOE_OUT_INFO_UNKNOWN  0x0 /* enum */\n-#define\tMC_CMD_AOE_OUT_INFO_R1_0  0x10 /* enum */\n-#define\tMC_CMD_AOE_OUT_INFO_R1_1  0x11 /* enum */\n-#define\tMC_CMD_AOE_OUT_INFO_R1_2  0x12 /* enum */\n-#define\tMC_CMD_AOE_OUT_INFO_R1_3  0x13 /* enum */\n-/* Result of FC booting - not valid while a ByteBlaster is connected. */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40\n-/* enum: No error */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0\n-/* enum: Bad address set in CPLD */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1\n-/* enum: Bad header */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2\n-/* enum: Bad text section details */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3\n-/* enum: Bad checksum */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4\n-/* enum: Bad BSP */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5\n-/* enum: Flash mode is invalid */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6\n-/* enum: FC application loaded and execution attempted */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80\n-/* enum: FC application Started */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81\n-/* enum: No bootrom in FPGA */\n-#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff\n-\n-/* MC_CMD_AOE_OUT_CURRENTS msgresponse */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_LEN 68\n-/* Set of currents and voltages (mA or mV as appropriate) */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0\n-#define\tMC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4\n-#define\tMC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */\n-#define\tMC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */\n-\n-/* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_LEN 40\n-/* Set of temperatures */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10\n-/* enum: The first set of enum values are for Modena code. */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */\n-/* enum: The second set of enum values are for Sorrento code. */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */\n-#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */\n-\n-/* MC_CMD_AOE_OUT_CPLD_READ msgresponse */\n-#define\tMC_CMD_AOE_OUT_CPLD_READ_LEN 4\n-/* The value read from the CPLD */\n-#define\tMC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0\n-\n-/* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */\n-#define\tMC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4\n-#define\tMC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252\n-#define\tMC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num))\n-/* Failure counts for each fan */\n-#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0\n-#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4\n-#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1\n-#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63\n-\n-/* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */\n-#define\tMC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4\n-/* Results of status command (only) */\n-#define\tMC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0\n-\n-/* MC_CMD_AOE_OUT_POWER_OFF msgresponse */\n-#define\tMC_CMD_AOE_OUT_POWER_OFF_LEN 0\n-\n-/* MC_CMD_AOE_OUT_POWER_ON msgresponse */\n-#define\tMC_CMD_AOE_OUT_POWER_ON_LEN 0\n-\n-/* MC_CMD_AOE_OUT_LOAD msgresponse */\n-#define\tMC_CMD_AOE_OUT_LOAD_LEN 0\n-\n-/* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */\n-#define\tMC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0\n-\n-/* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA\n- * for details\n- */\n-#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)\n-#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0\n-#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8\n-#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0\n-#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4\n-#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS\n-\n-/* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */\n-#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5\n-#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252\n-#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num))\n-/* in bytes */\n-#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0\n-#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4\n-#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1\n-#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1\n-#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248\n-\n-/* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */\n-#define\tMC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12\n-#define\tMC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252\n-#define\tMC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num))\n-/* Used to align the in and out data blocks so the MC can re-use the cmd */\n-#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0\n-/* out bytes */\n-#define\tMC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4\n-#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8\n-#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4\n-#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1\n-#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61\n-\n-/* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */\n-#define\tMC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0\n-\n-/* MC_CMD_AOE_OUT_DDR msgresponse */\n-#define\tMC_CMD_AOE_OUT_DDR_LENMIN 17\n-#define\tMC_CMD_AOE_OUT_DDR_LENMAX 252\n-#define\tMC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num))\n-/* Information on the module. */\n-#define\tMC_CMD_AOE_OUT_DDR_FLAGS_OFST 0\n-#define\tMC_CMD_AOE_OUT_DDR_PRESENT_LBN 0\n-#define\tMC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1\n-#define\tMC_CMD_AOE_OUT_DDR_POWERED_LBN 1\n-#define\tMC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1\n-#define\tMC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2\n-#define\tMC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1\n-#define\tMC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3\n-#define\tMC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1\n-/* Memory size, in MB. */\n-#define\tMC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4\n-/* The memory type, as reported from SPD information */\n-#define\tMC_CMD_AOE_OUT_DDR_TYPE_OFST 8\n-/* Nominal voltage of the module (as applied) */\n-#define\tMC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12\n-/* SPD data read from the module */\n-#define\tMC_CMD_AOE_OUT_DDR_SPD_OFST 16\n-#define\tMC_CMD_AOE_OUT_DDR_SPD_LEN 1\n-#define\tMC_CMD_AOE_OUT_DDR_SPD_MINNUM 1\n-#define\tMC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236\n-\n-/* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */\n-#define\tMC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0\n-\n-/* MC_CMD_AOE_OUT_LINK_STATE msgresponse */\n-#define\tMC_CMD_AOE_OUT_LINK_STATE_LEN 0\n-\n-/* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */\n-#define\tMC_CMD_AOE_OUT_SIENA_STATS_LEN 0\n-\n-/* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */\n-#define\tMC_CMD_AOE_OUT_ASIC_STATS_LEN 0\n-\n-/* MC_CMD_AOE_OUT_FC msgresponse */\n-#define\tMC_CMD_AOE_OUT_FC_LEN 0\n-\n-/* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8\n-/* Flags describing status info on the module. */\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1\n-/* DDR ECC status on the module. */\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24\n-#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8\n-\n-/* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */\n-#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4\n-#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0\n-\n-/* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */\n-#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0\n-\n-/* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */\n-#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0\n-\n-/* MC_CMD_AOE_OUT_FC_BOOT msgresponse */\n-#define\tMC_CMD_AOE_OUT_FC_BOOT_LEN 0\n-\n-\n-/***********************************/\n /* MC_CMD_PTP\n  * Perform PTP operation\n  */\n@@ -3616,41 +1330,54 @@\n #define\tMC_CMD_PTP_OP_ENABLE 0x1\n /* enum: Disable PTP packet timestamping operation. */\n #define\tMC_CMD_PTP_OP_DISABLE 0x2\n-/* enum: Send a PTP packet. */\n+/* enum: Send a PTP packet. This operation is used on Siena and Huntington.\n+ * From Medford onwards it is not supported: on those platforms PTP transmit\n+ * timestamping is done using the fast path.\n+ */\n #define\tMC_CMD_PTP_OP_TRANSMIT 0x3\n /* enum: Read the current NIC time. */\n #define\tMC_CMD_PTP_OP_READ_NIC_TIME 0x4\n-/* enum: Get the current PTP status. */\n+/* enum: Get the current PTP status. Note that the clock frequency returned (in\n+ * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).\n+ */\n #define\tMC_CMD_PTP_OP_STATUS 0x5\n /* enum: Adjust the PTP NIC's time. */\n #define\tMC_CMD_PTP_OP_ADJUST 0x6\n /* enum: Synchronize host and NIC time. */\n #define\tMC_CMD_PTP_OP_SYNCHRONIZE 0x7\n-/* enum: Basic manufacturing tests. */\n+/* enum: Basic manufacturing tests. Siena PTP adapters only. */\n #define\tMC_CMD_PTP_OP_MANFTEST_BASIC 0x8\n-/* enum: Packet based manufacturing tests. */\n+/* enum: Packet based manufacturing tests. Siena PTP adapters only. */\n #define\tMC_CMD_PTP_OP_MANFTEST_PACKET 0x9\n /* enum: Reset some of the PTP related statistics */\n #define\tMC_CMD_PTP_OP_RESET_STATS 0xa\n /* enum: Debug operations to MC. */\n #define\tMC_CMD_PTP_OP_DEBUG 0xb\n-/* enum: Read an FPGA register */\n+/* enum: Read an FPGA register. Siena PTP adapters only. */\n #define\tMC_CMD_PTP_OP_FPGAREAD 0xc\n-/* enum: Write an FPGA register */\n+/* enum: Write an FPGA register. Siena PTP adapters only. */\n #define\tMC_CMD_PTP_OP_FPGAWRITE 0xd\n /* enum: Apply an offset to the NIC clock */\n #define\tMC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe\n-/* enum: Change Apply an offset to the NIC clock */\n+/* enum: Change the frequency correction applied to the NIC clock */\n #define\tMC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf\n-/* enum: Set the MC packet filter VLAN tags for received PTP packets */\n+/* enum: Set the MC packet filter VLAN tags for received PTP packets.\n+ * Deprecated for Huntington onwards.\n+ */\n #define\tMC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10\n-/* enum: Set the MC packet filter UUID for received PTP packets */\n+/* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for\n+ * Huntington onwards.\n+ */\n #define\tMC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11\n-/* enum: Set the MC packet filter Domain for received PTP packets */\n+/* enum: Set the MC packet filter Domain for received PTP packets. Deprecated\n+ * for Huntington onwards.\n+ */\n #define\tMC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12\n-/* enum: Set the clock source */\n+/* enum: Set the clock source. Required for snapper tests on Huntington and\n+ * Medford. Not implemented for Siena or Medford2.\n+ */\n #define\tMC_CMD_PTP_OP_SET_CLK_SRC 0x13\n-/* enum: Reset value of Timer Reg. */\n+/* enum: Reset value of Timer Reg. Not implemented. */\n #define\tMC_CMD_PTP_OP_RST_CLK 0x14\n /* enum: Enable the forwarding of PPS events to the host */\n #define\tMC_CMD_PTP_OP_PPS_ENABLE 0x15\n@@ -3671,7 +1398,7 @@\n /* enum: Unsubscribe to stop receiving time events */\n #define\tMC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19\n /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS\n- * input on the same NIC.\n+ * input on the same NIC. Siena PTP adapters only.\n  */\n #define\tMC_CMD_PTP_OP_MANFTEST_PPS 0x1a\n /* enum: Set the PTP sync status. Status is used by firmware to report to event\n@@ -3684,11 +1411,15 @@\n /* MC_CMD_PTP_IN_ENABLE msgrequest */\n #define\tMC_CMD_PTP_IN_ENABLE_LEN 16\n #define\tMC_CMD_PTP_IN_CMD_OFST 0\n+#define\tMC_CMD_PTP_IN_CMD_LEN 4\n #define\tMC_CMD_PTP_IN_PERIPH_ID_OFST 4\n-/* Event queue for PTP events */\n+#define\tMC_CMD_PTP_IN_PERIPH_ID_LEN 4\n+/* Not used. Events are always sent to function relative queue 0. */\n #define\tMC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8\n-/* PTP timestamping mode */\n+#define\tMC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4\n+/* PTP timestamping mode. Not used from Huntington onwards. */\n #define\tMC_CMD_PTP_IN_ENABLE_MODE_OFST 12\n+#define\tMC_CMD_PTP_IN_ENABLE_MODE_LEN 4\n /* enum: PTP, version 1 */\n #define\tMC_CMD_PTP_MODE_V1 0x0\n /* enum: PTP, version 1, with VLAN headers - deprecated */\n@@ -3705,16 +1436,21 @@\n /* MC_CMD_PTP_IN_DISABLE msgrequest */\n #define\tMC_CMD_PTP_IN_DISABLE_LEN 8\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n \n /* MC_CMD_PTP_IN_TRANSMIT msgrequest */\n #define\tMC_CMD_PTP_IN_TRANSMIT_LENMIN 13\n #define\tMC_CMD_PTP_IN_TRANSMIT_LENMAX 252\n #define\tMC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Transmit packet length */\n #define\tMC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8\n+#define\tMC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4\n /* Transmit packet data */\n #define\tMC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12\n #define\tMC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1\n@@ -3724,17 +1460,30 @@\n /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */\n #define\tMC_CMD_PTP_IN_READ_NIC_TIME_LEN 8\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n+\n+/* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */\n+#define\tMC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n \n /* MC_CMD_PTP_IN_STATUS msgrequest */\n #define\tMC_CMD_PTP_IN_STATUS_LEN 8\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n \n /* MC_CMD_PTP_IN_ADJUST msgrequest */\n #define\tMC_CMD_PTP_IN_ADJUST_LEN 24\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Frequency adjustment 40 bit fixed point ns */\n #define\tMC_CMD_PTP_IN_ADJUST_FREQ_OFST 8\n #define\tMC_CMD_PTP_IN_ADJUST_FREQ_LEN 8\n@@ -3742,21 +1491,67 @@\n #define\tMC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12\n /* enum: Number of fractional bits in frequency adjustment */\n #define\tMC_CMD_PTP_IN_ADJUST_BITS 0x28\n+/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ\n+ * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES\n+ * field.\n+ */\n+#define\tMC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c\n /* Time adjustment in seconds */\n #define\tMC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16\n+#define\tMC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4\n /* Time adjustment major value */\n #define\tMC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16\n+#define\tMC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4\n /* Time adjustment in nanoseconds */\n #define\tMC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20\n+#define\tMC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4\n /* Time adjustment minor value */\n #define\tMC_CMD_PTP_IN_ADJUST_MINOR_OFST 20\n+#define\tMC_CMD_PTP_IN_ADJUST_MINOR_LEN 4\n+\n+/* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_LEN 28\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n+/* Frequency adjustment 40 bit fixed point ns */\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12\n+/* enum: Number of fractional bits in frequency adjustment */\n+/*               MC_CMD_PTP_IN_ADJUST_BITS 0x28 */\n+/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ\n+ * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES\n+ * field.\n+ */\n+/*               MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */\n+/* Time adjustment in seconds */\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4\n+/* Time adjustment major value */\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4\n+/* Time adjustment in nanoseconds */\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4\n+/* Time adjustment minor value */\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4\n+/* Upper 32bits of major time offset adjustment */\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4\n \n /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */\n #define\tMC_CMD_PTP_IN_SYNCHRONIZE_LEN 20\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Number of time readings to capture */\n #define\tMC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4\n /* Host address in which to write \"synchronization started\" indication (64\n  * bits)\n  */\n@@ -3768,42 +1563,59 @@\n /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */\n #define\tMC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n \n /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */\n #define\tMC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Enable or disable packet testing */\n #define\tMC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8\n+#define\tMC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4\n \n /* MC_CMD_PTP_IN_RESET_STATS msgrequest */\n #define\tMC_CMD_PTP_IN_RESET_STATS_LEN 8\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /* Reset PTP statistics */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n \n /* MC_CMD_PTP_IN_DEBUG msgrequest */\n #define\tMC_CMD_PTP_IN_DEBUG_LEN 12\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Debug operations */\n #define\tMC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8\n+#define\tMC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4\n \n /* MC_CMD_PTP_IN_FPGAREAD msgrequest */\n #define\tMC_CMD_PTP_IN_FPGAREAD_LEN 16\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n #define\tMC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8\n+#define\tMC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4\n #define\tMC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12\n+#define\tMC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4\n \n /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */\n #define\tMC_CMD_PTP_IN_FPGAWRITE_LENMIN 13\n #define\tMC_CMD_PTP_IN_FPGAWRITE_LENMAX 252\n #define\tMC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n #define\tMC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8\n+#define\tMC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4\n #define\tMC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12\n #define\tMC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1\n #define\tMC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1\n@@ -3812,34 +1624,67 @@\n /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */\n #define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Time adjustment in seconds */\n #define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4\n /* Time adjustment major value */\n #define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4\n /* Time adjustment in nanoseconds */\n #define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4\n /* Time adjustment minor value */\n #define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4\n+\n+/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20\n+/*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n+/* Time adjustment in seconds */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4\n+/* Time adjustment major value */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4\n+/* Time adjustment in nanoseconds */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4\n+/* Time adjustment minor value */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4\n+/* Upper 32bits of major time offset adjustment */\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16\n+#define\tMC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4\n \n /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */\n #define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Frequency adjustment 40 bit fixed point ns */\n #define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8\n #define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8\n #define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8\n #define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12\n-/* enum: Number of fractional bits in frequency adjustment */\n-/*               MC_CMD_PTP_IN_ADJUST_BITS 0x28 */\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */\n \n /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */\n #define\tMC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Number of VLAN tags, 0 if not VLAN */\n #define\tMC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8\n+#define\tMC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4\n /* Set of VLAN tags to filter against */\n #define\tMC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12\n #define\tMC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4\n@@ -3848,9 +1693,12 @@\n /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */\n #define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* 1 to enable UUID filtering, 0 to disable */\n #define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4\n /* UUID to filter against */\n #define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12\n #define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8\n@@ -3860,18 +1708,25 @@\n /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */\n #define\tMC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* 1 to enable Domain filtering, 0 to disable */\n #define\tMC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8\n+#define\tMC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4\n /* Domain number to filter against */\n #define\tMC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12\n+#define\tMC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4\n \n /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */\n #define\tMC_CMD_PTP_IN_SET_CLK_SRC_LEN 12\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Set the clock source. */\n #define\tMC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8\n+#define\tMC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4\n /* enum: Internal. */\n #define\tMC_CMD_PTP_CLK_SRC_INTERNAL 0x0\n /* enum: External. */\n@@ -3880,42 +1735,56 @@\n /* MC_CMD_PTP_IN_RST_CLK msgrequest */\n #define\tMC_CMD_PTP_IN_RST_CLK_LEN 8\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /* Reset value of Timer Reg. */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n \n /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */\n #define\tMC_CMD_PTP_IN_PPS_ENABLE_LEN 12\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /* Enable or disable */\n #define\tMC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4\n+#define\tMC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4\n /* enum: Enable */\n #define\tMC_CMD_PTP_ENABLE_PPS 0x0\n /* enum: Disable */\n #define\tMC_CMD_PTP_DISABLE_PPS 0x1\n-/* Queue id to send events back */\n+/* Not used. Events are always sent to function relative queue 0. */\n #define\tMC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8\n+#define\tMC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4\n \n /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */\n #define\tMC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n \n /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */\n #define\tMC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n \n /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */\n #define\tMC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n \n /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Original field containing queue ID. Now extended to include flags. */\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31\n@@ -3924,29 +1793,39 @@\n /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */\n #define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* Unsubscribe options */\n #define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4\n /* enum: Unsubscribe a single queue */\n #define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0\n /* enum: Unsubscribe all queues */\n #define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1\n /* Event queue ID */\n #define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4\n \n /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */\n #define\tMC_CMD_PTP_IN_MANFTEST_PPS_LEN 12\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* 1 to enable PPS test mode, 0 to disable and return result. */\n #define\tMC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8\n+#define\tMC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4\n \n /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */\n #define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24\n /*            MC_CMD_PTP_IN_CMD_OFST 0 */\n+/*            MC_CMD_PTP_IN_CMD_LEN 4 */\n /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */\n+/*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */\n /* NIC - Host System Clock Synchronization status */\n #define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4\n /* enum: Host System clock and NIC clock are not in sync */\n #define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0\n /* enum: Host System clock and NIC clock are synchronized */\n@@ -3955,8 +1834,11 @@\n  * no longer in sync.\n  */\n #define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4\n #define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4\n #define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20\n+#define\tMC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4\n \n /* MC_CMD_PTP_OUT msgresponse */\n #define\tMC_CMD_PTP_OUT_LEN 0\n@@ -3965,12 +1847,16 @@\n #define\tMC_CMD_PTP_OUT_TRANSMIT_LEN 8\n /* Value of seconds timestamp */\n #define\tMC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0\n+#define\tMC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4\n /* Timestamp major value */\n #define\tMC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0\n+#define\tMC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4\n /* Value of nanoseconds timestamp */\n #define\tMC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4\n+#define\tMC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4\n /* Timestamp minor value */\n #define\tMC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4\n+#define\tMC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4\n \n /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */\n #define\tMC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0\n@@ -3982,47 +1868,85 @@\n #define\tMC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8\n /* Value of seconds timestamp */\n #define\tMC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4\n /* Timestamp major value */\n #define\tMC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4\n /* Value of nanoseconds timestamp */\n #define\tMC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4\n /* Timestamp minor value */\n #define\tMC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4\n+\n+/* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12\n+/* Value of seconds timestamp */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4\n+/* Timestamp major value */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4\n+/* Value of nanoseconds timestamp */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4\n+/* Timestamp minor value */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4\n+/* Upper 32bits of major timestamp value */\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8\n+#define\tMC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4\n \n /* MC_CMD_PTP_OUT_STATUS msgresponse */\n #define\tMC_CMD_PTP_OUT_STATUS_LEN 64\n /* Frequency of NIC's hardware clock */\n #define\tMC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0\n+#define\tMC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4\n /* Number of packets transmitted and timestamped */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4\n /* Number of packets received and timestamped */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4\n /* Number of packets timestamped by the FPGA */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4\n /* Number of packets filter matched */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4\n /* Number of packets not filter matched */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4\n /* Number of PPS overflows (noise on input?) */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4\n /* Number of PPS bad periods */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4\n /* Minimum period of PPS pulse in nanoseconds */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4\n /* Maximum period of PPS pulse in nanoseconds */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4\n /* Last period of PPS pulse in nanoseconds */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4\n /* Mean period of PPS pulse in nanoseconds */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4\n /* Minimum offset of PPS pulse in nanoseconds (signed) */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4\n /* Maximum offset of PPS pulse in nanoseconds (signed) */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4\n /* Last offset of PPS pulse in nanoseconds (signed) */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4\n /* Mean offset of PPS pulse in nanoseconds (signed) */\n #define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60\n+#define\tMC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4\n \n /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */\n #define\tMC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20\n@@ -4035,23 +1959,31 @@\n #define\tMC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12\n /* Host time immediately before NIC's hardware clock read */\n #define\tMC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4\n /* Value of seconds timestamp */\n #define\tMC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4\n /* Timestamp major value */\n #define\tMC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4\n /* Value of nanoseconds timestamp */\n #define\tMC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4\n /* Timestamp minor value */\n #define\tMC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4\n /* Host time immediately after NIC's hardware clock read */\n #define\tMC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4\n /* Number of nanoseconds waited after reading NIC's hardware clock */\n #define\tMC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16\n+#define\tMC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4\n \n /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */\n #define\tMC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8\n /* Results of testing */\n #define\tMC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0\n+#define\tMC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4\n /* enum: Successful test */\n #define\tMC_CMD_PTP_MANF_SUCCESS 0x0\n /* enum: FPGA load failed */\n@@ -4084,15 +2016,19 @@\n #define\tMC_CMD_PTP_MANF_CLOCK_READ 0xe\n /* Presence of external oscillator */\n #define\tMC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4\n+#define\tMC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4\n \n /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */\n #define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12\n /* Results of testing */\n #define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0\n+#define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4\n /* Number of packets received by FPGA */\n #define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4\n+#define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4\n /* Number of packets received by Siena filters */\n #define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8\n+#define\tMC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4\n \n /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */\n #define\tMC_CMD_PTP_OUT_FPGAREAD_LENMIN 1\n@@ -4108,9 +2044,11 @@\n /* Time format required/used by for this NIC. Applies to all PTP MCDI\n  * operations that pass times between the host and firmware. If this operation\n  * is not supported (older firmware) a format of seconds and nanoseconds should\n- * be assumed.\n+ * be assumed. Note this enum is deprecated. Do not add to it- use the\n+ * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.\n  */\n #define\tMC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0\n+#define\tMC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4\n /* enum: Times are in seconds and nanoseconds */\n #define\tMC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0\n /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */\n@@ -4126,12 +2064,16 @@\n  * be assumed.\n  */\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4\n /* enum: Times are in seconds and nanoseconds */\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0\n /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1\n /* enum: Major register has units of seconds, minor 2^-27s per tick */\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2\n+/* enum: Major register units are seconds, minor units are quarter nanoseconds\n+ */\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3\n /* Minimum acceptable value for a corrected synchronization timeset. When\n  * comparing host and NIC clock times, the MC returns a set of samples that\n  * contain the host start and end time, the MC time when the host start was\n@@ -4140,46 +2082,66 @@\n  * end and start times minus the time that the MC waited for host end.\n  */\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4\n /* Various PTP capabilities */\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4\n \n /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16\n /* Uncorrected error on PTP transmit timestamps in NIC clock format */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4\n /* Uncorrected error on PTP receive timestamps in NIC clock format */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4\n /* Uncorrected error on PPS output in NIC clock format */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4\n /* Uncorrected error on PPS input in NIC clock format */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4\n \n /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24\n /* Uncorrected error on PTP transmit timestamps in NIC clock format */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4\n /* Uncorrected error on PTP receive timestamps in NIC clock format */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4\n /* Uncorrected error on PPS output in NIC clock format */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4\n /* Uncorrected error on PPS input in NIC clock format */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4\n /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4\n /* Uncorrected error on non-PTP receive timestamps in NIC clock format */\n #define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20\n+#define\tMC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4\n \n /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */\n #define\tMC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4\n /* Results of testing */\n #define\tMC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0\n+#define\tMC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */\n \n@@ -4194,14 +2156,17 @@\n #define\tMC_CMD_CSR_READ32 0xc\n #undef\tMC_CMD_0xc_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_CSR_READ32_IN msgrequest */\n #define\tMC_CMD_CSR_READ32_IN_LEN 12\n /* Address */\n #define\tMC_CMD_CSR_READ32_IN_ADDR_OFST 0\n+#define\tMC_CMD_CSR_READ32_IN_ADDR_LEN 4\n #define\tMC_CMD_CSR_READ32_IN_STEP_OFST 4\n+#define\tMC_CMD_CSR_READ32_IN_STEP_LEN 4\n #define\tMC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8\n+#define\tMC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4\n \n /* MC_CMD_CSR_READ32_OUT msgresponse */\n #define\tMC_CMD_CSR_READ32_OUT_LENMIN 4\n@@ -4221,7 +2186,7 @@\n #define\tMC_CMD_CSR_WRITE32 0xd\n #undef\tMC_CMD_0xd_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_CSR_WRITE32_IN msgrequest */\n #define\tMC_CMD_CSR_WRITE32_IN_LENMIN 12\n@@ -4229,7 +2194,9 @@\n #define\tMC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))\n /* Address */\n #define\tMC_CMD_CSR_WRITE32_IN_ADDR_OFST 0\n+#define\tMC_CMD_CSR_WRITE32_IN_ADDR_LEN 4\n #define\tMC_CMD_CSR_WRITE32_IN_STEP_OFST 4\n+#define\tMC_CMD_CSR_WRITE32_IN_STEP_LEN 4\n #define\tMC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8\n #define\tMC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4\n #define\tMC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1\n@@ -4238,6 +2205,7 @@\n /* MC_CMD_CSR_WRITE32_OUT msgresponse */\n #define\tMC_CMD_CSR_WRITE32_OUT_LEN 4\n #define\tMC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0\n+#define\tMC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4\n \n \n /***********************************/\n@@ -4259,6 +2227,7 @@\n  * sensors.\n  */\n #define\tMC_CMD_HP_IN_SUBCMD_OFST 0\n+#define\tMC_CMD_HP_IN_SUBCMD_LEN 4\n /* enum: OCSD (Option Card Sensor Data) sub-command. */\n #define\tMC_CMD_HP_IN_OCSD_SUBCMD 0x0\n /* enum: Last known valid HP sub-command. */\n@@ -4273,10 +2242,12 @@\n  * NULL.)\n  */\n #define\tMC_CMD_HP_IN_OCSD_INTERVAL_OFST 12\n+#define\tMC_CMD_HP_IN_OCSD_INTERVAL_LEN 4\n \n /* MC_CMD_HP_OUT msgresponse */\n #define\tMC_CMD_HP_OUT_LEN 4\n #define\tMC_CMD_HP_OUT_OCSD_STATUS_OFST 0\n+#define\tMC_CMD_HP_OUT_OCSD_STATUS_LEN 4\n /* enum: OCSD stopped for this card. */\n #define\tMC_CMD_HP_OUT_OCSD_STOPPED 0x1\n /* enum: OCSD was successfully started with the address provided. */\n@@ -4323,29 +2294,35 @@\n  * external devices.\n  */\n #define\tMC_CMD_MDIO_READ_IN_BUS_OFST 0\n+#define\tMC_CMD_MDIO_READ_IN_BUS_LEN 4\n /* enum: Internal. */\n #define\tMC_CMD_MDIO_BUS_INTERNAL 0x0\n /* enum: External. */\n #define\tMC_CMD_MDIO_BUS_EXTERNAL 0x1\n /* Port address */\n #define\tMC_CMD_MDIO_READ_IN_PRTAD_OFST 4\n+#define\tMC_CMD_MDIO_READ_IN_PRTAD_LEN 4\n /* Device Address or clause 22. */\n #define\tMC_CMD_MDIO_READ_IN_DEVAD_OFST 8\n+#define\tMC_CMD_MDIO_READ_IN_DEVAD_LEN 4\n /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you\n  * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.\n  */\n #define\tMC_CMD_MDIO_CLAUSE22 0x20\n /* Address */\n #define\tMC_CMD_MDIO_READ_IN_ADDR_OFST 12\n+#define\tMC_CMD_MDIO_READ_IN_ADDR_LEN 4\n \n /* MC_CMD_MDIO_READ_OUT msgresponse */\n #define\tMC_CMD_MDIO_READ_OUT_LEN 8\n /* Value */\n #define\tMC_CMD_MDIO_READ_OUT_VALUE_OFST 0\n+#define\tMC_CMD_MDIO_READ_OUT_VALUE_LEN 4\n /* Status the MDIO commands return the raw status bits from the MDIO block. A\n  * \"good\" transaction should have the DONE bit set and all other bits clear.\n  */\n #define\tMC_CMD_MDIO_READ_OUT_STATUS_OFST 4\n+#define\tMC_CMD_MDIO_READ_OUT_STATUS_LEN 4\n /* enum: Good. */\n #define\tMC_CMD_MDIO_STATUS_GOOD 0x8\n \n@@ -4365,22 +2342,27 @@\n  * external devices.\n  */\n #define\tMC_CMD_MDIO_WRITE_IN_BUS_OFST 0\n+#define\tMC_CMD_MDIO_WRITE_IN_BUS_LEN 4\n /* enum: Internal. */\n /*               MC_CMD_MDIO_BUS_INTERNAL 0x0 */\n /* enum: External. */\n /*               MC_CMD_MDIO_BUS_EXTERNAL 0x1 */\n /* Port address */\n #define\tMC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4\n+#define\tMC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4\n /* Device Address or clause 22. */\n #define\tMC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8\n+#define\tMC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4\n /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you\n  * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.\n  */\n /*               MC_CMD_MDIO_CLAUSE22 0x20 */\n /* Address */\n #define\tMC_CMD_MDIO_WRITE_IN_ADDR_OFST 12\n+#define\tMC_CMD_MDIO_WRITE_IN_ADDR_LEN 4\n /* Value */\n #define\tMC_CMD_MDIO_WRITE_IN_VALUE_OFST 16\n+#define\tMC_CMD_MDIO_WRITE_IN_VALUE_LEN 4\n \n /* MC_CMD_MDIO_WRITE_OUT msgresponse */\n #define\tMC_CMD_MDIO_WRITE_OUT_LEN 4\n@@ -4388,6 +2370,7 @@\n  * \"good\" transaction should have the DONE bit set and all other bits clear.\n  */\n #define\tMC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0\n+#define\tMC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4\n /* enum: Good. */\n /*               MC_CMD_MDIO_STATUS_GOOD 0x8 */\n \n@@ -4399,7 +2382,7 @@\n #define\tMC_CMD_DBI_WRITE 0x12\n #undef\tMC_CMD_0x12_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_DBI_WRITE_IN msgrequest */\n #define\tMC_CMD_DBI_WRITE_IN_LENMIN 12\n@@ -4419,9 +2402,11 @@\n /* MC_CMD_DBIWROP_TYPEDEF structuredef */\n #define\tMC_CMD_DBIWROP_TYPEDEF_LEN 12\n #define\tMC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0\n+#define\tMC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4\n #define\tMC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0\n #define\tMC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32\n #define\tMC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4\n+#define\tMC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4\n #define\tMC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16\n #define\tMC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16\n #define\tMC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15\n@@ -4431,6 +2416,7 @@\n #define\tMC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32\n #define\tMC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32\n #define\tMC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8\n+#define\tMC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4\n #define\tMC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64\n #define\tMC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32\n \n@@ -4446,13 +2432,16 @@\n #define\tMC_CMD_PORT_READ32_IN_LEN 4\n /* Address */\n #define\tMC_CMD_PORT_READ32_IN_ADDR_OFST 0\n+#define\tMC_CMD_PORT_READ32_IN_ADDR_LEN 4\n \n /* MC_CMD_PORT_READ32_OUT msgresponse */\n #define\tMC_CMD_PORT_READ32_OUT_LEN 8\n /* Value */\n #define\tMC_CMD_PORT_READ32_OUT_VALUE_OFST 0\n+#define\tMC_CMD_PORT_READ32_OUT_VALUE_LEN 4\n /* Status */\n #define\tMC_CMD_PORT_READ32_OUT_STATUS_OFST 4\n+#define\tMC_CMD_PORT_READ32_OUT_STATUS_LEN 4\n \n \n /***********************************/\n@@ -4466,13 +2455,16 @@\n #define\tMC_CMD_PORT_WRITE32_IN_LEN 8\n /* Address */\n #define\tMC_CMD_PORT_WRITE32_IN_ADDR_OFST 0\n+#define\tMC_CMD_PORT_WRITE32_IN_ADDR_LEN 4\n /* Value */\n #define\tMC_CMD_PORT_WRITE32_IN_VALUE_OFST 4\n+#define\tMC_CMD_PORT_WRITE32_IN_VALUE_LEN 4\n \n /* MC_CMD_PORT_WRITE32_OUT msgresponse */\n #define\tMC_CMD_PORT_WRITE32_OUT_LEN 4\n /* Status */\n #define\tMC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0\n+#define\tMC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4\n \n \n /***********************************/\n@@ -4486,6 +2478,7 @@\n #define\tMC_CMD_PORT_READ128_IN_LEN 4\n /* Address */\n #define\tMC_CMD_PORT_READ128_IN_ADDR_OFST 0\n+#define\tMC_CMD_PORT_READ128_IN_ADDR_LEN 4\n \n /* MC_CMD_PORT_READ128_OUT msgresponse */\n #define\tMC_CMD_PORT_READ128_OUT_LEN 20\n@@ -4494,6 +2487,7 @@\n #define\tMC_CMD_PORT_READ128_OUT_VALUE_LEN 16\n /* Status */\n #define\tMC_CMD_PORT_READ128_OUT_STATUS_OFST 16\n+#define\tMC_CMD_PORT_READ128_OUT_STATUS_LEN 4\n \n \n /***********************************/\n@@ -4507,6 +2501,7 @@\n #define\tMC_CMD_PORT_WRITE128_IN_LEN 20\n /* Address */\n #define\tMC_CMD_PORT_WRITE128_IN_ADDR_OFST 0\n+#define\tMC_CMD_PORT_WRITE128_IN_ADDR_LEN 4\n /* Value */\n #define\tMC_CMD_PORT_WRITE128_IN_VALUE_OFST 4\n #define\tMC_CMD_PORT_WRITE128_IN_VALUE_LEN 16\n@@ -4515,6 +2510,7 @@\n #define\tMC_CMD_PORT_WRITE128_OUT_LEN 4\n /* Status */\n #define\tMC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0\n+#define\tMC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4\n \n /* MC_CMD_CAPABILITIES structuredef */\n #define\tMC_CMD_CAPABILITIES_LEN 4\n@@ -4560,20 +2556,27 @@\n #define\tMC_CMD_GET_BOARD_CFG_OUT_LENMAX 136\n #define\tMC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))\n #define\tMC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4\n #define\tMC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4\n #define\tMC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32\n /* See MC_CMD_CAPABILITIES */\n #define\tMC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4\n /* See MC_CMD_CAPABILITIES */\n #define\tMC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4\n #define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44\n #define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6\n #define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50\n #define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6\n #define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4\n #define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4\n #define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4\n #define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68\n+#define\tMC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4\n /* This field contains a 16-bit value for each of the types of NVRAM area. The\n  * values are defined in the firmware/mc/platform/.c file for a specific board\n  * type, but otherwise have no meaning to the MC; they are used by the driver\n@@ -4592,7 +2595,7 @@\n #define\tMC_CMD_DBI_READX 0x19\n #undef\tMC_CMD_0x19_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_DBI_READX_IN msgrequest */\n #define\tMC_CMD_DBI_READX_IN_LENMIN 8\n@@ -4619,9 +2622,11 @@\n /* MC_CMD_DBIRDOP_TYPEDEF structuredef */\n #define\tMC_CMD_DBIRDOP_TYPEDEF_LEN 8\n #define\tMC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4\n #define\tMC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0\n #define\tMC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32\n #define\tMC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4\n #define\tMC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16\n #define\tMC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16\n #define\tMC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15\n@@ -4639,7 +2644,7 @@\n #define\tMC_CMD_SET_RAND_SEED 0x1a\n #undef\tMC_CMD_0x1a_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_SET_RAND_SEED_IN msgrequest */\n #define\tMC_CMD_SET_RAND_SEED_IN_LEN 16\n@@ -4689,14 +2694,17 @@\n #define\tMC_CMD_DRV_ATTACH_IN_LEN 12\n /* new state to set if UPDATE=1 */\n #define\tMC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0\n+#define\tMC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4\n #define\tMC_CMD_DRV_ATTACH_LBN 0\n #define\tMC_CMD_DRV_ATTACH_WIDTH 1\n #define\tMC_CMD_DRV_PREBOOT_LBN 1\n #define\tMC_CMD_DRV_PREBOOT_WIDTH 1\n /* 1 to set new state, or 0 to just report the existing state */\n #define\tMC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4\n+#define\tMC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4\n /* preferred datapath firmware (for Huntington; ignored for Siena) */\n #define\tMC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8\n+#define\tMC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4\n /* enum: Prefer to use full featured firmware */\n #define\tMC_CMD_FW_FULL_FEATURED 0x0\n /* enum: Prefer to use firmware with fewer features but lower latency */\n@@ -4720,13 +2728,16 @@\n #define\tMC_CMD_DRV_ATTACH_OUT_LEN 4\n /* previous or existing state, see the bitmask at NEW_STATE */\n #define\tMC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0\n+#define\tMC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4\n \n /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */\n #define\tMC_CMD_DRV_ATTACH_EXT_OUT_LEN 8\n /* previous or existing state, see the bitmask at NEW_STATE */\n #define\tMC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0\n+#define\tMC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4\n /* Flags associated with this function */\n #define\tMC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4\n+#define\tMC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4\n /* enum: Labels the lowest-numbered function visible to the OS */\n #define\tMC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0\n /* enum: The function can control the link state of the physical port it is\n@@ -4751,6 +2762,7 @@\n #define\tMC_CMD_SHMUART_IN_LEN 4\n /* ??? */\n #define\tMC_CMD_SHMUART_IN_FLAG_OFST 0\n+#define\tMC_CMD_SHMUART_IN_FLAG_LEN 4\n \n /* MC_CMD_SHMUART_OUT msgresponse */\n #define\tMC_CMD_SHMUART_OUT_LEN 0\n@@ -4789,6 +2801,7 @@\n  * (TBD).\n  */\n #define\tMC_CMD_ENTITY_RESET_IN_FLAG_OFST 0\n+#define\tMC_CMD_ENTITY_RESET_IN_FLAG_LEN 4\n #define\tMC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0\n #define\tMC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1\n \n@@ -4806,8 +2819,10 @@\n #define\tMC_CMD_PCIE_CREDITS_IN_LEN 8\n /* poll period. 0 is disabled */\n #define\tMC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0\n+#define\tMC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4\n /* wipe statistics */\n #define\tMC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4\n+#define\tMC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4\n \n /* MC_CMD_PCIE_CREDITS_OUT msgresponse */\n #define\tMC_CMD_PCIE_CREDITS_OUT_LEN 16\n@@ -4838,31 +2853,54 @@\n /* MC_CMD_RXD_MONITOR_IN msgrequest */\n #define\tMC_CMD_RXD_MONITOR_IN_LEN 12\n #define\tMC_CMD_RXD_MONITOR_IN_QID_OFST 0\n+#define\tMC_CMD_RXD_MONITOR_IN_QID_LEN 4\n #define\tMC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4\n+#define\tMC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4\n #define\tMC_CMD_RXD_MONITOR_IN_WIPE_OFST 8\n+#define\tMC_CMD_RXD_MONITOR_IN_WIPE_LEN 4\n \n /* MC_CMD_RXD_MONITOR_OUT msgresponse */\n #define\tMC_CMD_RXD_MONITOR_OUT_LEN 80\n #define\tMC_CMD_RXD_MONITOR_OUT_QID_OFST 0\n+#define\tMC_CMD_RXD_MONITOR_OUT_QID_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48\n+#define\tMC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4\n #define\tMC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76\n+#define\tMC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4\n \n \n /***********************************/\n@@ -4872,13 +2910,14 @@\n #define\tMC_CMD_PUTS 0x23\n #undef\tMC_CMD_0x23_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_PUTS_IN msgrequest */\n #define\tMC_CMD_PUTS_IN_LENMIN 13\n #define\tMC_CMD_PUTS_IN_LENMAX 252\n #define\tMC_CMD_PUTS_IN_LEN(num) (12+1*(num))\n #define\tMC_CMD_PUTS_IN_DEST_OFST 0\n+#define\tMC_CMD_PUTS_IN_DEST_LEN 4\n #define\tMC_CMD_PUTS_IN_UART_LBN 0\n #define\tMC_CMD_PUTS_IN_UART_WIDTH 1\n #define\tMC_CMD_PUTS_IN_PORT_LBN 1\n@@ -4911,6 +2950,7 @@\n #define\tMC_CMD_GET_PHY_CFG_OUT_LEN 72\n /* flags */\n #define\tMC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4\n #define\tMC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0\n #define\tMC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1\n #define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1\n@@ -4927,8 +2967,10 @@\n #define\tMC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1\n /* ?? */\n #define\tMC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4\n+#define\tMC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4\n /* Bitmask of supported capabilities */\n #define\tMC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8\n+#define\tMC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4\n #define\tMC_CMD_PHY_CAP_10HDX_LBN 1\n #define\tMC_CMD_PHY_CAP_10HDX_WIDTH 1\n #define\tMC_CMD_PHY_CAP_10FDX_LBN 2\n@@ -4953,17 +2995,39 @@\n #define\tMC_CMD_PHY_CAP_40000FDX_WIDTH 1\n #define\tMC_CMD_PHY_CAP_DDM_LBN 12\n #define\tMC_CMD_PHY_CAP_DDM_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_100000FDX_LBN 13\n+#define\tMC_CMD_PHY_CAP_100000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_25000FDX_LBN 14\n+#define\tMC_CMD_PHY_CAP_25000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_50000FDX_LBN 15\n+#define\tMC_CMD_PHY_CAP_50000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_BASER_FEC_LBN 16\n+#define\tMC_CMD_PHY_CAP_BASER_FEC_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17\n+#define\tMC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_RS_FEC_LBN 18\n+#define\tMC_CMD_PHY_CAP_RS_FEC_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19\n+#define\tMC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20\n+#define\tMC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21\n+#define\tMC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1\n /* ?? */\n #define\tMC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12\n+#define\tMC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4\n /* ?? */\n #define\tMC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16\n+#define\tMC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4\n /* ?? */\n #define\tMC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20\n+#define\tMC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4\n /* ?? */\n #define\tMC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24\n #define\tMC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20\n /* ?? */\n #define\tMC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44\n+#define\tMC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4\n /* enum: Xaui. */\n #define\tMC_CMD_MEDIA_XAUI 0x1\n /* enum: CX4. */\n@@ -4979,6 +3043,7 @@\n /* enum: QSFP+. */\n #define\tMC_CMD_MEDIA_QSFP_PLUS 0x7\n #define\tMC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48\n+#define\tMC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4\n /* enum: Native clause 22 */\n #define\tMC_CMD_MMD_CLAUSE22 0x0\n #define\tMC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */\n@@ -5010,6 +3075,7 @@\n #define\tMC_CMD_START_BIST_IN_LEN 4\n /* Type of test. */\n #define\tMC_CMD_START_BIST_IN_TYPE_OFST 0\n+#define\tMC_CMD_START_BIST_IN_TYPE_LEN 4\n /* enum: Run the PHY's short cable BIST. */\n #define\tMC_CMD_PHY_BIST_CABLE_SHORT 0x1\n /* enum: Run the PHY's long cable BIST. */\n@@ -5052,6 +3118,7 @@\n #define\tMC_CMD_POLL_BIST_OUT_LEN 8\n /* result */\n #define\tMC_CMD_POLL_BIST_OUT_RESULT_OFST 0\n+#define\tMC_CMD_POLL_BIST_OUT_RESULT_LEN 4\n /* enum: Running. */\n #define\tMC_CMD_POLL_BIST_RUNNING 0x1\n /* enum: Passed. */\n@@ -5061,19 +3128,26 @@\n /* enum: Timed-out. */\n #define\tMC_CMD_POLL_BIST_TIMEOUT 0x4\n #define\tMC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4\n+#define\tMC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4\n \n /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */\n #define\tMC_CMD_POLL_BIST_OUT_SFT9001_LEN 36\n /* result */\n /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */\n+/*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */\n /*            Enum values, see field(s): */\n /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */\n #define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4\n #define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4\n #define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4\n #define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4\n /* Status of each channel A */\n #define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4\n /* enum: Ok. */\n #define\tMC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1\n /* enum: Open. */\n@@ -5086,14 +3160,17 @@\n #define\tMC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9\n /* Status of each channel B */\n #define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4\n /*            Enum values, see field(s): */\n /*               CABLE_STATUS_A */\n /* Status of each channel C */\n #define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4\n /*            Enum values, see field(s): */\n /*               CABLE_STATUS_A */\n /* Status of each channel D */\n #define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32\n+#define\tMC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4\n /*            Enum values, see field(s): */\n /*               CABLE_STATUS_A */\n \n@@ -5101,9 +3178,11 @@\n #define\tMC_CMD_POLL_BIST_OUT_MRSFP_LEN 8\n /* result */\n /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */\n+/*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */\n /*            Enum values, see field(s): */\n /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */\n #define\tMC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4\n+#define\tMC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4\n /* enum: Complete. */\n #define\tMC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0\n /* enum: Bus switch off I2C write. */\n@@ -5127,9 +3206,11 @@\n #define\tMC_CMD_POLL_BIST_OUT_MEM_LEN 36\n /* result */\n /*            MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */\n+/*            MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */\n /*            Enum values, see field(s): */\n /*               MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */\n #define\tMC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4\n /* enum: Test has completed. */\n #define\tMC_CMD_POLL_BIST_MEM_COMPLETE 0x0\n /* enum: RAM test - walk ones. */\n@@ -5146,8 +3227,10 @@\n #define\tMC_CMD_POLL_BIST_MEM_ECC 0x6\n /* Failure address, only valid if result is POLL_BIST_FAILED */\n #define\tMC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4\n /* Bus or address space to which the failure address corresponds */\n #define\tMC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4\n /* enum: MC MIPS bus. */\n #define\tMC_CMD_POLL_BIST_MEM_BUS_MC 0x0\n /* enum: CSR IREG bus. */\n@@ -5168,14 +3251,19 @@\n #define\tMC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8\n /* Pattern written to RAM / register */\n #define\tMC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4\n /* Actual value read from RAM / register */\n #define\tMC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4\n /* ECC error mask */\n #define\tMC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4\n /* ECC parity error mask */\n #define\tMC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4\n /* ECC fatal error mask */\n #define\tMC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32\n+#define\tMC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4\n \n \n /***********************************/\n@@ -5328,6 +3416,143 @@\n /*            Enum values, see field(s): */\n /*               100M */\n \n+/* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for\n+ * newer NICs with 25G/50G/100G support\n+ */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64\n+/* Supported loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4\n+/* enum: None. */\n+/*               MC_CMD_LOOPBACK_NONE  0x0 */\n+/* enum: Data. */\n+/*               MC_CMD_LOOPBACK_DATA  0x1 */\n+/* enum: GMAC. */\n+/*               MC_CMD_LOOPBACK_GMAC  0x2 */\n+/* enum: XGMII. */\n+/*               MC_CMD_LOOPBACK_XGMII 0x3 */\n+/* enum: XGXS. */\n+/*               MC_CMD_LOOPBACK_XGXS  0x4 */\n+/* enum: XAUI. */\n+/*               MC_CMD_LOOPBACK_XAUI  0x5 */\n+/* enum: GMII. */\n+/*               MC_CMD_LOOPBACK_GMII  0x6 */\n+/* enum: SGMII. */\n+/*               MC_CMD_LOOPBACK_SGMII  0x7 */\n+/* enum: XGBR. */\n+/*               MC_CMD_LOOPBACK_XGBR  0x8 */\n+/* enum: XFI. */\n+/*               MC_CMD_LOOPBACK_XFI  0x9 */\n+/* enum: XAUI Far. */\n+/*               MC_CMD_LOOPBACK_XAUI_FAR  0xa */\n+/* enum: GMII Far. */\n+/*               MC_CMD_LOOPBACK_GMII_FAR  0xb */\n+/* enum: SGMII Far. */\n+/*               MC_CMD_LOOPBACK_SGMII_FAR  0xc */\n+/* enum: XFI Far. */\n+/*               MC_CMD_LOOPBACK_XFI_FAR  0xd */\n+/* enum: GPhy. */\n+/*               MC_CMD_LOOPBACK_GPHY  0xe */\n+/* enum: PhyXS. */\n+/*               MC_CMD_LOOPBACK_PHYXS  0xf */\n+/* enum: PCS. */\n+/*               MC_CMD_LOOPBACK_PCS  0x10 */\n+/* enum: PMA-PMD. */\n+/*               MC_CMD_LOOPBACK_PMAPMD  0x11 */\n+/* enum: Cross-Port. */\n+/*               MC_CMD_LOOPBACK_XPORT  0x12 */\n+/* enum: XGMII-Wireside. */\n+/*               MC_CMD_LOOPBACK_XGMII_WS  0x13 */\n+/* enum: XAUI Wireside. */\n+/*               MC_CMD_LOOPBACK_XAUI_WS  0x14 */\n+/* enum: XAUI Wireside Far. */\n+/*               MC_CMD_LOOPBACK_XAUI_WS_FAR  0x15 */\n+/* enum: XAUI Wireside near. */\n+/*               MC_CMD_LOOPBACK_XAUI_WS_NEAR  0x16 */\n+/* enum: GMII Wireside. */\n+/*               MC_CMD_LOOPBACK_GMII_WS  0x17 */\n+/* enum: XFI Wireside. */\n+/*               MC_CMD_LOOPBACK_XFI_WS  0x18 */\n+/* enum: XFI Wireside Far. */\n+/*               MC_CMD_LOOPBACK_XFI_WS_FAR  0x19 */\n+/* enum: PhyXS Wireside. */\n+/*               MC_CMD_LOOPBACK_PHYXS_WS  0x1a */\n+/* enum: PMA lanes MAC-Serdes. */\n+/*               MC_CMD_LOOPBACK_PMA_INT  0x1b */\n+/* enum: KR Serdes Parallel (Encoder). */\n+/*               MC_CMD_LOOPBACK_SD_NEAR  0x1c */\n+/* enum: KR Serdes Serial. */\n+/*               MC_CMD_LOOPBACK_SD_FAR  0x1d */\n+/* enum: PMA lanes MAC-Serdes Wireside. */\n+/*               MC_CMD_LOOPBACK_PMA_INT_WS  0x1e */\n+/* enum: KR Serdes Parallel Wireside (Full PCS). */\n+/*               MC_CMD_LOOPBACK_SD_FEP2_WS  0x1f */\n+/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */\n+/*               MC_CMD_LOOPBACK_SD_FEP1_5_WS  0x20 */\n+/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */\n+/*               MC_CMD_LOOPBACK_SD_FEP_WS  0x21 */\n+/* enum: KR Serdes Serial Wireside. */\n+/*               MC_CMD_LOOPBACK_SD_FES_WS  0x22 */\n+/* enum: Near side of AOE Siena side port */\n+/*               MC_CMD_LOOPBACK_AOE_INT_NEAR  0x23 */\n+/* enum: Medford Wireside datapath loopback */\n+/*               MC_CMD_LOOPBACK_DATA_WS  0x24 */\n+/* enum: Force link up without setting up any physical loopback (snapper use\n+ * only)\n+ */\n+/*               MC_CMD_LOOPBACK_FORCE_EXT_LINK  0x25 */\n+/* Supported loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12\n+/*            Enum values, see field(s): */\n+/*               100M */\n+/* Supported loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20\n+/*            Enum values, see field(s): */\n+/*               100M */\n+/* Supported loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28\n+/*            Enum values, see field(s): */\n+/*               100M */\n+/* Supported loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36\n+/*            Enum values, see field(s): */\n+/*               100M */\n+/* Supported 25G loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44\n+/*            Enum values, see field(s): */\n+/*               100M */\n+/* Supported 50 loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52\n+/*            Enum values, see field(s): */\n+/*               100M */\n+/* Supported 100G loopbacks. */\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60\n+/*            Enum values, see field(s): */\n+/*               100M */\n+\n \n /***********************************/\n /* MC_CMD_GET_LINK\n@@ -5346,17 +3571,22 @@\n #define\tMC_CMD_GET_LINK_OUT_LEN 28\n /* near-side advertised capabilities */\n #define\tMC_CMD_GET_LINK_OUT_CAP_OFST 0\n+#define\tMC_CMD_GET_LINK_OUT_CAP_LEN 4\n /* link-partner advertised capabilities */\n #define\tMC_CMD_GET_LINK_OUT_LP_CAP_OFST 4\n+#define\tMC_CMD_GET_LINK_OUT_LP_CAP_LEN 4\n /* Autonegotiated speed in mbit/s. The link may still be down even if this\n  * reads non-zero.\n  */\n #define\tMC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8\n+#define\tMC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4\n /* Current loopback setting. */\n #define\tMC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12\n+#define\tMC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */\n #define\tMC_CMD_GET_LINK_OUT_FLAGS_OFST 16\n+#define\tMC_CMD_GET_LINK_OUT_FLAGS_LEN 4\n #define\tMC_CMD_GET_LINK_OUT_LINK_UP_LBN 0\n #define\tMC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1\n #define\tMC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1\n@@ -5371,9 +3601,11 @@\n #define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1\n /* This returns the negotiated flow control value. */\n #define\tMC_CMD_GET_LINK_OUT_FCNTL_OFST 20\n+#define\tMC_CMD_GET_LINK_OUT_FCNTL_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */\n #define\tMC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24\n+#define\tMC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4\n #define\tMC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0\n #define\tMC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1\n #define\tMC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1\n@@ -5398,8 +3630,10 @@\n #define\tMC_CMD_SET_LINK_IN_LEN 16\n /* ??? */\n #define\tMC_CMD_SET_LINK_IN_CAP_OFST 0\n+#define\tMC_CMD_SET_LINK_IN_CAP_LEN 4\n /* Flags */\n #define\tMC_CMD_SET_LINK_IN_FLAGS_OFST 4\n+#define\tMC_CMD_SET_LINK_IN_FLAGS_LEN 4\n #define\tMC_CMD_SET_LINK_IN_LOWPOWER_LBN 0\n #define\tMC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1\n #define\tMC_CMD_SET_LINK_IN_POWEROFF_LBN 1\n@@ -5408,12 +3642,14 @@\n #define\tMC_CMD_SET_LINK_IN_TXDIS_WIDTH 1\n /* Loopback mode. */\n #define\tMC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8\n+#define\tMC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */\n /* A loopback speed of \"0\" is supported, and means (choose any available\n  * speed).\n  */\n #define\tMC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12\n+#define\tMC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4\n \n /* MC_CMD_SET_LINK_OUT msgresponse */\n #define\tMC_CMD_SET_LINK_OUT_LEN 0\n@@ -5432,6 +3668,7 @@\n #define\tMC_CMD_SET_ID_LED_IN_LEN 4\n /* Set LED state. */\n #define\tMC_CMD_SET_ID_LED_IN_STATE_OFST 0\n+#define\tMC_CMD_SET_ID_LED_IN_STATE_LEN 4\n #define\tMC_CMD_LED_OFF  0x0 /* enum */\n #define\tMC_CMD_LED_ON  0x1 /* enum */\n #define\tMC_CMD_LED_DEFAULT  0x2 /* enum */\n@@ -5455,17 +3692,21 @@\n  * EtherII, VLAN, bug16011 padding).\n  */\n #define\tMC_CMD_SET_MAC_IN_MTU_OFST 0\n+#define\tMC_CMD_SET_MAC_IN_MTU_LEN 4\n #define\tMC_CMD_SET_MAC_IN_DRAIN_OFST 4\n+#define\tMC_CMD_SET_MAC_IN_DRAIN_LEN 4\n #define\tMC_CMD_SET_MAC_IN_ADDR_OFST 8\n #define\tMC_CMD_SET_MAC_IN_ADDR_LEN 8\n #define\tMC_CMD_SET_MAC_IN_ADDR_LO_OFST 8\n #define\tMC_CMD_SET_MAC_IN_ADDR_HI_OFST 12\n #define\tMC_CMD_SET_MAC_IN_REJECT_OFST 16\n+#define\tMC_CMD_SET_MAC_IN_REJECT_LEN 4\n #define\tMC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0\n #define\tMC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1\n #define\tMC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1\n #define\tMC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1\n #define\tMC_CMD_SET_MAC_IN_FCNTL_OFST 20\n+#define\tMC_CMD_SET_MAC_IN_FCNTL_LEN 4\n /* enum: Flow control is off. */\n #define\tMC_CMD_FCNTL_OFF 0x0\n /* enum: Respond to flow control. */\n@@ -5479,6 +3720,7 @@\n /* enum: Issue flow control. */\n #define\tMC_CMD_FCNTL_GENERATE 0x5\n #define\tMC_CMD_SET_MAC_IN_FLAGS_OFST 24\n+#define\tMC_CMD_SET_MAC_IN_FLAGS_LEN 4\n #define\tMC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0\n #define\tMC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1\n \n@@ -5488,17 +3730,21 @@\n  * EtherII, VLAN, bug16011 padding).\n  */\n #define\tMC_CMD_SET_MAC_EXT_IN_MTU_OFST 0\n+#define\tMC_CMD_SET_MAC_EXT_IN_MTU_LEN 4\n #define\tMC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4\n+#define\tMC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4\n #define\tMC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8\n #define\tMC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8\n #define\tMC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8\n #define\tMC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16\n+#define\tMC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1\n #define\tMC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20\n+#define\tMC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4\n /* enum: Flow control is off. */\n /*               MC_CMD_FCNTL_OFF 0x0 */\n /* enum: Respond to flow control. */\n@@ -5512,6 +3758,7 @@\n /* enum: Issue flow control. */\n /*               MC_CMD_FCNTL_GENERATE 0x5 */\n #define\tMC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24\n+#define\tMC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4\n #define\tMC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0\n #define\tMC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1\n /* Select which parameters to configure. A parameter will only be modified if\n@@ -5520,6 +3767,7 @@\n  * set).\n  */\n #define\tMC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28\n+#define\tMC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1\n@@ -5541,6 +3789,7 @@\n  * to 0.\n  */\n #define\tMC_CMD_SET_MAC_V2_OUT_MTU_OFST 0\n+#define\tMC_CMD_SET_MAC_V2_OUT_MTU_LEN 4\n \n \n /***********************************/\n@@ -5647,6 +3896,7 @@\n #define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0\n #define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4\n #define\tMC_CMD_MAC_STATS_IN_CMD_OFST 8\n+#define\tMC_CMD_MAC_STATS_IN_CMD_LEN 4\n #define\tMC_CMD_MAC_STATS_IN_DMA_LBN 0\n #define\tMC_CMD_MAC_STATS_IN_DMA_WIDTH 1\n #define\tMC_CMD_MAC_STATS_IN_CLEAR_LBN 1\n@@ -5661,9 +3911,16 @@\n #define\tMC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1\n #define\tMC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16\n #define\tMC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16\n+/* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as\n+ * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not\n+ * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to\n+ * MC_CMD_MAC_NSTATS * sizeof(uint64_t)\n+ */\n #define\tMC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12\n+#define\tMC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4\n /* port id so vadapter stats can be provided */\n #define\tMC_CMD_MAC_STATS_IN_PORT_ID_OFST 16\n+#define\tMC_CMD_MAC_STATS_IN_PORT_ID_LEN 4\n \n /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */\n #define\tMC_CMD_MAC_STATS_OUT_DMA_LEN 0\n@@ -5808,9 +4065,50 @@\n #define\tMC_CMD_GMAC_DMABUF_START  0x40\n /* enum: End of GMAC stats buffer space, for Siena only. */\n #define\tMC_CMD_GMAC_DMABUF_END    0x5f\n-#define\tMC_CMD_MAC_GENERATION_END 0x60 /* enum */\n+/* enum: GENERATION_END value, used together with GENERATION_START to verify\n+ * consistency of DMAd data. For legacy firmware / drivers without extended\n+ * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *\n+ * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise,\n+ * this value is invalid/ reserved and GENERATION_END is written as the last\n+ * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that\n+ * this is consistent with the legacy behaviour, in the sense that entry 96 is\n+ * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *\n+ * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.\n+ */\n+#define\tMC_CMD_MAC_GENERATION_END 0x60\n #define\tMC_CMD_MAC_NSTATS  0x61 /* enum */\n \n+/* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */\n+#define\tMC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0\n+\n+/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3)\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2\n+/* enum: Start of FEC stats buffer space, Medford2 and up */\n+#define\tMC_CMD_MAC_FEC_DMABUF_START  0x61\n+/* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)\n+ */\n+#define\tMC_CMD_MAC_FEC_UNCORRECTED_ERRORS  0x61\n+/* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)\n+ */\n+#define\tMC_CMD_MAC_FEC_CORRECTED_ERRORS  0x62\n+/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */\n+#define\tMC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0  0x63\n+/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */\n+#define\tMC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1  0x64\n+/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */\n+#define\tMC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2  0x65\n+/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */\n+#define\tMC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3  0x66\n+/* enum: This includes the final GENERATION_END */\n+#define\tMC_CMD_MAC_NSTATS_V2  0x68\n+/*            Other enum values, see field(s): */\n+/*               MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */\n+\n \n /***********************************/\n /* MC_CMD_SRIOV\n@@ -5821,21 +4119,28 @@\n /* MC_CMD_SRIOV_IN msgrequest */\n #define\tMC_CMD_SRIOV_IN_LEN 12\n #define\tMC_CMD_SRIOV_IN_ENABLE_OFST 0\n+#define\tMC_CMD_SRIOV_IN_ENABLE_LEN 4\n #define\tMC_CMD_SRIOV_IN_VI_BASE_OFST 4\n+#define\tMC_CMD_SRIOV_IN_VI_BASE_LEN 4\n #define\tMC_CMD_SRIOV_IN_VF_COUNT_OFST 8\n+#define\tMC_CMD_SRIOV_IN_VF_COUNT_LEN 4\n \n /* MC_CMD_SRIOV_OUT msgresponse */\n #define\tMC_CMD_SRIOV_OUT_LEN 8\n #define\tMC_CMD_SRIOV_OUT_VI_SCALE_OFST 0\n+#define\tMC_CMD_SRIOV_OUT_VI_SCALE_LEN 4\n #define\tMC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4\n+#define\tMC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4\n \n /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32\n /* this is only used for the first record */\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8\n@@ -5845,6 +4150,7 @@\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32\n@@ -5855,6 +4161,7 @@\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32\n \n@@ -5907,10 +4214,12 @@\n /* MC_CMD_WOL_FILTER_SET_IN msgrequest */\n #define\tMC_CMD_WOL_FILTER_SET_IN_LEN 192\n #define\tMC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0\n+#define\tMC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4\n #define\tMC_CMD_FILTER_MODE_SIMPLE    0x0 /* enum */\n #define\tMC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */\n /* A type value of 1 is unused. */\n #define\tMC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4\n+#define\tMC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4\n /* enum: Magic */\n #define\tMC_CMD_WOL_TYPE_MAGIC      0x0\n /* enum: MS Windows Magic */\n@@ -5932,7 +4241,9 @@\n /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */\n #define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16\n /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */\n /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */\n #define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8\n #define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8\n #define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8\n@@ -5941,9 +4252,13 @@\n /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20\n /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */\n /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12\n+#define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18\n@@ -5952,7 +4267,9 @@\n /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44\n /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */\n /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24\n@@ -5965,7 +4282,9 @@\n /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */\n #define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187\n /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */\n /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */\n #define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8\n #define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48\n #define\tMC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56\n@@ -5980,8 +4299,11 @@\n /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12\n /*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */\n /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */\n+/*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1\n@@ -5990,6 +4312,7 @@\n /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */\n #define\tMC_CMD_WOL_FILTER_SET_OUT_LEN 4\n #define\tMC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0\n+#define\tMC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4\n \n \n /***********************************/\n@@ -6004,6 +4327,7 @@\n /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */\n #define\tMC_CMD_WOL_FILTER_REMOVE_IN_LEN 4\n #define\tMC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0\n+#define\tMC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4\n \n /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */\n #define\tMC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0\n@@ -6022,6 +4346,7 @@\n /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */\n #define\tMC_CMD_WOL_FILTER_RESET_IN_LEN 4\n #define\tMC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0\n+#define\tMC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4\n #define\tMC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */\n #define\tMC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */\n \n@@ -6063,6 +4388,7 @@\n #define\tMC_CMD_NVRAM_TYPES_OUT_LEN 4\n /* Bit mask of supported types. */\n #define\tMC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0\n+#define\tMC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4\n /* enum: Disabled callisto. */\n #define\tMC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0\n /* enum: MC firmware. */\n@@ -6120,17 +4446,22 @@\n /* MC_CMD_NVRAM_INFO_IN msgrequest */\n #define\tMC_CMD_NVRAM_INFO_IN_LEN 4\n #define\tMC_CMD_NVRAM_INFO_IN_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_INFO_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n \n /* MC_CMD_NVRAM_INFO_OUT msgresponse */\n #define\tMC_CMD_NVRAM_INFO_OUT_LEN 24\n #define\tMC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n #define\tMC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4\n+#define\tMC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4\n #define\tMC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8\n+#define\tMC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4\n #define\tMC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12\n+#define\tMC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4\n #define\tMC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0\n #define\tMC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1\n #define\tMC_CMD_NVRAM_INFO_OUT_TLV_LBN 1\n@@ -6142,16 +4473,22 @@\n #define\tMC_CMD_NVRAM_INFO_OUT_A_B_LBN 7\n #define\tMC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1\n #define\tMC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16\n+#define\tMC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4\n #define\tMC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20\n+#define\tMC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4\n \n /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_LEN 28\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1\n@@ -6161,10 +4498,13 @@\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4\n /* Writes must be multiples of this size. Added to support the MUM on Sorrento.\n  */\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4\n \n \n /***********************************/\n@@ -6183,6 +4523,7 @@\n  */\n #define\tMC_CMD_NVRAM_UPDATE_START_IN_LEN 4\n #define\tMC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n \n@@ -6193,9 +4534,11 @@\n  */\n #define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8\n #define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n #define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4\n+#define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4\n #define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0\n #define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1\n \n@@ -6217,20 +4560,26 @@\n /* MC_CMD_NVRAM_READ_IN msgrequest */\n #define\tMC_CMD_NVRAM_READ_IN_LEN 12\n #define\tMC_CMD_NVRAM_READ_IN_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_READ_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n #define\tMC_CMD_NVRAM_READ_IN_OFFSET_OFST 4\n+#define\tMC_CMD_NVRAM_READ_IN_OFFSET_LEN 4\n /* amount to read in bytes */\n #define\tMC_CMD_NVRAM_READ_IN_LENGTH_OFST 8\n+#define\tMC_CMD_NVRAM_READ_IN_LENGTH_LEN 4\n \n /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */\n #define\tMC_CMD_NVRAM_READ_IN_V2_LEN 16\n #define\tMC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n #define\tMC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4\n+#define\tMC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4\n /* amount to read in bytes */\n #define\tMC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8\n+#define\tMC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4\n /* Optional control info. If a partition is stored with an A/B versioning\n  * scheme (i.e. in more than one physical partition in NVRAM) the host can set\n  * this to control which underlying physical partition is used to read data\n@@ -6240,6 +4589,7 @@\n  * verifying by reading with MODE=TARGET_BACKUP.\n  */\n #define\tMC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12\n+#define\tMC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4\n /* enum: Same as omitting MODE: caller sees data in current partition unless it\n  * holds the write lock in which case it sees data in the partition it is\n  * updating.\n@@ -6280,10 +4630,13 @@\n #define\tMC_CMD_NVRAM_WRITE_IN_LENMAX 252\n #define\tMC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))\n #define\tMC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n #define\tMC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4\n+#define\tMC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4\n #define\tMC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8\n+#define\tMC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4\n #define\tMC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12\n #define\tMC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1\n #define\tMC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1\n@@ -6307,10 +4660,13 @@\n /* MC_CMD_NVRAM_ERASE_IN msgrequest */\n #define\tMC_CMD_NVRAM_ERASE_IN_LEN 12\n #define\tMC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n #define\tMC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4\n+#define\tMC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4\n #define\tMC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8\n+#define\tMC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4\n \n /* MC_CMD_NVRAM_ERASE_OUT msgresponse */\n #define\tMC_CMD_NVRAM_ERASE_OUT_LEN 0\n@@ -6332,9 +4688,11 @@\n  */\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4\n \n /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH\n  * request with additional flags indicating version of NVRAM_UPDATE commands in\n@@ -6343,10 +4701,13 @@\n  */\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1\n \n@@ -6373,6 +4734,7 @@\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4\n /* Result of nvram update completion processing */\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4\n /* enum: Invalid return code; only non-zero values are defined. Defined as\n  * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.\n  */\n@@ -6407,6 +4769,8 @@\n  * only production signed images.\n  */\n #define\tMC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc\n+/* enum: The image has a lower security level than the current firmware. */\n+#define\tMC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd\n \n \n /***********************************/\n@@ -6435,6 +4799,7 @@\n /* MC_CMD_REBOOT_IN msgrequest */\n #define\tMC_CMD_REBOOT_IN_LEN 4\n #define\tMC_CMD_REBOOT_IN_FLAGS_OFST 0\n+#define\tMC_CMD_REBOOT_IN_FLAGS_LEN 4\n #define\tMC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */\n \n /* MC_CMD_REBOOT_OUT msgresponse */\n@@ -6473,11 +4838,12 @@\n #define\tMC_CMD_REBOOT_MODE 0x3f\n #undef\tMC_CMD_0x3f_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_REBOOT_MODE_IN msgrequest */\n #define\tMC_CMD_REBOOT_MODE_IN_LEN 4\n #define\tMC_CMD_REBOOT_MODE_IN_VALUE_OFST 0\n+#define\tMC_CMD_REBOOT_MODE_IN_VALUE_LEN 4\n /* enum: Normal. */\n #define\tMC_CMD_REBOOT_MODE_NORMAL 0x0\n /* enum: Power-on Reset. */\n@@ -6492,6 +4858,7 @@\n /* MC_CMD_REBOOT_MODE_OUT msgresponse */\n #define\tMC_CMD_REBOOT_MODE_OUT_LEN 4\n #define\tMC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0\n+#define\tMC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4\n \n \n /***********************************/\n@@ -6528,7 +4895,7 @@\n #define\tMC_CMD_SENSOR_INFO 0x41\n #undef\tMC_CMD_0x41_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n \n /* MC_CMD_SENSOR_INFO_IN msgrequest */\n #define\tMC_CMD_SENSOR_INFO_IN_LEN 0\n@@ -6542,12 +4909,14 @@\n  * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.\n  */\n #define\tMC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0\n+#define\tMC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4\n \n /* MC_CMD_SENSOR_INFO_OUT msgresponse */\n #define\tMC_CMD_SENSOR_INFO_OUT_LENMIN 4\n #define\tMC_CMD_SENSOR_INFO_OUT_LENMAX 252\n #define\tMC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))\n #define\tMC_CMD_SENSOR_INFO_OUT_MASK_OFST 0\n+#define\tMC_CMD_SENSOR_INFO_OUT_MASK_LEN 4\n /* enum: Controller temperature: degC */\n #define\tMC_CMD_SENSOR_CONTROLLER_TEMP  0x0\n /* enum: Phy common temperature: degC */\n@@ -6710,6 +5079,16 @@\n #define\tMC_CMD_SENSOR_BOARD_FRONT_TEMP  0x4f\n /* enum: Board temperature (back): degC */\n #define\tMC_CMD_SENSOR_BOARD_BACK_TEMP  0x50\n+/* enum: 1.8v power current: mA */\n+#define\tMC_CMD_SENSOR_IN_I1V8  0x51\n+/* enum: 2.5v power current: mA */\n+#define\tMC_CMD_SENSOR_IN_I2V5  0x52\n+/* enum: 3.3v power current: mA */\n+#define\tMC_CMD_SENSOR_IN_I3V3  0x53\n+/* enum: 12v power current: mA */\n+#define\tMC_CMD_SENSOR_IN_I12V0  0x54\n+/* enum: Not a sensor: reserved for the next page flag */\n+#define\tMC_CMD_SENSOR_PAGE2_NEXT  0x5f\n /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */\n #define\tMC_CMD_SENSOR_ENTRY_OFST 4\n #define\tMC_CMD_SENSOR_ENTRY_LEN 8\n@@ -6723,6 +5102,7 @@\n #define\tMC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252\n #define\tMC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))\n #define\tMC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0\n+#define\tMC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_SENSOR_INFO_OUT */\n #define\tMC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31\n@@ -6775,7 +5155,7 @@\n #define\tMC_CMD_READ_SENSORS 0x42\n #undef\tMC_CMD_0x42_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n \n /* MC_CMD_READ_SENSORS_IN msgrequest */\n #define\tMC_CMD_READ_SENSORS_IN_LEN 8\n@@ -6794,6 +5174,7 @@\n #define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4\n /* Size in bytes of host buffer. */\n #define\tMC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4\n \n /* MC_CMD_READ_SENSORS_OUT msgresponse */\n #define\tMC_CMD_READ_SENSORS_OUT_LEN 0\n@@ -6848,6 +5229,7 @@\n /* MC_CMD_GET_PHY_STATE_OUT msgresponse */\n #define\tMC_CMD_GET_PHY_STATE_OUT_LEN 4\n #define\tMC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0\n+#define\tMC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4\n /* enum: Ok. */\n #define\tMC_CMD_PHY_STATE_OK 0x1\n /* enum: Faulty. */\n@@ -6885,6 +5267,7 @@\n /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */\n #define\tMC_CMD_WOL_FILTER_GET_OUT_LEN 4\n #define\tMC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0\n+#define\tMC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4\n \n \n /***********************************/\n@@ -6902,6 +5285,7 @@\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4\n #define\tMC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */\n #define\tMC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS  0x2 /* enum */\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4\n@@ -6912,13 +5296,16 @@\n /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14\n /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */\n+/*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4\n \n /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42\n /*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */\n+/*            MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10\n@@ -6929,6 +5316,7 @@\n /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4\n \n \n /***********************************/\n@@ -6944,7 +5332,9 @@\n /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */\n #define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8\n #define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0\n+#define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4\n #define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4\n+#define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4\n \n /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */\n #define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0\n@@ -6984,6 +5374,7 @@\n #define\tMC_CMD_TESTASSERT_V2_IN_LEN 4\n /* How to provoke the assertion */\n #define\tMC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0\n+#define\tMC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4\n /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless\n  * you're testing firmware, this is what you want.\n  */\n@@ -7020,6 +5411,7 @@\n #define\tMC_CMD_WORKAROUND_IN_LEN 8\n /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */\n #define\tMC_CMD_WORKAROUND_IN_TYPE_OFST 0\n+#define\tMC_CMD_WORKAROUND_IN_TYPE_LEN 4\n /* enum: Bug 17230 work around. */\n #define\tMC_CMD_WORKAROUND_BUG17230 0x1\n /* enum: Bug 35388 work around (unsafe EVQ writes). */\n@@ -7048,6 +5440,7 @@\n  * the workaround\n  */\n #define\tMC_CMD_WORKAROUND_IN_ENABLED_OFST 4\n+#define\tMC_CMD_WORKAROUND_IN_ENABLED_LEN 4\n \n /* MC_CMD_WORKAROUND_OUT msgresponse */\n #define\tMC_CMD_WORKAROUND_OUT_LEN 0\n@@ -7057,6 +5450,7 @@\n  */\n #define\tMC_CMD_WORKAROUND_EXT_OUT_LEN 4\n #define\tMC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4\n #define\tMC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0\n #define\tMC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1\n \n@@ -7078,6 +5472,7 @@\n /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */\n #define\tMC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4\n #define\tMC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4\n \n /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */\n #define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5\n@@ -7085,6 +5480,7 @@\n #define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))\n /* in bytes */\n #define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4\n #define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4\n #define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1\n #define\tMC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1\n@@ -7104,12 +5500,14 @@\n /* MC_CMD_NVRAM_TEST_IN msgrequest */\n #define\tMC_CMD_NVRAM_TEST_IN_LEN 4\n #define\tMC_CMD_NVRAM_TEST_IN_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_TEST_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n \n /* MC_CMD_NVRAM_TEST_OUT msgresponse */\n #define\tMC_CMD_NVRAM_TEST_OUT_LEN 4\n #define\tMC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0\n+#define\tMC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4\n /* enum: Passed. */\n #define\tMC_CMD_NVRAM_TEST_PASS 0x0\n /* enum: Failed. */\n@@ -7130,12 +5528,16 @@\n #define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16\n /* 0-6 low->high de-emph. */\n #define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0\n+#define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4\n /* 0-8 low->high ref.V */\n #define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4\n+#define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4\n /* 0-8 0-8 low->high boost */\n #define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8\n+#define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4\n /* 0-8 low->high ref.V */\n #define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12\n+#define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4\n \n /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */\n #define\tMC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0\n@@ -7144,10 +5546,13 @@\n #define\tMC_CMD_MRSFP_TWEAK_OUT_LEN 12\n /* input bits */\n #define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0\n+#define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4\n /* output bits */\n #define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4\n+#define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4\n /* direction */\n #define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8\n+#define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4\n /* enum: Out. */\n #define\tMC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0\n /* enum: In. */\n@@ -7163,21 +5568,26 @@\n #define\tMC_CMD_SENSOR_SET_LIMS 0x4e\n #undef\tMC_CMD_0x4e_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */\n #define\tMC_CMD_SENSOR_SET_LIMS_IN_LEN 20\n #define\tMC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */\n /* interpretation is is sensor-specific. */\n #define\tMC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4\n /* interpretation is is sensor-specific. */\n #define\tMC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4\n /* interpretation is is sensor-specific. */\n #define\tMC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4\n /* interpretation is is sensor-specific. */\n #define\tMC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16\n+#define\tMC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4\n \n /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */\n #define\tMC_CMD_SENSOR_SET_LIMS_OUT_LEN 0\n@@ -7194,9 +5604,13 @@\n /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */\n #define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16\n #define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4\n #define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4\n #define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4\n #define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4\n \n \n /***********************************/\n@@ -7218,6 +5632,7 @@\n #define\tMC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))\n /* total number of partitions */\n #define\tMC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0\n+#define\tMC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4\n /* type ID code for each of NUM_PARTITIONS partitions */\n #define\tMC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4\n #define\tMC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4\n@@ -7239,6 +5654,7 @@\n #define\tMC_CMD_NVRAM_METADATA_IN_LEN 4\n /* Partition type ID code */\n #define\tMC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4\n \n /* MC_CMD_NVRAM_METADATA_OUT msgresponse */\n #define\tMC_CMD_NVRAM_METADATA_OUT_LENMIN 20\n@@ -7246,7 +5662,9 @@\n #define\tMC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))\n /* Partition type ID code */\n #define\tMC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0\n+#define\tMC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4\n #define\tMC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4\n+#define\tMC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4\n #define\tMC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0\n #define\tMC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1\n #define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1\n@@ -7255,6 +5673,7 @@\n #define\tMC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1\n /* Subtype ID code for content of this partition */\n #define\tMC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8\n+#define\tMC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4\n /* 1st component of W.X.Y.Z version number for content of this partition */\n #define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12\n #define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2\n@@ -7296,8 +5715,10 @@\n #define\tMC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2\n /* Number of allocated MAC addresses */\n #define\tMC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8\n+#define\tMC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4\n /* Spacing of allocated MAC addresses */\n #define\tMC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12\n+#define\tMC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4\n \n \n /***********************************/\n@@ -7313,6 +5734,7 @@\n #define\tMC_CMD_CLP_IN_LEN 4\n /* Sub operation */\n #define\tMC_CMD_CLP_IN_OP_OFST 0\n+#define\tMC_CMD_CLP_IN_OP_LEN 4\n /* enum: Return to factory default settings */\n #define\tMC_CMD_CLP_OP_DEFAULT 0x1\n /* enum: Set MAC address */\n@@ -7330,6 +5752,7 @@\n /* MC_CMD_CLP_IN_DEFAULT msgrequest */\n #define\tMC_CMD_CLP_IN_DEFAULT_LEN 4\n /*            MC_CMD_CLP_IN_OP_OFST 0 */\n+/*            MC_CMD_CLP_IN_OP_LEN 4 */\n \n /* MC_CMD_CLP_OUT_DEFAULT msgresponse */\n #define\tMC_CMD_CLP_OUT_DEFAULT_LEN 0\n@@ -7337,6 +5760,7 @@\n /* MC_CMD_CLP_IN_SET_MAC msgrequest */\n #define\tMC_CMD_CLP_IN_SET_MAC_LEN 12\n /*            MC_CMD_CLP_IN_OP_OFST 0 */\n+/*            MC_CMD_CLP_IN_OP_LEN 4 */\n /* MAC address assigned to port */\n #define\tMC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4\n #define\tMC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6\n@@ -7350,6 +5774,7 @@\n /* MC_CMD_CLP_IN_GET_MAC msgrequest */\n #define\tMC_CMD_CLP_IN_GET_MAC_LEN 4\n /*            MC_CMD_CLP_IN_OP_OFST 0 */\n+/*            MC_CMD_CLP_IN_OP_LEN 4 */\n \n /* MC_CMD_CLP_OUT_GET_MAC msgresponse */\n #define\tMC_CMD_CLP_OUT_GET_MAC_LEN 8\n@@ -7363,6 +5788,7 @@\n /* MC_CMD_CLP_IN_SET_BOOT msgrequest */\n #define\tMC_CMD_CLP_IN_SET_BOOT_LEN 5\n /*            MC_CMD_CLP_IN_OP_OFST 0 */\n+/*            MC_CMD_CLP_IN_OP_LEN 4 */\n /* Boot flag */\n #define\tMC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4\n #define\tMC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1\n@@ -7373,6 +5799,7 @@\n /* MC_CMD_CLP_IN_GET_BOOT msgrequest */\n #define\tMC_CMD_CLP_IN_GET_BOOT_LEN 4\n /*            MC_CMD_CLP_IN_OP_OFST 0 */\n+/*            MC_CMD_CLP_IN_OP_LEN 4 */\n \n /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */\n #define\tMC_CMD_CLP_OUT_GET_BOOT_LEN 4\n@@ -7391,11 +5818,12 @@\n #define\tMC_CMD_MUM 0x57\n #undef\tMC_CMD_0x57_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_MUM_IN msgrequest */\n #define\tMC_CMD_MUM_IN_LEN 4\n #define\tMC_CMD_MUM_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_MUM_IN_OP_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_OP_LBN 0\n #define\tMC_CMD_MUM_IN_OP_WIDTH 8\n /* enum: NULL MCDI command to MUM */\n@@ -7435,26 +5863,32 @@\n #define\tMC_CMD_MUM_IN_NULL_LEN 4\n /* MUM cmd header */\n #define\tMC_CMD_MUM_IN_CMD_OFST 0\n+#define\tMC_CMD_MUM_IN_CMD_LEN 4\n \n /* MC_CMD_MUM_IN_GET_VERSION msgrequest */\n #define\tMC_CMD_MUM_IN_GET_VERSION_LEN 4\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n \n /* MC_CMD_MUM_IN_READ msgrequest */\n #define\tMC_CMD_MUM_IN_READ_LEN 16\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n /* ID of (device connected to MUM) to read from registers of */\n #define\tMC_CMD_MUM_IN_READ_DEVICE_OFST 4\n+#define\tMC_CMD_MUM_IN_READ_DEVICE_LEN 4\n /* enum: Hittite HMC1035 clock generator on Sorrento board */\n #define\tMC_CMD_MUM_DEV_HITTITE 0x1\n /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */\n #define\tMC_CMD_MUM_DEV_HITTITE_NIC 0x2\n /* 32-bit address to read from */\n #define\tMC_CMD_MUM_IN_READ_ADDR_OFST 8\n+#define\tMC_CMD_MUM_IN_READ_ADDR_LEN 4\n /* Number of words to read. */\n #define\tMC_CMD_MUM_IN_READ_NUMWORDS_OFST 12\n+#define\tMC_CMD_MUM_IN_READ_NUMWORDS_LEN 4\n \n /* MC_CMD_MUM_IN_WRITE msgrequest */\n #define\tMC_CMD_MUM_IN_WRITE_LENMIN 16\n@@ -7462,12 +5896,15 @@\n #define\tMC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n /* ID of (device connected to MUM) to write to registers of */\n #define\tMC_CMD_MUM_IN_WRITE_DEVICE_OFST 4\n+#define\tMC_CMD_MUM_IN_WRITE_DEVICE_LEN 4\n /* enum: Hittite HMC1035 clock generator on Sorrento board */\n /*               MC_CMD_MUM_DEV_HITTITE 0x1 */\n /* 32-bit address to write to */\n #define\tMC_CMD_MUM_IN_WRITE_ADDR_OFST 8\n+#define\tMC_CMD_MUM_IN_WRITE_ADDR_LEN 4\n /* Words to write */\n #define\tMC_CMD_MUM_IN_WRITE_BUFFER_OFST 12\n #define\tMC_CMD_MUM_IN_WRITE_BUFFER_LEN 4\n@@ -7480,12 +5917,16 @@\n #define\tMC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n /* MUM I2C cmd code */\n #define\tMC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4\n+#define\tMC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4\n /* Number of bytes to write */\n #define\tMC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8\n+#define\tMC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4\n /* Number of bytes to read */\n #define\tMC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12\n+#define\tMC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4\n /* Bytes to write */\n #define\tMC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16\n #define\tMC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1\n@@ -7496,21 +5937,28 @@\n #define\tMC_CMD_MUM_IN_LOG_LEN 8\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_LOG_OP_OFST 4\n+#define\tMC_CMD_MUM_IN_LOG_OP_LEN 4\n #define\tMC_CMD_MUM_IN_LOG_OP_UART  0x1 /* enum */\n \n /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */\n #define\tMC_CMD_MUM_IN_LOG_OP_UART_LEN 12\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n /*            MC_CMD_MUM_IN_LOG_OP_OFST 4 */\n+/*            MC_CMD_MUM_IN_LOG_OP_LEN 4 */\n /* Enable/disable debug output to UART */\n #define\tMC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8\n+#define\tMC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4\n \n /* MC_CMD_MUM_IN_GPIO msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_LEN 8\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_GPIO_OPCODE_LBN 0\n #define\tMC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8\n #define\tMC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */\n@@ -7523,40 +5971,56 @@\n /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_IN_READ_LEN 8\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4\n \n /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4\n /* The first 32-bit word to be written to the GPIO OUT register. */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4\n /* The second 32-bit word to be written to the GPIO OUT register. */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4\n \n /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4\n \n /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4\n /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4\n /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4\n \n /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4\n \n /* MC_CMD_MUM_IN_GPIO_OP msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_OP_LEN 8\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8\n #define\tMC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */\n@@ -7569,26 +6033,34 @@\n /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4\n \n /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8\n \n /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8\n \n /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8\n \n@@ -7596,7 +6068,9 @@\n #define\tMC_CMD_MUM_IN_READ_SENSORS_LEN 8\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4\n+#define\tMC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4\n #define\tMC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0\n #define\tMC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8\n #define\tMC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8\n@@ -7606,13 +6080,16 @@\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n /* Bit-mask of clocks to be programmed */\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4\n #define\tMC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */\n #define\tMC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */\n #define\tMC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */\n /* Control flags for clock programming */\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1\n@@ -7624,19 +6101,24 @@\n #define\tMC_CMD_MUM_IN_FPGA_LOAD_LEN 8\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n /* Enable/Disable FPGA config from flash */\n #define\tMC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4\n+#define\tMC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4\n \n /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */\n #define\tMC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n \n /* MC_CMD_MUM_IN_QSFP msgrequest */\n #define\tMC_CMD_MUM_IN_QSFP_LEN 12\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_QSFP_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_OPCODE_LBN 0\n #define\tMC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4\n #define\tMC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */\n@@ -7646,52 +6128,77 @@\n #define\tMC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */\n #define\tMC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */\n #define\tMC_CMD_MUM_IN_QSFP_IDX_OFST 8\n+#define\tMC_CMD_MUM_IN_QSFP_IDX_LEN 4\n \n /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */\n #define\tMC_CMD_MUM_IN_QSFP_INIT_LEN 16\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8\n+#define\tMC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12\n+#define\tMC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4\n \n /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */\n #define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20\n+#define\tMC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4\n \n /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */\n #define\tMC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8\n+#define\tMC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4\n \n /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */\n #define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8\n+#define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12\n+#define\tMC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4\n \n /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */\n #define\tMC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8\n+#define\tMC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4\n \n /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */\n #define\tMC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4\n+#define\tMC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4\n #define\tMC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8\n+#define\tMC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4\n \n /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */\n #define\tMC_CMD_MUM_IN_READ_DDR_INFO_LEN 4\n /* MUM cmd header */\n /*            MC_CMD_MUM_IN_CMD_OFST 0 */\n+/*            MC_CMD_MUM_IN_CMD_LEN 4 */\n \n /* MC_CMD_MUM_OUT msgresponse */\n #define\tMC_CMD_MUM_OUT_LEN 0\n@@ -7702,6 +6209,7 @@\n /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */\n #define\tMC_CMD_MUM_OUT_GET_VERSION_LEN 12\n #define\tMC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4\n #define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4\n #define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8\n #define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4\n@@ -7739,8 +6247,10 @@\n #define\tMC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8\n /* The first 32-bit word read from the GPIO IN register. */\n #define\tMC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0\n+#define\tMC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4\n /* The second 32-bit word read from the GPIO IN register. */\n #define\tMC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4\n+#define\tMC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4\n \n /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */\n #define\tMC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0\n@@ -7749,8 +6259,10 @@\n #define\tMC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8\n /* The first 32-bit word read from the GPIO OUT register. */\n #define\tMC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4\n /* The second 32-bit word read from the GPIO OUT register. */\n #define\tMC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4\n \n /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */\n #define\tMC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0\n@@ -7758,11 +6270,14 @@\n /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */\n #define\tMC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8\n #define\tMC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4\n #define\tMC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4\n+#define\tMC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4\n \n /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */\n #define\tMC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4\n #define\tMC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0\n+#define\tMC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4\n \n /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */\n #define\tMC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0\n@@ -7791,6 +6306,7 @@\n /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */\n #define\tMC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4\n #define\tMC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0\n+#define\tMC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4\n \n /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */\n #define\tMC_CMD_MUM_OUT_FPGA_LOAD_LEN 0\n@@ -7798,6 +6314,7 @@\n /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */\n #define\tMC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4\n #define\tMC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0\n+#define\tMC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4\n \n /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */\n #define\tMC_CMD_MUM_OUT_QSFP_INIT_LEN 0\n@@ -7805,7 +6322,9 @@\n /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1\n@@ -7814,6 +6333,7 @@\n /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */\n #define\tMC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4\n #define\tMC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4\n \n /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */\n #define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5\n@@ -7821,6 +6341,7 @@\n #define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))\n /* in bytes */\n #define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0\n+#define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4\n #define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4\n #define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1\n #define\tMC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1\n@@ -7829,11 +6350,14 @@\n /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */\n #define\tMC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8\n #define\tMC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0\n+#define\tMC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4\n #define\tMC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4\n+#define\tMC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4\n \n /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */\n #define\tMC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4\n #define\tMC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0\n+#define\tMC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4\n \n /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24\n@@ -7841,12 +6365,14 @@\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))\n /* Discrete (soldered) DDR resistor strap info */\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16\n /* Number of SODIMM info records */\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4\n /* Array of SODIMM info records */\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8\n@@ -7907,6 +6433,7 @@\n /* EVB_PORT_ID structuredef */\n #define\tEVB_PORT_ID_LEN 4\n #define\tEVB_PORT_ID_PORT_ID_OFST 0\n+#define\tEVB_PORT_ID_PORT_ID_LEN 4\n /* enum: An invalid port handle. */\n #define\tEVB_PORT_ID_NULL  0x0\n /* enum: The port assigned to this function.. */\n@@ -8002,6 +6529,10 @@\n #define\tNVRAM_PARTITION_TYPE_FC_LOG               0xb04\n /* enum: MUM firmware partition */\n #define\tNVRAM_PARTITION_TYPE_MUM_FIRMWARE         0xc00\n+/* enum: SUC firmware partition (this is intentionally an alias of\n+ * MUM_FIRMWARE)\n+ */\n+#define\tNVRAM_PARTITION_TYPE_SUC_FIRMWARE         0xc00\n /* enum: MUM Non-volatile log output partition. */\n #define\tNVRAM_PARTITION_TYPE_MUM_LOG              0xc01\n /* enum: MUM Application table partition. */\n@@ -8016,8 +6547,8 @@\n #define\tNVRAM_PARTITION_TYPE_MUM_FUSELOCK         0xc06\n /* enum: UEFI expansion ROM if separate from PXE */\n #define\tNVRAM_PARTITION_TYPE_EXPANSION_UEFI       0xd00\n-/* enum: Spare partition 0 */\n-#define\tNVRAM_PARTITION_TYPE_SPARE_0              0x1000\n+/* enum: Used by the expansion ROM for logging */\n+#define\tNVRAM_PARTITION_TYPE_PXE_LOG              0x1000\n /* enum: Used for XIP code of shmbooted images */\n #define\tNVRAM_PARTITION_TYPE_XIP_SCRATCH          0x1100\n /* enum: Spare partition 2 */\n@@ -8034,6 +6565,18 @@\n  * medford_mc_status_hdr_t for layout on Medford.\n  */\n #define\tNVRAM_PARTITION_TYPE_STATUS               0x1600\n+/* enum: Spare partition 13 */\n+#define\tNVRAM_PARTITION_TYPE_SPARE_13              0x1700\n+/* enum: Spare partition 14 */\n+#define\tNVRAM_PARTITION_TYPE_SPARE_14              0x1800\n+/* enum: Spare partition 15 */\n+#define\tNVRAM_PARTITION_TYPE_SPARE_15              0x1900\n+/* enum: Spare partition 16 */\n+#define\tNVRAM_PARTITION_TYPE_SPARE_16              0x1a00\n+/* enum: Factory defaults for dynamic configuration */\n+#define\tNVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS    0x1b00\n+/* enum: Factory defaults for expansion ROM configuration */\n+#define\tNVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS    0x1c00\n /* enum: Start of reserved value range (firmware may use for any purpose) */\n #define\tNVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN  0xff00\n /* enum: End of reserved value range (firmware may use for any purpose) */\n@@ -8048,6 +6591,7 @@\n /* LICENSED_APP_ID structuredef */\n #define\tLICENSED_APP_ID_LEN 4\n #define\tLICENSED_APP_ID_ID_OFST 0\n+#define\tLICENSED_APP_ID_ID_LEN 4\n /* enum: OpenOnload */\n #define\tLICENSED_APP_ID_ONLOAD                  0x1\n /* enum: PTP timestamping */\n@@ -8240,7 +6784,7 @@\n #define\tMC_CMD_READ_REGS 0x50\n #undef\tMC_CMD_0x50_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_READ_REGS_IN msgrequest */\n #define\tMC_CMD_READ_REGS_IN_LEN 0\n@@ -8274,17 +6818,22 @@\n #define\tMC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))\n /* Size, in entries */\n #define\tMC_CMD_INIT_EVQ_IN_SIZE_OFST 0\n+#define\tMC_CMD_INIT_EVQ_IN_SIZE_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n  * local queue index.\n  */\n #define\tMC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4\n+#define\tMC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4\n /* The initial timer value. The load value is ignored if the timer mode is DIS.\n  */\n #define\tMC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8\n+#define\tMC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4\n /* The reload value is ignored in one-shot modes */\n #define\tMC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12\n+#define\tMC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4\n /* tbd */\n #define\tMC_CMD_INIT_EVQ_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_EVQ_IN_FLAGS_LEN 4\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1\n@@ -8300,6 +6849,7 @@\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1\n #define\tMC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20\n+#define\tMC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4\n /* enum: Disabled */\n #define\tMC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0\n /* enum: Immediate */\n@@ -8310,13 +6860,16 @@\n #define\tMC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3\n /* Target EVQ for wakeups if in wakeup mode. */\n #define\tMC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24\n+#define\tMC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4\n /* Target interrupt if in interrupting mode (note union with target EVQ). Use\n  * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test\n  * purposes.\n  */\n #define\tMC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24\n+#define\tMC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4\n /* Event Counter Mode. */\n #define\tMC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28\n+#define\tMC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4\n /* enum: Disabled */\n #define\tMC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0\n /* enum: Disabled */\n@@ -8327,6 +6880,7 @@\n #define\tMC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3\n /* Event queue packet count threshold. */\n #define\tMC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32\n+#define\tMC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4\n /* 64-bit address of 4k of 4k-aligned host memory buffer */\n #define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36\n #define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8\n@@ -8339,6 +6893,7 @@\n #define\tMC_CMD_INIT_EVQ_OUT_LEN 4\n /* Only valid if INTRFLAG was true */\n #define\tMC_CMD_INIT_EVQ_OUT_IRQ_OFST 0\n+#define\tMC_CMD_INIT_EVQ_OUT_IRQ_LEN 4\n \n /* MC_CMD_INIT_EVQ_V2_IN msgrequest */\n #define\tMC_CMD_INIT_EVQ_V2_IN_LENMIN 44\n@@ -8346,17 +6901,22 @@\n #define\tMC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))\n /* Size, in entries */\n #define\tMC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0\n+#define\tMC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n  * local queue index.\n  */\n #define\tMC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4\n+#define\tMC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4\n /* The initial timer value. The load value is ignored if the timer mode is DIS.\n  */\n #define\tMC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4\n /* The reload value is ignored in one-shot modes */\n #define\tMC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4\n /* tbd */\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1\n@@ -8393,6 +6953,7 @@\n  */\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3\n #define\tMC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4\n /* enum: Disabled */\n #define\tMC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0\n /* enum: Immediate */\n@@ -8403,13 +6964,16 @@\n #define\tMC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3\n /* Target EVQ for wakeups if in wakeup mode. */\n #define\tMC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24\n+#define\tMC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4\n /* Target interrupt if in interrupting mode (note union with target EVQ). Use\n  * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test\n  * purposes.\n  */\n #define\tMC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24\n+#define\tMC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4\n /* Event Counter Mode. */\n #define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28\n+#define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4\n /* enum: Disabled */\n #define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0\n /* enum: Disabled */\n@@ -8420,6 +6984,7 @@\n #define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3\n /* Event queue packet count threshold. */\n #define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32\n+#define\tMC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4\n /* 64-bit address of 4k of 4k-aligned host memory buffer */\n #define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36\n #define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8\n@@ -8432,8 +6997,10 @@\n #define\tMC_CMD_INIT_EVQ_V2_OUT_LEN 8\n /* Only valid if INTRFLAG was true */\n #define\tMC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4\n /* Actual configuration applied on the card */\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1\n@@ -8482,17 +7049,22 @@\n #define\tMC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))\n /* Size, in entries */\n #define\tMC_CMD_INIT_RXQ_IN_SIZE_OFST 0\n+#define\tMC_CMD_INIT_RXQ_IN_SIZE_LEN 4\n /* The EVQ to send events to. This is an index originally specified to INIT_EVQ\n  */\n #define\tMC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4\n+#define\tMC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4\n /* The value to put in the event data. Check hardware spec. for valid range. */\n #define\tMC_CMD_INIT_RXQ_IN_LABEL_OFST 8\n+#define\tMC_CMD_INIT_RXQ_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n  * local queue index.\n  */\n #define\tMC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12\n+#define\tMC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_RXQ_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_RXQ_IN_FLAGS_LEN 4\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1\n@@ -8511,8 +7083,10 @@\n #define\tMC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n #define\tMC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20\n+#define\tMC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4\n /* The port ID associated with the v-adaptor which should contain this DMAQ. */\n #define\tMC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24\n+#define\tMC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4\n /* 64-bit address of 4k of 4k-aligned host memory buffer */\n #define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8\n@@ -8527,17 +7101,22 @@\n #define\tMC_CMD_INIT_RXQ_EXT_IN_LEN 544\n /* Size, in entries */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4\n /* The EVQ to send events to. This is an index originally specified to INIT_EVQ\n  */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4\n /* The value to put in the event data. Check hardware spec. for valid range. */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n  * local queue index.\n  */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1\n@@ -8573,8 +7152,10 @@\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4\n /* The port ID associated with the v-adaptor which should contain this DMAQ. */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4\n /* 64-bit address of 4k of 4k-aligned host memory buffer */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8\n@@ -8583,6 +7164,7 @@\n #define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64\n /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4\n \n /* MC_CMD_INIT_RXQ_OUT msgresponse */\n #define\tMC_CMD_INIT_RXQ_OUT_LEN 0\n@@ -8607,18 +7189,23 @@\n #define\tMC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))\n /* Size, in entries */\n #define\tMC_CMD_INIT_TXQ_IN_SIZE_OFST 0\n+#define\tMC_CMD_INIT_TXQ_IN_SIZE_LEN 4\n /* The EVQ to send events to. This is an index originally specified to\n  * INIT_EVQ.\n  */\n #define\tMC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4\n+#define\tMC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4\n /* The value to put in the event data. Check hardware spec. for valid range. */\n #define\tMC_CMD_INIT_TXQ_IN_LABEL_OFST 8\n+#define\tMC_CMD_INIT_TXQ_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n  * local queue index.\n  */\n #define\tMC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12\n+#define\tMC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_TXQ_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_TXQ_IN_FLAGS_LEN 4\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1\n@@ -8639,8 +7226,10 @@\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n #define\tMC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20\n+#define\tMC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4\n /* The port ID associated with the v-adaptor which should contain this DMAQ. */\n #define\tMC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24\n+#define\tMC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4\n /* 64-bit address of 4k of 4k-aligned host memory buffer */\n #define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8\n@@ -8655,18 +7244,23 @@\n #define\tMC_CMD_INIT_TXQ_EXT_IN_LEN 544\n /* Size, in entries */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4\n /* The EVQ to send events to. This is an index originally specified to\n  * INIT_EVQ.\n  */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4\n /* The value to put in the event data. Check hardware spec. for valid range. */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n  * local queue index.\n  */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1\n@@ -8691,8 +7285,10 @@\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4\n /* The port ID associated with the v-adaptor which should contain this DMAQ. */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4\n /* 64-bit address of 4k of 4k-aligned host memory buffer */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8\n@@ -8702,6 +7298,7 @@\n #define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64\n /* Flags related to Qbb flow control mode. */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4\n #define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0\n #define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1\n #define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1\n@@ -8729,6 +7326,7 @@\n  * passed to INIT_EVQ\n  */\n #define\tMC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0\n+#define\tMC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4\n \n /* MC_CMD_FINI_EVQ_OUT msgresponse */\n #define\tMC_CMD_FINI_EVQ_OUT_LEN 0\n@@ -8747,6 +7345,7 @@\n #define\tMC_CMD_FINI_RXQ_IN_LEN 4\n /* Instance of RXQ to destroy */\n #define\tMC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0\n+#define\tMC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4\n \n /* MC_CMD_FINI_RXQ_OUT msgresponse */\n #define\tMC_CMD_FINI_RXQ_OUT_LEN 0\n@@ -8765,6 +7364,7 @@\n #define\tMC_CMD_FINI_TXQ_IN_LEN 4\n /* Instance of TXQ to destroy */\n #define\tMC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0\n+#define\tMC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4\n \n /* MC_CMD_FINI_TXQ_OUT msgresponse */\n #define\tMC_CMD_FINI_TXQ_OUT_LEN 0\n@@ -8783,6 +7383,7 @@\n #define\tMC_CMD_DRIVER_EVENT_IN_LEN 12\n /* Handle of target EVQ */\n #define\tMC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0\n+#define\tMC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4\n /* Bits 0 - 63 of event */\n #define\tMC_CMD_DRIVER_EVENT_IN_DATA_OFST 4\n #define\tMC_CMD_DRIVER_EVENT_IN_DATA_LEN 8\n@@ -8809,6 +7410,7 @@\n #define\tMC_CMD_PROXY_CMD_IN_LEN 4\n /* The handle of the target function. */\n #define\tMC_CMD_PROXY_CMD_IN_TARGET_OFST 0\n+#define\tMC_CMD_PROXY_CMD_IN_TARGET_LEN 4\n #define\tMC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0\n #define\tMC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16\n #define\tMC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16\n@@ -8824,6 +7426,7 @@\n #define\tMC_PROXY_STATUS_BUFFER_LEN 16\n /* Handle allocated by the firmware for this proxy transaction */\n #define\tMC_PROXY_STATUS_BUFFER_HANDLE_OFST 0\n+#define\tMC_PROXY_STATUS_BUFFER_HANDLE_LEN 4\n /* enum: An invalid handle. */\n #define\tMC_PROXY_STATUS_BUFFER_HANDLE_INVALID  0x0\n #define\tMC_PROXY_STATUS_BUFFER_HANDLE_LBN 0\n@@ -8854,6 +7457,7 @@\n  * elevated privilege mask granted to the requesting function.\n  */\n #define\tMC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12\n+#define\tMC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4\n #define\tMC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96\n #define\tMC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32\n \n@@ -8871,6 +7475,7 @@\n /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */\n #define\tMC_CMD_PROXY_CONFIGURE_IN_LEN 108\n #define\tMC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4\n #define\tMC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0\n #define\tMC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1\n /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n@@ -8882,6 +7487,7 @@\n #define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8\n /* Must be a power of 2 */\n #define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4\n /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n  * of blocks, each of the size REPLY_BLOCK_SIZE.\n  */\n@@ -8891,6 +7497,7 @@\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20\n /* Must be a power of 2 */\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4\n /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n  * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if\n  * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.\n@@ -8901,8 +7508,10 @@\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32\n /* Must be a power of 2, or zero if this buffer is not provided */\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4\n /* Applies to all three buffers */\n #define\tMC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4\n /* A bit mask defining which MCDI operations may be proxied */\n #define\tMC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44\n #define\tMC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64\n@@ -8910,6 +7519,7 @@\n /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1\n /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n@@ -8921,6 +7531,7 @@\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8\n /* Must be a power of 2 */\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4\n /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n  * of blocks, each of the size REPLY_BLOCK_SIZE.\n  */\n@@ -8930,6 +7541,7 @@\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20\n /* Must be a power of 2 */\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4\n /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n  * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if\n  * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.\n@@ -8940,12 +7552,15 @@\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32\n /* Must be a power of 2, or zero if this buffer is not provided */\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4\n /* Applies to all three buffers */\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4\n /* A bit mask defining which MCDI operations may be proxied */\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4\n \n /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */\n #define\tMC_CMD_PROXY_CONFIGURE_OUT_LEN 0\n@@ -8966,7 +7581,9 @@\n /* MC_CMD_PROXY_COMPLETE_IN msgrequest */\n #define\tMC_CMD_PROXY_COMPLETE_IN_LEN 12\n #define\tMC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0\n+#define\tMC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4\n #define\tMC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4\n+#define\tMC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4\n /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply\n  * is stored in the REPLY_BUFF.\n  */\n@@ -8982,6 +7599,7 @@\n  */\n #define\tMC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3\n #define\tMC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8\n+#define\tMC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4\n \n /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */\n #define\tMC_CMD_PROXY_COMPLETE_OUT_LEN 0\n@@ -9002,17 +7620,22 @@\n #define\tMC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8\n /* Owner ID to use */\n #define\tMC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4\n /* Size of buffer table pages to use, in bytes (note that only a few values are\n  * legal on any specific hardware).\n  */\n #define\tMC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4\n \n /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */\n #define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12\n #define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4\n #define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4\n /* Buffer table IDs for use in DMA descriptors. */\n #define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4\n \n \n /***********************************/\n@@ -9029,10 +7652,13 @@\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4\n /* ID */\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4\n /* Num entries */\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4\n /* Buffer table entry address */\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8\n@@ -9056,48 +7682,11 @@\n /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */\n #define\tMC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4\n #define\tMC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0\n+#define\tMC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4\n \n /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */\n #define\tMC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0\n \n-/* PORT_CONFIG_ENTRY structuredef */\n-#define\tPORT_CONFIG_ENTRY_LEN 16\n-/* External port number (label) */\n-#define\tPORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0\n-#define\tPORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1\n-#define\tPORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0\n-#define\tPORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8\n-/* Port core location */\n-#define\tPORT_CONFIG_ENTRY_CORE_OFST 1\n-#define\tPORT_CONFIG_ENTRY_CORE_LEN 1\n-#define\tPORT_CONFIG_ENTRY_STANDALONE  0x0 /* enum */\n-#define\tPORT_CONFIG_ENTRY_MASTER  0x1 /* enum */\n-#define\tPORT_CONFIG_ENTRY_SLAVE  0x2 /* enum */\n-#define\tPORT_CONFIG_ENTRY_CORE_LBN 8\n-#define\tPORT_CONFIG_ENTRY_CORE_WIDTH 8\n-/* Internal number (HW resource) relative to the core */\n-#define\tPORT_CONFIG_ENTRY_INT_NUMBER_OFST 2\n-#define\tPORT_CONFIG_ENTRY_INT_NUMBER_LEN 1\n-#define\tPORT_CONFIG_ENTRY_INT_NUMBER_LBN 16\n-#define\tPORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8\n-/* Reserved */\n-#define\tPORT_CONFIG_ENTRY_RSVD_OFST 3\n-#define\tPORT_CONFIG_ENTRY_RSVD_LEN 1\n-#define\tPORT_CONFIG_ENTRY_RSVD_LBN 24\n-#define\tPORT_CONFIG_ENTRY_RSVD_WIDTH 8\n-/* Bitmask of KR lanes used by the port */\n-#define\tPORT_CONFIG_ENTRY_LANES_OFST 4\n-#define\tPORT_CONFIG_ENTRY_LANES_LBN 32\n-#define\tPORT_CONFIG_ENTRY_LANES_WIDTH 32\n-/* Port capabilities (MC_CMD_PHY_CAP_*) */\n-#define\tPORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8\n-#define\tPORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64\n-#define\tPORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32\n-/* Reserved (align to 16 bytes) */\n-#define\tPORT_CONFIG_ENTRY_RSVD2_OFST 12\n-#define\tPORT_CONFIG_ENTRY_RSVD2_LBN 96\n-#define\tPORT_CONFIG_ENTRY_RSVD2_WIDTH 32\n-\n \n /***********************************/\n /* MC_CMD_FILTER_OP\n@@ -9112,6 +7701,7 @@\n #define\tMC_CMD_FILTER_OP_IN_LEN 108\n /* identifies the type of operation requested */\n #define\tMC_CMD_FILTER_OP_IN_OP_OFST 0\n+#define\tMC_CMD_FILTER_OP_IN_OP_LEN 4\n /* enum: single-recipient filter insert */\n #define\tMC_CMD_FILTER_OP_IN_OP_INSERT  0x0\n /* enum: single-recipient filter remove */\n@@ -9132,8 +7722,10 @@\n /* The port ID associated with the v-adaptor which should contain this filter.\n  */\n #define\tMC_CMD_FILTER_OP_IN_PORT_ID_OFST 12\n+#define\tMC_CMD_FILTER_OP_IN_PORT_ID_LEN 4\n /* fields to include in match criteria */\n #define\tMC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4\n #define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0\n #define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1\n #define\tMC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1\n@@ -9164,6 +7756,7 @@\n #define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1\n /* receive destination */\n #define\tMC_CMD_FILTER_OP_IN_RX_DEST_OFST 20\n+#define\tMC_CMD_FILTER_OP_IN_RX_DEST_LEN 4\n /* enum: drop packets */\n #define\tMC_CMD_FILTER_OP_IN_RX_DEST_DROP  0x0\n /* enum: receive to host */\n@@ -9176,8 +7769,10 @@\n #define\tMC_CMD_FILTER_OP_IN_RX_DEST_TX1  0x4\n /* receive queue handle (for multiple queue modes, this is the base queue) */\n #define\tMC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24\n+#define\tMC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4\n /* receive mode */\n #define\tMC_CMD_FILTER_OP_IN_RX_MODE_OFST 28\n+#define\tMC_CMD_FILTER_OP_IN_RX_MODE_LEN 4\n /* enum: receive to just the specified queue */\n #define\tMC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE  0x0\n /* enum: receive to multiple queues using RSS context */\n@@ -9192,13 +7787,16 @@\n  * MC_CMD_DOT1P_MAPPING_ALLOC.\n  */\n #define\tMC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32\n+#define\tMC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4\n /* transmit domain (reserved; set to 0) */\n #define\tMC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36\n+#define\tMC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4\n /* transmit destination (either set the MAC and/or PM bits for explicit\n  * control, or set this field to TX_DEST_DEFAULT for sensible default\n  * behaviour)\n  */\n #define\tMC_CMD_FILTER_OP_IN_TX_DEST_OFST 40\n+#define\tMC_CMD_FILTER_OP_IN_TX_DEST_LEN 4\n /* enum: request default behaviour (based on filter type) */\n #define\tMC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT  0xffffffff\n #define\tMC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0\n@@ -9231,8 +7829,10 @@\n #define\tMC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2\n /* Firmware defined register 0 to match (reserved; set to 0) */\n #define\tMC_CMD_FILTER_OP_IN_FWDEF0_OFST 68\n+#define\tMC_CMD_FILTER_OP_IN_FWDEF0_LEN 4\n /* Firmware defined register 1 to match (reserved; set to 0) */\n #define\tMC_CMD_FILTER_OP_IN_FWDEF1_OFST 72\n+#define\tMC_CMD_FILTER_OP_IN_FWDEF1_LEN 4\n /* source IP address to match (as bytes in network order; set last 12 bytes to\n  * 0 for IPv4 address)\n  */\n@@ -9251,6 +7851,7 @@\n #define\tMC_CMD_FILTER_OP_EXT_IN_LEN 172\n /* identifies the type of operation requested */\n #define\tMC_CMD_FILTER_OP_EXT_IN_OP_OFST 0\n+#define\tMC_CMD_FILTER_OP_EXT_IN_OP_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_FILTER_OP_IN/OP */\n /* filter handle (for remove / unsubscribe operations) */\n@@ -9261,8 +7862,10 @@\n /* The port ID associated with the v-adaptor which should contain this filter.\n  */\n #define\tMC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12\n+#define\tMC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4\n /* fields to include in match criteria */\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1\n@@ -9321,6 +7924,7 @@\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1\n /* receive destination */\n #define\tMC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4\n /* enum: drop packets */\n #define\tMC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP  0x0\n /* enum: receive to host */\n@@ -9333,8 +7937,10 @@\n #define\tMC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1  0x4\n /* receive queue handle (for multiple queue modes, this is the base queue) */\n #define\tMC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4\n /* receive mode */\n #define\tMC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4\n /* enum: receive to just the specified queue */\n #define\tMC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE  0x0\n /* enum: receive to multiple queues using RSS context */\n@@ -9349,13 +7955,16 @@\n  * MC_CMD_DOT1P_MAPPING_ALLOC.\n  */\n #define\tMC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32\n+#define\tMC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4\n /* transmit domain (reserved; set to 0) */\n #define\tMC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4\n /* transmit destination (either set the MAC and/or PM bits for explicit\n  * control, or set this field to TX_DEST_DEFAULT for sensible default\n  * behaviour)\n  */\n #define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4\n /* enum: request default behaviour (based on filter type) */\n #define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT  0xffffffff\n #define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0\n@@ -9388,11 +7997,13 @@\n #define\tMC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2\n /* Firmware defined register 0 to match (reserved; set to 0) */\n #define\tMC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68\n+#define\tMC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4\n /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP\n  * protocol is GRE) to match (as bytes in network order; set last byte to 0 for\n  * VXLAN/NVGRE, or 1 for Geneve)\n  */\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24\n@@ -9458,10 +8069,12 @@\n  * to 0)\n  */\n #define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4\n /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set\n  * to 0)\n  */\n #define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136\n+#define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4\n /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network\n  * order; set last 12 bytes to 0 for IPv4 address)\n  */\n@@ -9477,6 +8090,7 @@\n #define\tMC_CMD_FILTER_OP_OUT_LEN 12\n /* identifies the type of operation requested */\n #define\tMC_CMD_FILTER_OP_OUT_OP_OFST 0\n+#define\tMC_CMD_FILTER_OP_OUT_OP_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_FILTER_OP_IN/OP */\n /* Returned filter handle (for insert / subscribe operations). Note that these\n@@ -9496,6 +8110,7 @@\n #define\tMC_CMD_FILTER_OP_EXT_OUT_LEN 12\n /* identifies the type of operation requested */\n #define\tMC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_FILTER_OP_EXT_IN/OP */\n /* Returned filter handle (for insert / subscribe operations). Note that these\n@@ -9523,6 +8138,7 @@\n #define\tMC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4\n /* identifies the type of operation requested */\n #define\tMC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4\n /* enum: read the list of supported RX filter matches */\n #define\tMC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES  0x1\n /* enum: read flags indicating restrictions on filter insertion for the calling\n@@ -9545,10 +8161,12 @@\n #define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))\n /* identifies the type of operation requested */\n #define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */\n /* number of supported match types */\n #define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4\n /* array of supported match types (valid MATCH_FIELDS values for\n  * MC_CMD_FILTER_OP) sorted in decreasing priority order\n  */\n@@ -9561,10 +8179,12 @@\n #define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8\n /* identifies the type of operation requested */\n #define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0\n+#define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */\n /* bitfield of filter insertion restrictions */\n #define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4\n+#define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4\n #define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0\n #define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1\n \n@@ -9578,28 +8198,37 @@\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36\n /* identifies the type of operation requested */\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */\n /* a version number representing the set of rule lookups that are implemented\n  * by the currently running firmware\n  */\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_LEN 4\n /* enum: implements lookup sequences described in SF-114946-SW draft C */\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C  0x0\n /* the number of nodes in the subnet map */\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_LEN 4\n /* the number of entries in one subnet map node */\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_LEN 4\n /* minimum valid value for a subnet ID in a subnet map leaf */\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_LEN 4\n /* maximum valid value for a subnet ID in a subnet map leaf */\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_LEN 4\n /* the number of entries in the local and remote port range maps */\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_LEN 4\n /* minimum valid value for a portrange ID in a port range map leaf */\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_LEN 4\n /* maximum valid value for a portrange ID in a port range map leaf */\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32\n+#define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_LEN 4\n \n \n /***********************************/\n@@ -9607,7 +8236,9 @@\n  * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.\n  * Please note that this interface is only of use to debug tools which have\n  * knowledge of firmware and hardware data structures; nothing here is intended\n- * for use by normal driver code.\n+ * for use by normal driver code. Note that although this command is in the\n+ * Admin privilege group, in tamperproof adapters, only read operations are\n+ * permitted.\n  */\n #define\tMC_CMD_PARSER_DISP_RW 0xe5\n #undef\tMC_CMD_0xe5_PRIVILEGE_CTG\n@@ -9618,11 +8249,16 @@\n #define\tMC_CMD_PARSER_DISP_RW_IN_LEN 32\n /* identifies the target of the operation */\n #define\tMC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0\n+#define\tMC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4\n /* enum: RX dispatcher CPU */\n #define\tMC_CMD_PARSER_DISP_RW_IN_RX_DICPU  0x0\n /* enum: TX dispatcher CPU */\n #define\tMC_CMD_PARSER_DISP_RW_IN_TX_DICPU  0x1\n-/* enum: Lookup engine (with original metadata format) */\n+/* enum: Lookup engine (with original metadata format). Deprecated; used only\n+ * by cmdclient as a fallback for very old Huntington firmware, and not\n+ * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA\n+ * instead.\n+ */\n #define\tMC_CMD_PARSER_DISP_RW_IN_LUE  0x2\n /* enum: Lookup engine (with requested metadata format) */\n #define\tMC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA  0x3\n@@ -9634,26 +8270,37 @@\n #define\tMC_CMD_PARSER_DISP_RW_IN_MISC_STATE  0x5\n /* identifies the type of operation requested */\n #define\tMC_CMD_PARSER_DISP_RW_IN_OP_OFST 4\n-/* enum: read a word of DICPU DMEM or a LUE entry */\n+#define\tMC_CMD_PARSER_DISP_RW_IN_OP_LEN 4\n+/* enum: Read a word of DICPU DMEM or a LUE entry */\n #define\tMC_CMD_PARSER_DISP_RW_IN_READ  0x0\n-/* enum: write a word of DICPU DMEM or a LUE entry */\n+/* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on\n+ * tamperproof adapters.\n+ */\n #define\tMC_CMD_PARSER_DISP_RW_IN_WRITE  0x1\n-/* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */\n+/* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not\n+ * permitted on tamperproof adapters.\n+ */\n #define\tMC_CMD_PARSER_DISP_RW_IN_RMW  0x2\n /* data memory address (DICPU targets) or LUE index (LUE targets) */\n #define\tMC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8\n+#define\tMC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4\n /* selector (for MISC_STATE target) */\n #define\tMC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8\n+#define\tMC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4\n /* enum: Port to datapath mapping */\n #define\tMC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING  0x1\n /* value to write (for DMEM writes) */\n #define\tMC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12\n+#define\tMC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4\n /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */\n #define\tMC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12\n+#define\tMC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4\n /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */\n #define\tMC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16\n+#define\tMC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4\n /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */\n #define\tMC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12\n+#define\tMC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4\n /* value to write (for LUE writes) */\n #define\tMC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12\n #define\tMC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20\n@@ -9662,6 +8309,7 @@\n #define\tMC_CMD_PARSER_DISP_RW_OUT_LEN 52\n /* value read (for DMEM reads) */\n #define\tMC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0\n+#define\tMC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4\n /* value read (for LUE reads) */\n #define\tMC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0\n #define\tMC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20\n@@ -9707,6 +8355,7 @@\n #define\tMC_CMD_SET_PF_COUNT_IN_LEN 4\n /* New number of PFs on the device. */\n #define\tMC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0\n+#define\tMC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4\n \n /* MC_CMD_SET_PF_COUNT_OUT msgresponse */\n #define\tMC_CMD_SET_PF_COUNT_OUT_LEN 0\n@@ -9728,6 +8377,7 @@\n #define\tMC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4\n /* Identifies the port assignment for this function. */\n #define\tMC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0\n+#define\tMC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4\n \n \n /***********************************/\n@@ -9743,6 +8393,7 @@\n #define\tMC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4\n /* Identifies the port assignment for this function. */\n #define\tMC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0\n+#define\tMC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4\n \n /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */\n #define\tMC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0\n@@ -9761,8 +8412,10 @@\n #define\tMC_CMD_ALLOC_VIS_IN_LEN 8\n /* The minimum number of VIs that is acceptable */\n #define\tMC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0\n+#define\tMC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4\n /* The maximum number of VIs that would be useful */\n #define\tMC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4\n+#define\tMC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4\n \n /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.\n  * Use extended version in new code.\n@@ -9770,21 +8423,26 @@\n #define\tMC_CMD_ALLOC_VIS_OUT_LEN 8\n /* The number of VIs allocated on this function */\n #define\tMC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0\n+#define\tMC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4\n /* The base absolute VI number allocated to this function. Required to\n  * correctly interpret wakeup events.\n  */\n #define\tMC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4\n+#define\tMC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4\n \n /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */\n #define\tMC_CMD_ALLOC_VIS_EXT_OUT_LEN 12\n /* The number of VIs allocated on this function */\n #define\tMC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0\n+#define\tMC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4\n /* The base absolute VI number allocated to this function. Required to\n  * correctly interpret wakeup events.\n  */\n #define\tMC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4\n+#define\tMC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4\n /* Function's port vi_shift value (always 0 on Huntington) */\n #define\tMC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8\n+#define\tMC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4\n \n \n /***********************************/\n@@ -9820,15 +8478,20 @@\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_LEN 20\n /* Number of VFs currently enabled. */\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4\n /* Max number of VFs before sriov stride and offset may need to be changed. */\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1\n /* RID offset of first VF from PF. */\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4\n /* RID offset of each subsequent VF from the previous. */\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4\n \n \n /***********************************/\n@@ -9844,19 +8507,24 @@\n #define\tMC_CMD_SET_SRIOV_CFG_IN_LEN 20\n /* Number of VFs currently enabled. */\n #define\tMC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4\n /* Max number of VFs before sriov stride and offset may need to be changed. */\n #define\tMC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4\n #define\tMC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4\n #define\tMC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0\n #define\tMC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1\n /* RID offset of first VF from PF, or 0 for no change, or\n  * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.\n  */\n #define\tMC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4\n /* RID offset of each subsequent VF from the previous, 0 for no change, or\n  * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.\n  */\n #define\tMC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4\n \n /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */\n #define\tMC_CMD_SET_SRIOV_CFG_OUT_LEN 0\n@@ -9879,12 +8547,15 @@\n #define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12\n /* The number of VIs allocated on this function */\n #define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0\n+#define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4\n /* The base absolute VI number allocated to this function. Required to\n  * correctly interpret wakeup events.\n  */\n #define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4\n+#define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4\n /* Function's port vi_shift value (always 0 on Huntington) */\n #define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8\n+#define\tMC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4\n \n \n /***********************************/\n@@ -9900,6 +8571,7 @@\n #define\tMC_CMD_DUMP_VI_STATE_IN_LEN 4\n /* The VI number to query. */\n #define\tMC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0\n+#define\tMC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4\n \n /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_LEN 96\n@@ -9933,6 +8605,7 @@\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24\n /* Combined metadata field. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16\n@@ -10015,6 +8688,7 @@\n #define\tMC_CMD_ALLOC_PIOBUF_OUT_LEN 4\n /* Handle for allocated push I/O buffer. */\n #define\tMC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0\n+#define\tMC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4\n \n \n /***********************************/\n@@ -10030,6 +8704,7 @@\n #define\tMC_CMD_FREE_PIOBUF_IN_LEN 4\n /* Handle for allocated push I/O buffer. */\n #define\tMC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0\n+#define\tMC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4\n \n /* MC_CMD_FREE_PIOBUF_OUT msgresponse */\n #define\tMC_CMD_FREE_PIOBUF_OUT_LEN 0\n@@ -10048,6 +8723,7 @@\n #define\tMC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4\n /* VI number to get information for. */\n #define\tMC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4\n \n /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */\n #define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4\n@@ -10070,6 +8746,7 @@\n #define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19\n #define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1\n #define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4\n \n \n /***********************************/\n@@ -10085,6 +8762,7 @@\n #define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8\n /* VI number to set information for. */\n #define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4\n /* Transaction processing steering hint 1 for use with the Rx Queue. */\n #define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4\n #define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1\n@@ -10104,6 +8782,7 @@\n #define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51\n #define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1\n #define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4\n \n /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */\n #define\tMC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0\n@@ -10121,6 +8800,7 @@\n /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4\n /* enum: MISC. */\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC  0x0\n /* enum: IDO. */\n@@ -10133,10 +8813,12 @@\n /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */\n /* Amalgamated TLP info word. */\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1\n@@ -10185,10 +8867,12 @@\n /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */\n /* Amalgamated TLP info word. */\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0\n@@ -10256,6 +8940,7 @@\n  * in a command from the host.)\n  */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE     0x0 /* enum */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET    0x1 /* enum */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS    0x2 /* enum */\n@@ -10265,6 +8950,7 @@\n  * mc_flash_layout.h.)\n  */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4\n /* enum: Valid in phase 2 (PHASE_IMEMS) only */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT  0x0\n /* enum: Valid in phase 2 (PHASE_IMEMS) only */\n@@ -10301,12 +8987,14 @@\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL  0xffffffff\n /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4\n /* enum: Last chunk, containing checksum rather than data */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST  0xffffffff\n /* enum: Abort download of this item */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT  0xfffffffe\n /* Length of this chunk in bytes */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4\n /* Data for this chunk */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16\n #define\tMC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4\n@@ -10317,8 +9005,10 @@\n #define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8\n /* Same as MC_CMD_ERR field, but included as 0 in success cases */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4\n /* Extra status information */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4\n /* enum: Code download OK, completed. */\n #define\tMC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE  0x0\n /* enum: Code download aborted as requested. */\n@@ -10356,6 +9046,7 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_LEN 20\n /* First word of flags. */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4\n #define\tMC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4\n@@ -10423,6 +9114,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY  0x1\n /* enum: Packed stream RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM  0x2\n+/* enum: Rules engine RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE  0x5\n /* enum: BIST RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST  0x10a\n /* enum: RXDP Test firmware image 1 */\n@@ -10443,6 +9136,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL  0x108\n /* enum: RXDP Test firmware image 9 */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY  0x10b\n+/* enum: RXDP Test firmware image 10 */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW  0x10c\n /* TxDPCPU firmware id. */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2\n@@ -10452,6 +9147,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY  0x1\n /* enum: High packet rate TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE  0x3\n+/* enum: Rules engine TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE  0x5\n /* enum: BIST TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST  0x12d\n /* enum: TXDP Test firmware image 1 */\n@@ -10539,8 +9236,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n /* Hardware capabilities of NIC */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4\n /* Licensed capabilities */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4\n \n /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */\n #define\tMC_CMD_GET_CAPABILITIES_V2_IN_LEN 0\n@@ -10549,6 +9248,7 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72\n /* First word of flags. */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4\n@@ -10616,6 +9316,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY  0x1\n /* enum: Packed stream RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM  0x2\n+/* enum: Rules engine RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE  0x5\n /* enum: BIST RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST  0x10a\n /* enum: RXDP Test firmware image 1 */\n@@ -10636,6 +9338,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL  0x108\n /* enum: RXDP Test firmware image 9 */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY  0x10b\n+/* enum: RXDP Test firmware image 10 */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW  0x10c\n /* TxDPCPU firmware id. */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2\n@@ -10645,6 +9349,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY  0x1\n /* enum: High packet rate TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE  0x3\n+/* enum: Rules engine TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE  0x5\n /* enum: BIST TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST  0x12d\n /* enum: TXDP Test firmware image 1 */\n@@ -10732,10 +9438,13 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n /* Hardware capabilities of NIC */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4\n /* Licensed capabilities */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4\n /* Second word of flags. Not present on older firmware (check the length). */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1\n@@ -10826,6 +9535,7 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76\n /* First word of flags. */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4\n@@ -10893,6 +9603,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY  0x1\n /* enum: Packed stream RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM  0x2\n+/* enum: Rules engine RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE  0x5\n /* enum: BIST RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST  0x10a\n /* enum: RXDP Test firmware image 1 */\n@@ -10913,6 +9625,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL  0x108\n /* enum: RXDP Test firmware image 9 */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY  0x10b\n+/* enum: RXDP Test firmware image 10 */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW  0x10c\n /* TxDPCPU firmware id. */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2\n@@ -10922,6 +9636,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY  0x1\n /* enum: High packet rate TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE  0x3\n+/* enum: Rules engine TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE  0x5\n /* enum: BIST TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST  0x12d\n /* enum: TXDP Test firmware image 1 */\n@@ -11009,10 +9725,13 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n /* Hardware capabilities of NIC */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4\n /* Licensed capabilities */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4\n /* Second word of flags. Not present on older firmware (check the length). */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1\n@@ -11124,6 +9843,326 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2\n \n+/* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78\n+/* First word of flags. */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1\n+/* RxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP  0x0\n+/* enum: Low latency RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY  0x1\n+/* enum: Packed stream RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM  0x2\n+/* enum: Rules engine RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE  0x5\n+/* enum: BIST RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST  0x10a\n+/* enum: RXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH  0x101\n+/* enum: RXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD  0x102\n+/* enum: RXDP Test firmware image 3 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST  0x103\n+/* enum: RXDP Test firmware image 4 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE  0x104\n+/* enum: RXDP Test firmware image 5 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE  0x105\n+/* enum: RXDP Test firmware image 6 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS  0x106\n+/* enum: RXDP Test firmware image 7 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT  0x107\n+/* enum: RXDP Test firmware image 8 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL  0x108\n+/* enum: RXDP Test firmware image 9 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY  0x10b\n+/* enum: RXDP Test firmware image 10 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW  0x10c\n+/* TxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP  0x0\n+/* enum: Low latency TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY  0x1\n+/* enum: High packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE  0x3\n+/* enum: Rules engine TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE  0x5\n+/* enum: BIST TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST  0x12d\n+/* enum: TXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT  0x101\n+/* enum: TXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS  0x102\n+/* enum: TXDP CSR bus test firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR  0x103\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED  0x0\n+/* enum: Trivial RX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT  0x1\n+/* enum: RX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT  0x2\n+/* enum: Full featured RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED  0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH  0x3\n+/* enum: siena_compat variant RX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM  0x4\n+/* enum: Low latency RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY  0x5\n+/* enum: Packed stream RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM  0x6\n+/* enum: RX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF  0x7\n+/* enum: Rules engine RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE  0x8\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n+/* enum: RX PD firmware parsing but not filtering network overlay tunnel\n+ * encapsulations (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY  0xf\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED  0x0\n+/* enum: Trivial TX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT  0x1\n+/* enum: TX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT  0x2\n+/* enum: Full featured TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED  0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH  0x3\n+/* enum: siena_compat variant TX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM  0x4\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY  0x5 /* enum */\n+/* enum: TX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF  0x7\n+/* enum: Rules engine TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE  0x8\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE  0xe\n+/* Hardware capabilities of NIC */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4\n+/* Licensed capabilities */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4\n+/* Second word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1\n+/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present\n+ * on older firmware (check the length).\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2\n+/* One byte per PF containing the number of the external port assigned to this\n+ * PF, indexed by PF number. Special values indicate that a PF is either not\n+ * present or not assigned.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED  0xff\n+/* enum: PF does not exist. */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT  0xfe\n+/* enum: PF does exist but is not assigned to any external port. */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED  0xfd\n+/* enum: This value indicates that PF is assigned, but it cannot be expressed\n+ * in this field. It is intended for a possible future situation where a more\n+ * complex scheme of PFs to ports mapping is being used. The future driver\n+ * should look for a new field supporting the new scheme. The current/old\n+ * driver should treat this value as PF_NOT_ASSIGNED.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT  0xfc\n+/* One byte per PF containing the number of its VFs, indexed by PF number. A\n+ * special value indicates that a PF is not present.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+/*               MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED  0xff */\n+/* enum: PF does not exist. */\n+/*               MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT  0xfe */\n+/* Number of VIs available for each external port */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4\n+/* Size of RX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ RX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1\n+/* Size of TX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ TX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1\n+/* Total number of available PIO buffers */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2\n+/* Size of a single PIO buffer */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2\n+/* On chips later than Medford the amount of address space assigned to each VI\n+ * is configurable. This is a global setting that the driver must query to\n+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available\n+ * with 8k VI windows.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1\n+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.\n+ * CTPIO is not mapped.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K   0x0\n+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K  0x1\n+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K  0x2\n+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1\n+/* Number of buffers per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2\n+/* Entry count in the MAC stats array, including the final GENERATION_END\n+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to\n+ * hold at least this many 64-bit stats values, if they wish to receive all\n+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the\n+ * stats array returned will be truncated.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2\n+\n \n /***********************************/\n /* MC_CMD_V2_EXTN\n@@ -11144,7 +10183,16 @@\n #define\tMC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16\n #define\tMC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10\n #define\tMC_CMD_V2_EXTN_IN_UNUSED2_LBN 26\n-#define\tMC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6\n+#define\tMC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2\n+/* Type of command/response */\n+#define\tMC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28\n+#define\tMC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4\n+/* enum: MCDI command directed to or response originating from the MC. */\n+#define\tMC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC  0x0\n+/* enum: MCDI command directed to a TSA controller. MCDI responses of this type\n+ * are not defined.\n+ */\n+#define\tMC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA  0x1\n \n \n /***********************************/\n@@ -11163,6 +10211,7 @@\n #define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4\n /* the bucket id */\n #define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0\n+#define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4\n \n \n /***********************************/\n@@ -11178,6 +10227,7 @@\n #define\tMC_CMD_TCM_BUCKET_FREE_IN_LEN 4\n /* the bucket id */\n #define\tMC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0\n+#define\tMC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4\n \n /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */\n #define\tMC_CMD_TCM_BUCKET_FREE_OUT_LEN 0\n@@ -11196,17 +10246,22 @@\n #define\tMC_CMD_TCM_BUCKET_INIT_IN_LEN 8\n /* the bucket id */\n #define\tMC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0\n+#define\tMC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4\n /* the rate in mbps */\n #define\tMC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4\n+#define\tMC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4\n \n /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */\n #define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12\n /* the bucket id */\n #define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4\n /* the rate in mbps */\n #define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4\n /* the desired maximum fill level */\n #define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4\n \n /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */\n #define\tMC_CMD_TCM_BUCKET_INIT_OUT_LEN 0\n@@ -11225,10 +10280,13 @@\n #define\tMC_CMD_TCM_TXQ_INIT_IN_LEN 28\n /* the txq id */\n #define\tMC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4\n /* the static priority associated with the txq */\n #define\tMC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4\n /* bitmask of the priority queues this txq is inserted into when inserted. */\n #define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4\n #define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0\n #define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1\n #define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1\n@@ -11237,25 +10295,32 @@\n #define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1\n /* the reaction point (RP) bucket */\n #define\tMC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4\n /* an already reserved bucket (typically set to bucket associated with outer\n  * vswitch)\n  */\n #define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4\n /* an already reserved bucket (typically set to bucket associated with inner\n  * vswitch)\n  */\n #define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4\n /* the min bucket (typically for ETS/minimum bandwidth) */\n #define\tMC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4\n \n /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32\n /* the txq id */\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4\n /* the static priority associated with the txq */\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4\n /* bitmask of the priority queues this txq is inserted into when inserted. */\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1\n@@ -11264,18 +10329,23 @@\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1\n /* the reaction point (RP) bucket */\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4\n /* an already reserved bucket (typically set to bucket associated with outer\n  * vswitch)\n  */\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4\n /* an already reserved bucket (typically set to bucket associated with inner\n  * vswitch)\n  */\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4\n /* the min bucket (typically for ETS/minimum bandwidth) */\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4\n /* the static priority associated with the txq */\n #define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4\n \n /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */\n #define\tMC_CMD_TCM_TXQ_INIT_OUT_LEN 0\n@@ -11294,8 +10364,10 @@\n #define\tMC_CMD_LINK_PIOBUF_IN_LEN 8\n /* Handle for allocated push I/O buffer. */\n #define\tMC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0\n+#define\tMC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4\n /* Function Local Instance (VI) number. */\n #define\tMC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4\n+#define\tMC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4\n \n /* MC_CMD_LINK_PIOBUF_OUT msgresponse */\n #define\tMC_CMD_LINK_PIOBUF_OUT_LEN 0\n@@ -11314,6 +10386,7 @@\n #define\tMC_CMD_UNLINK_PIOBUF_IN_LEN 4\n /* Function Local Instance (VI) number. */\n #define\tMC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0\n+#define\tMC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4\n \n /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */\n #define\tMC_CMD_UNLINK_PIOBUF_OUT_LEN 0\n@@ -11332,8 +10405,10 @@\n #define\tMC_CMD_VSWITCH_ALLOC_IN_LEN 16\n /* The port to connect to the v-switch's upstream port. */\n #define\tMC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4\n /* The type of v-switch to create. */\n #define\tMC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4\n /* enum: VLAN */\n #define\tMC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN  0x1\n /* enum: VEB */\n@@ -11346,6 +10421,7 @@\n #define\tMC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST  0x5\n /* Flags controlling v-port creation */\n #define\tMC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4\n #define\tMC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0\n #define\tMC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1\n /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,\n@@ -11356,6 +10432,7 @@\n  * v-ports with this number of tags.\n  */\n #define\tMC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4\n \n /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */\n #define\tMC_CMD_VSWITCH_ALLOC_OUT_LEN 0\n@@ -11374,6 +10451,7 @@\n #define\tMC_CMD_VSWITCH_FREE_IN_LEN 4\n /* The port to which the v-switch is connected. */\n #define\tMC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4\n \n /* MC_CMD_VSWITCH_FREE_OUT msgresponse */\n #define\tMC_CMD_VSWITCH_FREE_OUT_LEN 0\n@@ -11394,6 +10472,7 @@\n #define\tMC_CMD_VSWITCH_QUERY_IN_LEN 4\n /* The port to which the v-switch is connected. */\n #define\tMC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4\n \n /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */\n #define\tMC_CMD_VSWITCH_QUERY_OUT_LEN 0\n@@ -11412,8 +10491,10 @@\n #define\tMC_CMD_VPORT_ALLOC_IN_LEN 20\n /* The port to which the v-switch is connected. */\n #define\tMC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4\n /* The type of the new v-port. */\n #define\tMC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4\n+#define\tMC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4\n /* enum: VLAN (obsolete) */\n #define\tMC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN  0x1\n /* enum: VEB (obsolete) */\n@@ -11434,6 +10515,7 @@\n #define\tMC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST  0x6\n /* Flags controlling v-port creation */\n #define\tMC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8\n+#define\tMC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4\n #define\tMC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0\n #define\tMC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1\n #define\tMC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1\n@@ -11443,8 +10525,10 @@\n  * v-switch.\n  */\n #define\tMC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12\n+#define\tMC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4\n /* The actual VLAN tags to insert/remove */\n #define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16\n+#define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4\n #define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0\n #define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16\n #define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16\n@@ -11454,6 +10538,7 @@\n #define\tMC_CMD_VPORT_ALLOC_OUT_LEN 4\n /* The handle of the new v-port */\n #define\tMC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0\n+#define\tMC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4\n \n \n /***********************************/\n@@ -11469,6 +10554,7 @@\n #define\tMC_CMD_VPORT_FREE_IN_LEN 4\n /* The handle of the v-port */\n #define\tMC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0\n+#define\tMC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4\n \n /* MC_CMD_VPORT_FREE_OUT msgresponse */\n #define\tMC_CMD_VPORT_FREE_OUT_LEN 0\n@@ -11487,18 +10573,23 @@\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_LEN 30\n /* The port to connect to the v-adaptor's port. */\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4\n /* Flags controlling v-adaptor creation */\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n /* The number of VLAN tags to strip on receive */\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4\n /* The number of VLAN tags to transparently insert/remove. */\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4\n /* The actual VLAN tags to insert/remove */\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16\n@@ -11526,6 +10617,7 @@\n #define\tMC_CMD_VADAPTOR_FREE_IN_LEN 4\n /* The port to which the v-adaptor is connected. */\n #define\tMC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4\n \n /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */\n #define\tMC_CMD_VADAPTOR_FREE_OUT_LEN 0\n@@ -11544,6 +10636,7 @@\n #define\tMC_CMD_VADAPTOR_SET_MAC_IN_LEN 10\n /* The port to which the v-adaptor is connected. */\n #define\tMC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4\n /* The new MAC address to assign to this v-adaptor */\n #define\tMC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4\n #define\tMC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6\n@@ -11565,6 +10658,7 @@\n #define\tMC_CMD_VADAPTOR_GET_MAC_IN_LEN 4\n /* The port to which the v-adaptor is connected. */\n #define\tMC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4\n \n /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */\n #define\tMC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6\n@@ -11586,15 +10680,19 @@\n #define\tMC_CMD_VADAPTOR_QUERY_IN_LEN 4\n /* The port to which the v-adaptor is connected. */\n #define\tMC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4\n \n /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */\n #define\tMC_CMD_VADAPTOR_QUERY_OUT_LEN 12\n /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */\n #define\tMC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0\n+#define\tMC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4\n /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */\n #define\tMC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4\n+#define\tMC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4\n /* The number of VLAN tags that may still be added */\n #define\tMC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8\n+#define\tMC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4\n \n \n /***********************************/\n@@ -11610,8 +10708,10 @@\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_LEN 8\n /* The port to assign. */\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4\n /* The target function to modify. */\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16\n@@ -11633,9 +10733,13 @@\n /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */\n #define\tMC_CMD_RDWR_A64_REGIONS_IN_LEN 17\n #define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4\n #define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4\n #define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4\n #define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12\n+#define\tMC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4\n /* Write enable bits 0-3, set to write, clear to read. */\n #define\tMC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128\n #define\tMC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4\n@@ -11647,9 +10751,13 @@\n  */\n #define\tMC_CMD_RDWR_A64_REGIONS_OUT_LEN 16\n #define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0\n+#define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4\n #define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4\n+#define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4\n #define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8\n+#define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4\n #define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12\n+#define\tMC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4\n \n \n /***********************************/\n@@ -11665,11 +10773,13 @@\n #define\tMC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4\n /* The handle of the owning upstream port */\n #define\tMC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4\n \n /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */\n #define\tMC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4\n /* The handle of the new Onload stack */\n #define\tMC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0\n+#define\tMC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4\n \n \n /***********************************/\n@@ -11685,6 +10795,7 @@\n #define\tMC_CMD_ONLOAD_STACK_FREE_IN_LEN 4\n /* The handle of the Onload stack */\n #define\tMC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0\n+#define\tMC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4\n \n /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */\n #define\tMC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0\n@@ -11703,8 +10814,10 @@\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12\n /* The handle of the owning upstream port */\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4\n /* The type of context to allocate */\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4\n /* enum: Allocate a context for exclusive use. The key and indirection table\n  * must be explicitly configured.\n  */\n@@ -11718,6 +10831,7 @@\n  * in the indirection table will be in the range 0 to NUM_QUEUES-1.\n  */\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4\n \n /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4\n@@ -11726,6 +10840,7 @@\n  * handle.\n  */\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4\n /* enum: guaranteed invalid RSS context handle value */\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID  0xffffffff\n \n@@ -11743,6 +10858,7 @@\n #define\tMC_CMD_RSS_CONTEXT_FREE_IN_LEN 4\n /* The handle of the RSS context */\n #define\tMC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4\n \n /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */\n #define\tMC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0\n@@ -11761,6 +10877,7 @@\n #define\tMC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44\n /* The handle of the RSS context */\n #define\tMC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4\n /* The 40-byte Toeplitz hash key (TBD endianness issues?) */\n #define\tMC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40\n@@ -11782,6 +10899,7 @@\n #define\tMC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4\n /* The handle of the RSS context */\n #define\tMC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4\n \n /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */\n #define\tMC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44\n@@ -11803,6 +10921,7 @@\n #define\tMC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132\n /* The handle of the RSS context */\n #define\tMC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4\n /* The 128-byte indirection table (1 byte per entry) */\n #define\tMC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128\n@@ -11824,6 +10943,7 @@\n #define\tMC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4\n /* The handle of the RSS context */\n #define\tMC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4\n \n /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */\n #define\tMC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132\n@@ -11845,6 +10965,7 @@\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8\n /* The handle of the RSS context */\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4\n /* Hash control flags. The _EN bits are always supported, but new modes are\n  * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:\n  * in this case, the MODE fields may be set to non-zero values, and will take\n@@ -11858,6 +10979,7 @@\n  * particular packet type.)\n  */\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1\n@@ -11898,6 +11020,7 @@\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4\n /* The handle of the RSS context */\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4\n \n /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8\n@@ -11915,6 +11038,7 @@\n  * always be used for a SET regardless of old/new driver vs. old/new firmware.\n  */\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1\n@@ -11952,11 +11076,13 @@\n #define\tMC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8\n /* The handle of the owning upstream port */\n #define\tMC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4\n /* Number of queues spanned by this mapping, in the range 1-64; valid fixed\n  * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and\n  * referenced RSS contexts must span no more than this number.\n  */\n #define\tMC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4\n \n /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */\n #define\tMC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4\n@@ -11965,6 +11091,7 @@\n  * handle.\n  */\n #define\tMC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4\n /* enum: guaranteed invalid .1p mapping handle value */\n #define\tMC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID  0xffffffff\n \n@@ -11982,6 +11109,7 @@\n #define\tMC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4\n /* The handle of the .1p mapping */\n #define\tMC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0\n+#define\tMC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4\n \n /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */\n #define\tMC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0\n@@ -12000,6 +11128,7 @@\n #define\tMC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36\n /* The handle of the .1p mapping */\n #define\tMC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0\n+#define\tMC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4\n /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context\n  * handle)\n  */\n@@ -12023,6 +11152,7 @@\n #define\tMC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4\n /* The handle of the .1p mapping */\n #define\tMC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0\n+#define\tMC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4\n \n /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */\n #define\tMC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36\n@@ -12049,10 +11179,13 @@\n #define\tMC_CMD_GET_VECTOR_CFG_OUT_LEN 12\n /* Base absolute interrupt vector number. */\n #define\tMC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0\n+#define\tMC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4\n /* Number of interrupt vectors allocate to this PF. */\n #define\tMC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4\n+#define\tMC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4\n /* Number of interrupt vectors to allocate per VF. */\n #define\tMC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8\n+#define\tMC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4\n \n \n /***********************************/\n@@ -12070,10 +11203,13 @@\n  * let the system find a suitable base.\n  */\n #define\tMC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0\n+#define\tMC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4\n /* Number of interrupt vectors allocate to this PF. */\n #define\tMC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4\n+#define\tMC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4\n /* Number of interrupt vectors to allocate per VF. */\n #define\tMC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8\n+#define\tMC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4\n \n /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */\n #define\tMC_CMD_SET_VECTOR_CFG_OUT_LEN 0\n@@ -12092,6 +11228,7 @@\n #define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10\n /* The handle of the v-port */\n #define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0\n+#define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4\n /* MAC address to add */\n #define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4\n #define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6\n@@ -12113,6 +11250,7 @@\n #define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10\n /* The handle of the v-port */\n #define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0\n+#define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4\n /* MAC address to add */\n #define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4\n #define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6\n@@ -12134,6 +11272,7 @@\n #define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4\n /* The handle of the v-port */\n #define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4\n \n /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */\n #define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4\n@@ -12141,6 +11280,7 @@\n #define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))\n /* The number of MAC addresses returned */\n #define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4\n /* Array of MAC addresses */\n #define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4\n #define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6\n@@ -12163,8 +11303,10 @@\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_LEN 44\n /* The handle of the v-port */\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4\n /* Flags requesting what should be changed. */\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1\n@@ -12174,14 +11316,17 @@\n  * v-switch.\n  */\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4\n /* The actual VLAN tags to insert/remove */\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16\n /* The number of MAC addresses to add */\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4\n /* MAC addresses to add */\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6\n@@ -12190,6 +11335,7 @@\n /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */\n #define\tMC_CMD_VPORT_RECONFIGURE_OUT_LEN 4\n #define\tMC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4\n #define\tMC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0\n #define\tMC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1\n \n@@ -12207,15 +11353,18 @@\n #define\tMC_CMD_EVB_PORT_QUERY_IN_LEN 4\n /* The handle of the v-port */\n #define\tMC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0\n+#define\tMC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4\n \n /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */\n #define\tMC_CMD_EVB_PORT_QUERY_OUT_LEN 8\n /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */\n #define\tMC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0\n+#define\tMC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4\n /* The number of VLAN tags that may be used on a v-adaptor connected to this\n  * EVB port.\n  */\n #define\tMC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4\n+#define\tMC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4\n \n \n /***********************************/\n@@ -12228,14 +11377,16 @@\n #define\tMC_CMD_DUMP_BUFTBL_ENTRIES 0xab\n #undef\tMC_CMD_0xab_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */\n #define\tMC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8\n /* Index of the first buffer table entry. */\n #define\tMC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4\n /* Number of buffer table entries to dump. */\n #define\tMC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4\n \n /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */\n #define\tMC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12\n@@ -12260,6 +11411,7 @@\n /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_LEN 4\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1\n@@ -12290,6 +11442,7 @@\n /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_LEN 4\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0\n+#define\tMC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1\n@@ -12314,8 +11467,10 @@\n #define\tMC_CMD_GET_CLOCK_OUT_LEN 8\n /* System frequency, MHz */\n #define\tMC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0\n+#define\tMC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4\n /* DPCPU frequency, MHz */\n #define\tMC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4\n+#define\tMC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4\n \n \n /***********************************/\n@@ -12325,36 +11480,43 @@\n #define\tMC_CMD_SET_CLOCK 0xad\n #undef\tMC_CMD_0xad_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_SET_CLOCK_IN msgrequest */\n #define\tMC_CMD_SET_CLOCK_IN_LEN 28\n /* Requested frequency in MHz for system clock domain */\n #define\tMC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0\n+#define\tMC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4\n /* enum: Leave the system clock domain frequency unchanged */\n #define\tMC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE  0x0\n /* Requested frequency in MHz for inter-core clock domain */\n #define\tMC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4\n+#define\tMC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4\n /* enum: Leave the inter-core clock domain frequency unchanged */\n #define\tMC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE  0x0\n /* Requested frequency in MHz for DPCPU clock domain */\n #define\tMC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8\n+#define\tMC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4\n /* enum: Leave the DPCPU clock domain frequency unchanged */\n #define\tMC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE  0x0\n /* Requested frequency in MHz for PCS clock domain */\n #define\tMC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12\n+#define\tMC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4\n /* enum: Leave the PCS clock domain frequency unchanged */\n #define\tMC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE  0x0\n /* Requested frequency in MHz for MC clock domain */\n #define\tMC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16\n+#define\tMC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4\n /* enum: Leave the MC clock domain frequency unchanged */\n #define\tMC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE  0x0\n /* Requested frequency in MHz for rmon clock domain */\n #define\tMC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20\n+#define\tMC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4\n /* enum: Leave the rmon clock domain frequency unchanged */\n #define\tMC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE  0x0\n /* Requested frequency in MHz for vswitch clock domain */\n #define\tMC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24\n+#define\tMC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4\n /* enum: Leave the vswitch clock domain frequency unchanged */\n #define\tMC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE  0x0\n \n@@ -12362,30 +11524,37 @@\n #define\tMC_CMD_SET_CLOCK_OUT_LEN 28\n /* Resulting system frequency in MHz */\n #define\tMC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0\n+#define\tMC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4\n /* enum: The system clock domain doesn't exist */\n #define\tMC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED  0x0\n /* Resulting inter-core frequency in MHz */\n #define\tMC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4\n+#define\tMC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4\n /* enum: The inter-core clock domain doesn't exist / isn't used */\n #define\tMC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED  0x0\n /* Resulting DPCPU frequency in MHz */\n #define\tMC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8\n+#define\tMC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4\n /* enum: The dpcpu clock domain doesn't exist */\n #define\tMC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED  0x0\n /* Resulting PCS frequency in MHz */\n #define\tMC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12\n+#define\tMC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4\n /* enum: The PCS clock domain doesn't exist / isn't controlled */\n #define\tMC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED  0x0\n /* Resulting MC frequency in MHz */\n #define\tMC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16\n+#define\tMC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4\n /* enum: The MC clock domain doesn't exist / isn't controlled */\n #define\tMC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED  0x0\n /* Resulting rmon frequency in MHz */\n #define\tMC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20\n+#define\tMC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4\n /* enum: The rmon clock domain doesn't exist / isn't controlled */\n #define\tMC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED  0x0\n /* Resulting vswitch frequency in MHz */\n #define\tMC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24\n+#define\tMC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4\n /* enum: The vswitch clock domain doesn't exist / isn't controlled */\n #define\tMC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED  0x0\n \n@@ -12397,11 +11566,12 @@\n #define\tMC_CMD_DPCPU_RPC 0xae\n #undef\tMC_CMD_0xae_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_DPCPU_RPC_IN msgrequest */\n #define\tMC_CMD_DPCPU_RPC_IN_LEN 36\n #define\tMC_CMD_DPCPU_RPC_IN_CPU_OFST 0\n+#define\tMC_CMD_DPCPU_RPC_IN_CPU_LEN 4\n /* enum: RxDPCPU0 */\n #define\tMC_CMD_DPCPU_RPC_IN_DPCPU_RX0  0x0\n /* enum: TxDPCPU0 */\n@@ -12466,12 +11636,15 @@\n #define\tMC_CMD_DPCPU_RPC_IN_WDATA_LEN 24\n /* Register data to write. Only valid in write/write-read. */\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4\n /* Register address. */\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4\n \n /* MC_CMD_DPCPU_RPC_OUT msgresponse */\n #define\tMC_CMD_DPCPU_RPC_OUT_LEN 36\n #define\tMC_CMD_DPCPU_RPC_OUT_RC_OFST 0\n+#define\tMC_CMD_DPCPU_RPC_OUT_RC_LEN 4\n /* DATA */\n #define\tMC_CMD_DPCPU_RPC_OUT_DATA_OFST 4\n #define\tMC_CMD_DPCPU_RPC_OUT_DATA_LEN 32\n@@ -12482,9 +11655,13 @@\n #define\tMC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12\n #define\tMC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24\n #define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4\n #define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4\n #define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4\n #define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4\n \n \n /***********************************/\n@@ -12500,6 +11677,7 @@\n #define\tMC_CMD_TRIGGER_INTERRUPT_IN_LEN 4\n /* Interrupt level relative to base for function. */\n #define\tMC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0\n+#define\tMC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4\n \n /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */\n #define\tMC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0\n@@ -12518,6 +11696,7 @@\n #define\tMC_CMD_SHMBOOT_OP_IN_LEN 4\n /* Identifies the operation to perform */\n #define\tMC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0\n+#define\tMC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4\n /* enum: Copy slave_data section to the slave core. (Greenport only) */\n #define\tMC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA  0x0\n \n@@ -12532,13 +11711,16 @@\n #define\tMC_CMD_CAP_BLK_READ 0xe7\n #undef\tMC_CMD_0xe7_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_CAP_BLK_READ_IN msgrequest */\n #define\tMC_CMD_CAP_BLK_READ_IN_LEN 12\n #define\tMC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0\n+#define\tMC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4\n #define\tMC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4\n+#define\tMC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4\n #define\tMC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8\n+#define\tMC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4\n \n /* MC_CMD_CAP_BLK_READ_OUT msgresponse */\n #define\tMC_CMD_CAP_BLK_READ_OUT_LENMIN 8\n@@ -12559,53 +11741,77 @@\n #define\tMC_CMD_DUMP_DO 0xe8\n #undef\tMC_CMD_0xe8_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_DUMP_DO_IN msgrequest */\n #define\tMC_CMD_DUMP_DO_IN_LEN 52\n #define\tMC_CMD_DUMP_DO_IN_PADDING_OFST 0\n+#define\tMC_CMD_DUMP_DO_IN_PADDING_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM  0x0 /* enum */\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT  0x1 /* enum */\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM  0x1 /* enum */\n #define\tMC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY  0x2 /* enum */\n #define\tMC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI  0x3 /* enum */\n #define\tMC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART  0x4 /* enum */\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE  0x1000 /* enum */\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH  0x2 /* enum */\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4\n /* enum: The uart port this command was received over (if using a uart\n  * transport)\n  */\n #define\tMC_CMD_DUMP_DO_IN_UART_PORT_SRC  0xff\n #define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24\n+#define\tMC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM  0x0 /* enum */\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION  0x1 /* enum */\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4\n #define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48\n+#define\tMC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4\n \n /* MC_CMD_DUMP_DO_OUT msgresponse */\n #define\tMC_CMD_DUMP_DO_OUT_LEN 4\n #define\tMC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0\n+#define\tMC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4\n \n \n /***********************************/\n@@ -12615,41 +11821,64 @@\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9\n #undef\tMC_CMD_0xe9_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4\n \n \n /***********************************/\n@@ -12661,17 +11890,20 @@\n #define\tMC_CMD_SET_PSU 0xea\n #undef\tMC_CMD_0xea_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_SET_PSU_IN msgrequest */\n #define\tMC_CMD_SET_PSU_IN_LEN 12\n #define\tMC_CMD_SET_PSU_IN_PARAM_OFST 0\n+#define\tMC_CMD_SET_PSU_IN_PARAM_LEN 4\n #define\tMC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE  0x0 /* enum */\n #define\tMC_CMD_SET_PSU_IN_RAIL_OFST 4\n+#define\tMC_CMD_SET_PSU_IN_RAIL_LEN 4\n #define\tMC_CMD_SET_PSU_IN_RAIL_0V9  0x0 /* enum */\n #define\tMC_CMD_SET_PSU_IN_RAIL_1V2  0x1 /* enum */\n /* desired value, eg voltage in mV */\n #define\tMC_CMD_SET_PSU_IN_VALUE_OFST 8\n+#define\tMC_CMD_SET_PSU_IN_VALUE_LEN 4\n \n /* MC_CMD_SET_PSU_OUT msgresponse */\n #define\tMC_CMD_SET_PSU_OUT_LEN 0\n@@ -12692,7 +11924,9 @@\n /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */\n #define\tMC_CMD_GET_FUNCTION_INFO_OUT_LEN 8\n #define\tMC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0\n+#define\tMC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4\n #define\tMC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4\n+#define\tMC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4\n \n \n /***********************************/\n@@ -12730,12 +11964,16 @@\n #define\tMC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))\n /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */\n #define\tMC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0\n+#define\tMC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4\n /* Offset at which to write the data */\n #define\tMC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4\n+#define\tMC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4\n /* Length of data */\n #define\tMC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8\n+#define\tMC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4\n /* Reserved for future use */\n #define\tMC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12\n+#define\tMC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4\n #define\tMC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16\n #define\tMC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1\n #define\tMC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0\n@@ -12759,12 +11997,16 @@\n #define\tMC_CMD_UART_RECV_DATA_OUT_LEN 16\n /* CRC32 over OFFSET, LENGTH, RESERVED */\n #define\tMC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0\n+#define\tMC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4\n /* Offset from which to read the data */\n #define\tMC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4\n+#define\tMC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4\n /* Length of data */\n #define\tMC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8\n+#define\tMC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4\n /* Reserved for future use */\n #define\tMC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12\n+#define\tMC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4\n \n /* MC_CMD_UART_RECV_DATA_IN msgresponse */\n #define\tMC_CMD_UART_RECV_DATA_IN_LENMIN 16\n@@ -12772,12 +12014,16 @@\n #define\tMC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))\n /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */\n #define\tMC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0\n+#define\tMC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4\n /* Offset at which to write the data */\n #define\tMC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4\n+#define\tMC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4\n /* Length of data */\n #define\tMC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8\n+#define\tMC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4\n /* Reserved for future use */\n #define\tMC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12\n+#define\tMC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4\n #define\tMC_CMD_UART_RECV_DATA_IN_DATA_OFST 16\n #define\tMC_CMD_UART_RECV_DATA_IN_DATA_LEN 1\n #define\tMC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0\n@@ -12791,14 +12037,16 @@\n #define\tMC_CMD_READ_FUSES 0xf0\n #undef\tMC_CMD_0xf0_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_READ_FUSES_IN msgrequest */\n #define\tMC_CMD_READ_FUSES_IN_LEN 8\n /* Offset in OTP to read */\n #define\tMC_CMD_READ_FUSES_IN_OFFSET_OFST 0\n+#define\tMC_CMD_READ_FUSES_IN_OFFSET_LEN 4\n /* Length of data to read in bytes */\n #define\tMC_CMD_READ_FUSES_IN_LENGTH_OFST 4\n+#define\tMC_CMD_READ_FUSES_IN_LENGTH_LEN 4\n \n /* MC_CMD_READ_FUSES_OUT msgresponse */\n #define\tMC_CMD_READ_FUSES_OUT_LENMIN 4\n@@ -12806,6 +12054,7 @@\n #define\tMC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))\n /* Length of returned OTP data in bytes */\n #define\tMC_CMD_READ_FUSES_OUT_LENGTH_OFST 0\n+#define\tMC_CMD_READ_FUSES_OUT_LENGTH_LEN 4\n /* Returned data */\n #define\tMC_CMD_READ_FUSES_OUT_DATA_OFST 4\n #define\tMC_CMD_READ_FUSES_OUT_DATA_LEN 1\n@@ -12914,6 +12163,40 @@\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC  0x9\n /* enum: CTLE EQ Resistor (0-7, Medford) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES  0xa\n+/* enum: CTLE gain (0-31, Medford2) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN  0xb\n+/* enum: CTLE pole (0-31, Medford2) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE  0xc\n+/* enum: CTLE peaking (0-31, Medford2) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK  0xd\n+/* enum: DFE Tap1 - even path (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN  0xe\n+/* enum: DFE Tap1 - odd path (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD  0xf\n+/* enum: DFE Tap2 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2  0x10\n+/* enum: DFE Tap3 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3  0x11\n+/* enum: DFE Tap4 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4  0x12\n+/* enum: DFE Tap5 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5  0x13\n+/* enum: DFE Tap6 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6  0x14\n+/* enum: DFE Tap7 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7  0x15\n+/* enum: DFE Tap8 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8  0x16\n+/* enum: DFE Tap9 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9  0x17\n+/* enum: DFE Tap10 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10  0x18\n+/* enum: DFE Tap11 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11  0x19\n+/* enum: DFE Tap12 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12  0x1a\n+/* enum: I/Q clk offset (Medford2 - 0-5, sign-magnitude (-5 - +5)) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF  0x1b\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0  0x0 /* enum */\n@@ -12985,7 +12268,7 @@\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8\n-/* enum: TX Amplitude (Huntington, Medford) */\n+/* enum: TX Amplitude (Huntington, Medford, Medford2) */\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV  0x0\n /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE  0x1\n@@ -13007,9 +12290,9 @@\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET  0x9\n /* enum: TX Amplitude Fine control (Medford) */\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE  0xa\n-/* enum: Pre-shoot Tap (Medford) */\n+/* enum: Pre-shoot Tap (Medford, Medford2) */\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV  0xb\n-/* enum: De-emphasis Tap (Medford) */\n+/* enum: De-emphasis Tap (Medford, Medford2) */\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY  0xc\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3\n@@ -13078,7 +12361,24 @@\n /* Align the arguments to 32 bits */\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3\n+/* Port-relative lane to scan eye on */\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4\n+\n+/* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3\n+/* Port-relative lane to scan eye on */\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4\n+/* Scan duration / cycle count */\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4\n \n /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0\n@@ -13110,10 +12410,12 @@\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4\n \n /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */\n #define\tMC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4\n #define\tMC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0\n+#define\tMC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4\n \n \n /***********************************/\n@@ -13312,6 +12614,7 @@\n #define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1\n #define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3\n #define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4\n+#define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4\n \n /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */\n #define\tMC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0\n@@ -13355,6 +12658,7 @@\n #define\tMC_CMD_LICENSING_IN_LEN 4\n /* identifies the type of operation requested */\n #define\tMC_CMD_LICENSING_IN_OP_OFST 0\n+#define\tMC_CMD_LICENSING_IN_OP_LEN 4\n /* enum: re-read and apply licenses after a license key partition update; note\n  * that this operation returns a zero-length response\n  */\n@@ -13366,23 +12670,30 @@\n #define\tMC_CMD_LICENSING_OUT_LEN 28\n /* count of application keys which are valid */\n #define\tMC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0\n+#define\tMC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4\n /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with\n  * MC_CMD_FC_OP_LICENSE)\n  */\n #define\tMC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4\n+#define\tMC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4\n /* count of application keys which are invalid due to being blacklisted */\n #define\tMC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8\n+#define\tMC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4\n /* count of application keys which are invalid due to being unverifiable */\n #define\tMC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12\n+#define\tMC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4\n /* count of application keys which are invalid due to being for the wrong node\n  */\n #define\tMC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16\n+#define\tMC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4\n /* licensing state (for diagnostics; the exact meaning of the bits in this\n  * field are private to the firmware)\n  */\n #define\tMC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20\n+#define\tMC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4\n /* licensing subsystem self-test report (for manftest) */\n #define\tMC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24\n+#define\tMC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4\n /* enum: licensing subsystem self-test failed */\n #define\tMC_CMD_LICENSING_OUT_SELF_TEST_FAIL  0x0\n /* enum: licensing subsystem self-test passed */\n@@ -13403,6 +12714,7 @@\n #define\tMC_CMD_LICENSING_V3_IN_LEN 4\n /* identifies the type of operation requested */\n #define\tMC_CMD_LICENSING_V3_IN_OP_OFST 0\n+#define\tMC_CMD_LICENSING_V3_IN_OP_LEN 4\n /* enum: re-read and apply licenses after a license key partition update; note\n  * that this operation returns a zero-length response\n  */\n@@ -13416,20 +12728,26 @@\n #define\tMC_CMD_LICENSING_V3_OUT_LEN 88\n /* count of keys which are valid */\n #define\tMC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0\n+#define\tMC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4\n /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with\n  * MC_CMD_FC_OP_LICENSE)\n  */\n #define\tMC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4\n+#define\tMC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4\n /* count of keys which are invalid due to being unverifiable */\n #define\tMC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8\n+#define\tMC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4\n /* count of keys which are invalid due to being for the wrong node */\n #define\tMC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12\n+#define\tMC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4\n /* licensing state (for diagnostics; the exact meaning of the bits in this\n  * field are private to the firmware)\n  */\n #define\tMC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4\n /* licensing subsystem self-test report (for manftest) */\n #define\tMC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4\n /* enum: licensing subsystem self-test failed */\n #define\tMC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL  0x0\n /* enum: licensing subsystem self-test passed */\n@@ -13471,8 +12789,10 @@\n #define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))\n /* type of license (eg 3) */\n #define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4\n /* length of the license ID (in bytes) */\n #define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4\n+#define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4\n /* the unique license ID of the adapter */\n #define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8\n #define\tMC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1\n@@ -13512,11 +12832,13 @@\n #define\tMC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4\n /* application ID to query (LICENSED_APP_ID_xxx) */\n #define\tMC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0\n+#define\tMC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4\n \n /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */\n #define\tMC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4\n /* state of this application */\n #define\tMC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0\n+#define\tMC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4\n /* enum: no (or invalid) license is present for the application */\n #define\tMC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED  0x0\n /* enum: a valid license is present for the application */\n@@ -13548,6 +12870,7 @@\n #define\tMC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4\n /* state of this application */\n #define\tMC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4\n /* enum: no (or invalid) license is present for the application */\n #define\tMC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED  0x0\n /* enum: a valid license is present for the application */\n@@ -13600,8 +12923,10 @@\n #define\tMC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))\n /* application ID */\n #define\tMC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0\n+#define\tMC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4\n /* the type of operation requested */\n #define\tMC_CMD_LICENSED_APP_OP_IN_OP_OFST 4\n+#define\tMC_CMD_LICENSED_APP_OP_IN_OP_LEN 4\n /* enum: validate application */\n #define\tMC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE  0x0\n /* enum: mask application */\n@@ -13626,8 +12951,10 @@\n #define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72\n /* application ID */\n #define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4\n /* the type of operation requested */\n #define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4\n /* validation challenge */\n #define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8\n #define\tMC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64\n@@ -13636,6 +12963,7 @@\n #define\tMC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68\n /* feature expiry (time_t) */\n #define\tMC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0\n+#define\tMC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4\n /* validation response */\n #define\tMC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4\n #define\tMC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64\n@@ -13644,10 +12972,13 @@\n #define\tMC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12\n /* application ID */\n #define\tMC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0\n+#define\tMC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4\n /* the type of operation requested */\n #define\tMC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4\n+#define\tMC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4\n /* flag */\n #define\tMC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8\n+#define\tMC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4\n \n /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */\n #define\tMC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0\n@@ -13686,8 +13017,10 @@\n #define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96\n /* application expiry time */\n #define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4\n /* application expiry units */\n #define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4\n /* enum: expiry units are accounting units */\n #define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC  0x0\n /* enum: expiry units are calendar days */\n@@ -13712,7 +13045,7 @@\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES 0xd5\n #undef\tMC_CMD_0xd5_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+#define\tMC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n \n /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12\n@@ -13723,6 +13056,7 @@\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4\n /* whether to turn on or turn off the masked features */\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4\n /* enum: turn the features off */\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF  0x0\n /* enum: turn the features back on */\n@@ -13743,12 +13077,13 @@\n #define\tMC_CMD_LICENSING_V3_TEMPORARY 0xd6\n #undef\tMC_CMD_0xd6_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+#define\tMC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n \n /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4\n /* operation code */\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4\n /* enum: install a new license, overwriting any existing temporary license.\n  * This is an asynchronous operation owing to the time taken to validate an\n  * ECDSA license\n@@ -13766,6 +13101,7 @@\n /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4\n /* ECDSA license and signature */\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160\n@@ -13773,15 +13109,18 @@\n /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4\n \n /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4\n \n /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12\n /* status code */\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4\n /* enum: finished validating and installing license */\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK  0x0\n /* enum: license validation and installation in progress */\n@@ -13814,14 +13153,17 @@\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16\n /* configuration flags */\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1\n /* receive queue handle (for RSS mode, this is the base queue) */\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4\n /* receive mode */\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4\n /* enum: receive to just the specified queue */\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE  0x0\n /* enum: receive to multiple queues using RSS context */\n@@ -13831,6 +13173,7 @@\n  * of 0xFFFFFFFF is guaranteed never to be a valid handle.\n  */\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4\n \n /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0\n@@ -13854,20 +13197,24 @@\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16\n /* configuration flags */\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1\n /* receiving queue handle (for RSS mode, this is the base queue) */\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4\n /* receive mode */\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4\n /* enum: receiving to just the specified queue */\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE  0x0\n /* enum: receiving to multiple queues using RSS context */\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS  0x1\n /* RSS context (for RX_MODE_RSS) */\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4\n \n \n /***********************************/\n@@ -13885,6 +13232,7 @@\n #define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))\n /* the type of configuration setting to change */\n #define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4\n /* enum: Per-TXQ enable for multicast UDP destination lookup for possible\n  * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)\n  */\n@@ -13898,6 +13246,7 @@\n  * on the type of configuration setting being changed\n  */\n #define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4\n /* new value: the details depend on the type of configuration setting being\n  * changed\n  */\n@@ -13923,12 +13272,14 @@\n #define\tMC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8\n /* the type of configuration setting to read */\n #define\tMC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */\n /* handle for the entity to query: queue handle, EVB port ID, etc. depending on\n  * the type of configuration setting being read\n  */\n #define\tMC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4\n \n /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */\n #define\tMC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4\n@@ -13962,12 +13313,15 @@\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16\n /* configuration flags */\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1\n /* receive queue handle (for RSS mode, this is the base queue) */\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4\n /* receive mode */\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4\n /* enum: receive to just the specified queue */\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE  0x0\n /* enum: receive to multiple queues using RSS context */\n@@ -13977,6 +13331,7 @@\n  * of 0xFFFFFFFF is guaranteed never to be a valid handle.\n  */\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4\n \n /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0\n@@ -14000,18 +13355,22 @@\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16\n /* configuration flags */\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1\n /* receiving queue handle (for RSS mode, this is the base queue) */\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4\n /* receive mode */\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4\n /* enum: receiving to just the specified queue */\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE  0x0\n /* enum: receiving to multiple queues using RSS context */\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS  0x1\n /* RSS context (for RX_MODE_RSS) */\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4\n \n \n /***********************************/\n@@ -14027,16 +13386,22 @@\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8\n /* The rx queue to get stats for. */\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1\n \n /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4\n \n \n /***********************************/\n@@ -14044,6 +13409,9 @@\n  * Find out about available PCIE resources\n  */\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO 0xfd\n+#undef\tMC_CMD_0xfd_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n \n /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0\n@@ -14052,20 +13420,27 @@\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28\n /* The maximum number of PFs the device can expose */\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4\n /* The maximum number of VFs the device can expose in total */\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4\n /* The maximum number of MSI-X vectors the device can provide in total */\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4\n /* the number of MSI-X vectors the device will allocate by default to each PF\n  */\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4\n /* the number of MSI-X vectors the device will allocate by default to each VF\n  */\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4\n /* the maximum number of MSI-X vectors the device can allocate to any one PF */\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4\n /* the maximum number of MSI-X vectors the device can allocate to any one VF */\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4\n \n \n /***********************************/\n@@ -14084,10 +13459,13 @@\n #define\tMC_CMD_GET_PORT_MODES_OUT_LEN 12\n /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */\n #define\tMC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0\n+#define\tMC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4\n /* Default (canonical) board mode */\n #define\tMC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4\n+#define\tMC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4\n /* Current board mode */\n #define\tMC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8\n+#define\tMC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4\n \n \n /***********************************/\n@@ -14097,21 +13475,26 @@\n #define\tMC_CMD_READ_ATB 0x100\n #undef\tMC_CMD_0x100_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_READ_ATB_IN msgrequest */\n #define\tMC_CMD_READ_ATB_IN_LEN 16\n #define\tMC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0\n+#define\tMC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4\n #define\tMC_CMD_READ_ATB_IN_BUS_CCOM  0x0 /* enum */\n #define\tMC_CMD_READ_ATB_IN_BUS_CKR  0x1 /* enum */\n #define\tMC_CMD_READ_ATB_IN_BUS_CPCIE  0x8 /* enum */\n #define\tMC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4\n+#define\tMC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4\n #define\tMC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8\n+#define\tMC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4\n #define\tMC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12\n+#define\tMC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4\n \n /* MC_CMD_READ_ATB_OUT msgresponse */\n #define\tMC_CMD_READ_ATB_OUT_LEN 4\n #define\tMC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0\n+#define\tMC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4\n \n \n /***********************************/\n@@ -14129,7 +13512,9 @@\n /* Each workaround is represented by a single bit according to the enums below.\n  */\n #define\tMC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4\n #define\tMC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4\n+#define\tMC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4\n /* enum: Bug 17230 work around. */\n #define\tMC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2\n /* enum: Bug 35388 work around (unsafe EVQ writes). */\n@@ -14165,6 +13550,7 @@\n  * 1,3 = 0x00030001\n  */\n #define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4\n #define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0\n #define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16\n #define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16\n@@ -14174,6 +13560,7 @@\n  * set to 1.\n  */\n #define\tMC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4\n #define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN             0x1 /* enum */\n #define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_LINK              0x2 /* enum */\n #define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD            0x4 /* enum */\n@@ -14200,6 +13587,10 @@\n  * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.\n  */\n #define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN  0x2000\n+/* enum: Privilege for insecure commands. Commands that belong to this group\n+ * are not permitted on secure adapters regardless of the privilege mask.\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE          0x4000\n /* enum: Set this bit to indicate that a new privilege mask is to be set,\n  * otherwise the command will only read the existing mask.\n  */\n@@ -14209,6 +13600,7 @@\n #define\tMC_CMD_PRIVILEGE_MASK_OUT_LEN 4\n /* For an admin function, always all the privileges are reported. */\n #define\tMC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0\n+#define\tMC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4\n \n \n /***********************************/\n@@ -14226,12 +13618,14 @@\n  * e.g. VF 1,3 = 0x00030001\n  */\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0\n+#define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16\n /* New link state mode to be set */\n #define\tMC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4\n+#define\tMC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4\n #define\tMC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO       0x0 /* enum */\n #define\tMC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP         0x1 /* enum */\n #define\tMC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN       0x2 /* enum */\n@@ -14242,11 +13636,12 @@\n /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */\n #define\tMC_CMD_LINK_STATE_MODE_OUT_LEN 4\n #define\tMC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0\n+#define\tMC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4\n \n \n /***********************************/\n /* MC_CMD_GET_SNAPSHOT_LENGTH\n- * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH\n+ * Obtain the current range of allowable values for the SNAPSHOT_LENGTH\n  * parameter to MC_CMD_INIT_RXQ.\n  */\n #define\tMC_CMD_GET_SNAPSHOT_LENGTH 0x101\n@@ -14261,8 +13656,10 @@\n #define\tMC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8\n /* Minimum acceptable snapshot length. */\n #define\tMC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0\n+#define\tMC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4\n /* Maximum acceptable snapshot length. */\n #define\tMC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4\n+#define\tMC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4\n \n \n /***********************************/\n@@ -14272,7 +13669,7 @@\n #define\tMC_CMD_FUSE_DIAGS 0x102\n #undef\tMC_CMD_0x102_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_FUSE_DIAGS_IN msgrequest */\n #define\tMC_CMD_FUSE_DIAGS_IN_LEN 0\n@@ -14281,28 +13678,40 @@\n #define\tMC_CMD_FUSE_DIAGS_OUT_LEN 48\n /* Total number of mismatched bits between pairs in area 0 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4\n /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4\n /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4\n /* Checksum of data after logical OR of pairs in area 0 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4\n /* Total number of mismatched bits between pairs in area 1 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4\n /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4\n /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4\n /* Checksum of data after logical OR of pairs in area 1 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4\n /* Total number of mismatched bits between pairs in area 2 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4\n /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4\n /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4\n /* Checksum of data after logical OR of pairs in area 2 */\n #define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44\n+#define\tMC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4\n \n \n /***********************************/\n@@ -14320,6 +13729,7 @@\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_LEN 16\n /* The groups of functions to have their privilege masks modified. */\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_NONE       0x0 /* enum */\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_ALL        0x1 /* enum */\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY   0x2 /* enum */\n@@ -14328,6 +13738,7 @@\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_ONE        0x5 /* enum */\n /* For VFS_OF_PF specify the PF, for ONE specify the target function */\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16\n@@ -14336,10 +13747,12 @@\n  * refer to the command MC_CMD_PRIVILEGE_MASK\n  */\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4\n /* Privileges to be removed from the target functions. For privilege\n  * definitions refer to the command MC_CMD_PRIVILEGE_MASK\n  */\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4\n \n /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */\n #define\tMC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0\n@@ -14358,8 +13771,10 @@\n #define\tMC_CMD_XPM_READ_BYTES_IN_LEN 8\n /* Start address (byte) */\n #define\tMC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0\n+#define\tMC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4\n /* Count (bytes) */\n #define\tMC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4\n+#define\tMC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4\n \n /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */\n #define\tMC_CMD_XPM_READ_BYTES_OUT_LENMIN 0\n@@ -14379,7 +13794,7 @@\n #define\tMC_CMD_XPM_WRITE_BYTES 0x104\n #undef\tMC_CMD_0x104_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */\n #define\tMC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8\n@@ -14387,8 +13802,10 @@\n #define\tMC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))\n /* Start address (byte) */\n #define\tMC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4\n /* Count (bytes) */\n #define\tMC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4\n+#define\tMC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4\n /* Data */\n #define\tMC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8\n #define\tMC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1\n@@ -14406,14 +13823,16 @@\n #define\tMC_CMD_XPM_READ_SECTOR 0x105\n #undef\tMC_CMD_0x105_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */\n #define\tMC_CMD_XPM_READ_SECTOR_IN_LEN 8\n /* Sector index */\n #define\tMC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0\n+#define\tMC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4\n /* Sector size */\n #define\tMC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4\n+#define\tMC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4\n \n /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */\n #define\tMC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4\n@@ -14421,9 +13840,11 @@\n #define\tMC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))\n /* Sector type */\n #define\tMC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4\n #define\tMC_CMD_XPM_READ_SECTOR_OUT_BLANK            0x0 /* enum */\n #define\tMC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128   0x1 /* enum */\n #define\tMC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256   0x2 /* enum */\n+#define\tMC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA      0x3 /* enum */\n #define\tMC_CMD_XPM_READ_SECTOR_OUT_INVALID          0xff /* enum */\n /* Sector data */\n #define\tMC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4\n@@ -14439,7 +13860,7 @@\n #define\tMC_CMD_XPM_WRITE_SECTOR 0x106\n #undef\tMC_CMD_0x106_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */\n #define\tMC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12\n@@ -14456,10 +13877,12 @@\n #define\tMC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3\n /* Sector type */\n #define\tMC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */\n /* Sector size */\n #define\tMC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8\n+#define\tMC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4\n /* Sector data */\n #define\tMC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12\n #define\tMC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1\n@@ -14470,6 +13893,7 @@\n #define\tMC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4\n /* New sector index */\n #define\tMC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0\n+#define\tMC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4\n \n \n /***********************************/\n@@ -14479,12 +13903,13 @@\n #define\tMC_CMD_XPM_INVALIDATE_SECTOR 0x107\n #undef\tMC_CMD_0x107_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */\n #define\tMC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4\n /* Sector index */\n #define\tMC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0\n+#define\tMC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4\n \n /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */\n #define\tMC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0\n@@ -14497,14 +13922,16 @@\n #define\tMC_CMD_XPM_BLANK_CHECK 0x108\n #undef\tMC_CMD_0x108_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */\n #define\tMC_CMD_XPM_BLANK_CHECK_IN_LEN 8\n /* Start address (byte) */\n #define\tMC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0\n+#define\tMC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4\n /* Count (bytes) */\n #define\tMC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4\n+#define\tMC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4\n \n /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */\n #define\tMC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4\n@@ -14512,6 +13939,7 @@\n #define\tMC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))\n /* Total number of bad (non-blank) locations */\n #define\tMC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0\n+#define\tMC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4\n /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit\n  * into MCDI response)\n  */\n@@ -14528,14 +13956,16 @@\n #define\tMC_CMD_XPM_REPAIR 0x109\n #undef\tMC_CMD_0x109_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_XPM_REPAIR_IN msgrequest */\n #define\tMC_CMD_XPM_REPAIR_IN_LEN 8\n /* Start address (byte) */\n #define\tMC_CMD_XPM_REPAIR_IN_ADDR_OFST 0\n+#define\tMC_CMD_XPM_REPAIR_IN_ADDR_LEN 4\n /* Count (bytes) */\n #define\tMC_CMD_XPM_REPAIR_IN_COUNT_OFST 4\n+#define\tMC_CMD_XPM_REPAIR_IN_COUNT_LEN 4\n \n /* MC_CMD_XPM_REPAIR_OUT msgresponse */\n #define\tMC_CMD_XPM_REPAIR_OUT_LEN 0\n@@ -14549,7 +13979,7 @@\n #define\tMC_CMD_XPM_DECODER_TEST 0x10a\n #undef\tMC_CMD_0x10a_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */\n #define\tMC_CMD_XPM_DECODER_TEST_IN_LEN 0\n@@ -14569,7 +13999,7 @@\n #define\tMC_CMD_XPM_WRITE_TEST 0x10b\n #undef\tMC_CMD_0x10b_PRIVILEGE_CTG\n \n-#define\tMC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+#define\tMC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n \n /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */\n #define\tMC_CMD_XPM_WRITE_TEST_IN_LEN 0\n@@ -14596,10 +14026,13 @@\n #define\tMC_CMD_EXEC_SIGNED_IN_LEN 28\n /* the length of code to include in the CMAC */\n #define\tMC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0\n+#define\tMC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4\n /* the length of date to include in the CMAC */\n #define\tMC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4\n+#define\tMC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4\n /* the XPM sector containing the key to use */\n #define\tMC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8\n+#define\tMC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4\n /* the expected CMAC value */\n #define\tMC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12\n #define\tMC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16\n@@ -14623,6 +14056,7 @@\n #define\tMC_CMD_PREPARE_SIGNED_IN_LEN 4\n /* the length of data area to clear */\n #define\tMC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0\n+#define\tMC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4\n \n /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */\n #define\tMC_CMD_PREPARE_SIGNED_OUT_LEN 0\n@@ -14645,6 +14079,7 @@\n #define\tMC_CMD_SET_SECURITY_RULE_IN_LEN 92\n /* fields to include in match criteria */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_LEN 4\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1\n@@ -14701,8 +14136,10 @@\n #define\tMC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_LEN 2\n /* Physical port to match (as little-endian 32-bit value) */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_OFST 28\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_LEN 4\n /* Reserved; set to 0 */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_RESERVED_OFST 32\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_RESERVED_LEN 4\n /* remote IP address to match (as bytes in network order; set last 12 bytes to\n  * 0 for IPv4 address)\n  */\n@@ -14719,58 +14156,85 @@\n  * MC_CMD_SUBNET_MAP_SET_NODE appropriately\n  */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_OFST 68\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_LEN 4\n /* remote portrange ID to match (as little-endian 32-bit value); note that\n  * remote port ranges are matched by mapping the remote port to a \"portrange\n  * ID\" via a data structure which must already have been configured using\n  * MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE\n  */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_OFST 72\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_LEN 4\n /* local portrange ID to match (as little-endian 32-bit value); note that local\n  * port ranges are matched by mapping the local port to a \"portrange ID\" via a\n  * data structure which must already have been configured using\n  * MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE\n  */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_OFST 76\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_LEN 4\n /* set the action for transmitted packets matching this rule */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_LEN 4\n /* enum: make no decision */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE  0x0\n /* enum: decide to accept the packet */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST  0x1\n /* enum: decide to drop the packet */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST  0x2\n+/* enum: inform the TSA controller about some sample of packets matching this\n+ * rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with\n+ * either the WHITELIST or BLACKLIST action\n+ */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_SAMPLE  0x4\n /* enum: do not change the current TX action */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED  0xffffffff\n /* set the action for received packets matching this rule */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_LEN 4\n /* enum: make no decision */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE  0x0\n /* enum: decide to accept the packet */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST  0x1\n /* enum: decide to drop the packet */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST  0x2\n+/* enum: inform the TSA controller about some sample of packets matching this\n+ * rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with\n+ * either the WHITELIST or BLACKLIST action\n+ */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_SAMPLE  0x4\n /* enum: do not change the current RX action */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED  0xffffffff\n /* counter ID to associate with this rule; IDs are allocated using\n  * MC_CMD_SECURITY_RULE_COUNTER_ALLOC\n  */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_LEN 4\n /* enum: special value for the null counter ID */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE  0x0\n+/* enum: special value to tell the MC to allocate an available counter */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_SW_AUTO  0xeeeeeeee\n+/* enum: special value to request use of hardware counter (Medford2 only) */\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_HW  0xffffffff\n \n /* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */\n-#define\tMC_CMD_SET_SECURITY_RULE_OUT_LEN 28\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_LEN 32\n /* new reference count for uses of counter ID */\n #define\tMC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_LEN 4\n /* constructed match bits for this rule (as a tracing aid only) */\n #define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_OFST 4\n #define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_LEN 12\n /* constructed discriminator bits for this rule (as a tracing aid only) */\n #define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_OFST 16\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_LEN 4\n /* base location for probes for this rule (as a tracing aid only) */\n #define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_OFST 20\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_LEN 4\n /* step for probes for this rule (as a tracing aid only) */\n #define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_OFST 24\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_LEN 4\n+/* ID for reading back the counter */\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_OFST 28\n+#define\tMC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_LEN 4\n \n \n /***********************************/\n@@ -14790,6 +14254,7 @@\n #define\tMC_CMD_RESET_SECURITY_RULES_IN_LEN 4\n /* index of physical port to reset (or ALL_PHYSICAL_PORTS to reset all) */\n #define\tMC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0\n+#define\tMC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_LEN 4\n /* enum: special value to reset all physical ports */\n #define\tMC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS  0xffffffff\n \n@@ -14842,6 +14307,7 @@\n #define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4\n /* the number of new counter IDs to request */\n #define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_LEN 4\n \n /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT msgresponse */\n #define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMIN 4\n@@ -14851,6 +14317,7 @@\n  * requested if resources are unavailable)\n  */\n #define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_LEN 4\n /* new counter ID(s) */\n #define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 4\n #define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4\n@@ -14877,6 +14344,7 @@\n #define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num))\n /* the number of counter IDs to free */\n #define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_LEN 4\n /* the counter ID(s) to free */\n #define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_OFST 4\n #define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_LEN 4\n@@ -14908,6 +14376,7 @@\n #define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num))\n /* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */\n #define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_LEN 4\n /* SUBNET_MAP_NUM_ENTRIES_PER_NODE new entries; each entry is either a pointer\n  * to the next node, expressed as an offset in the trie memory (i.e. node ID\n  * multiplied by SUBNET_MAP_NUM_ENTRIES_PER_NODE), or a leaf value in the range\n@@ -15079,12 +14548,16 @@\n #define\tMC_CMD_RX_BALANCING_IN_LEN 16\n /* The RX port whose upconverter table will be modified */\n #define\tMC_CMD_RX_BALANCING_IN_PORT_OFST 0\n+#define\tMC_CMD_RX_BALANCING_IN_PORT_LEN 4\n /* The VLAN priority associated to the table index and vFIFO */\n #define\tMC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4\n+#define\tMC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4\n /* The resulting bit of SRC^DST for indexing the table */\n #define\tMC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8\n+#define\tMC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4\n /* The RX engine to which the vFIFO in the table entry will point to */\n #define\tMC_CMD_RX_BALANCING_IN_ENG_OFST 12\n+#define\tMC_CMD_RX_BALANCING_IN_ENG_LEN 4\n \n /* MC_CMD_RX_BALANCING_OUT msgresponse */\n #define\tMC_CMD_RX_BALANCING_OUT_LEN 0\n@@ -15108,6 +14581,7 @@\n /* MC_CMD_TSA_BIND_IN msgrequest: Protocol operation code */\n #define\tMC_CMD_TSA_BIND_IN_LEN 4\n #define\tMC_CMD_TSA_BIND_IN_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_IN_OP_LEN 4\n /* enum: Retrieve the TSAN ID from a TSAN. TSAN ID is a unique identifier for\n  * the network adapter. More specifically, TSAN ID equals the MAC address of\n  * the network adapter. TSAN ID is used as part of the TSAN authentication\n@@ -15128,14 +14602,36 @@\n  */\n #define\tMC_CMD_TSA_BIND_OP_SET_KEY 0x3\n /* enum: Request an unbinding operation. Note- TSAN clears the binding ticket\n- * from the Nvram section.\n+ * from the Nvram section. Deprecated. Use MC_CMD_TSA_BIND_OP_UNBIND_EXT opcode\n+ * as indicated below.\n  */\n #define\tMC_CMD_TSA_BIND_OP_UNBIND 0x4\n+/* enum: Opcode associated with the propagation of the unbinding ticket data\n+ * blob. The latest SF-115479-TC spec requires a more secure unbinding\n+ * procedure based on unbinding ticket. Note- The previous unbind operation\n+ * based on MC_CMD_TSA_BIND_OP_UNBIND remains in place but now deprecated.\n+ */\n+#define\tMC_CMD_TSA_BIND_OP_UNBIND_EXT 0x5\n+/* enum: Opcode associated with the propagation of the unbinding secret token.\n+ * TSAN persists the unbinding secret token. Refer to SF-115479-TC for more\n+ * information.\n+ */\n+#define\tMC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN 0x6\n+/* enum: Request a decommissioning operation. This is to force unbinding the\n+ * adapter. Note- This type of operation comes handy when keys other attributes\n+ * get corrupted at the database level on the controller side and not able to\n+ * unbind the adapter as part of a normal unbind procedure. Note- Refer to\n+ * SF-115479-TC for more information.\n+ */\n+#define\tMC_CMD_TSA_BIND_OP_DECOMMISSION 0x7\n+/* enum: Request a certificate. */\n+#define\tMC_CMD_TSA_BIND_OP_GET_CERTIFICATE 0x8\n \n /* MC_CMD_TSA_BIND_IN_GET_ID msgrequest */\n #define\tMC_CMD_TSA_BIND_IN_GET_ID_LEN 20\n /* The operation requested. */\n #define\tMC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_IN_GET_ID_OP_LEN 4\n /* Cryptographic nonce that TSAC generates and sends to TSAN. TSAC generates\n  * the nonce every time as part of the TSAN post-binding authentication\n  * procedure when the TSAN-TSAC connection terminates and TSAN does need to re-\n@@ -15148,6 +14644,7 @@\n #define\tMC_CMD_TSA_BIND_IN_GET_TICKET_LEN 4\n /* The operation requested. */\n #define\tMC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_IN_GET_TICKET_OP_LEN 4\n \n /* MC_CMD_TSA_BIND_IN_SET_KEY msgrequest */\n #define\tMC_CMD_TSA_BIND_IN_SET_KEY_LENMIN 5\n@@ -15155,6 +14652,7 @@\n #define\tMC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num))\n /* The operation requested. */\n #define\tMC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_IN_SET_KEY_OP_LEN 4\n /* This data blob contains the private key generated by the TSAC. TSAN uses\n  * this key for a signing operation. Note- This private key is used in\n  * conjunction with the post-binding TSAN authentication procedure that occurs\n@@ -15166,26 +14664,155 @@\n #define\tMC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1\n #define\tMC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248\n \n-/* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Asks for the un-binding procedure */\n+/* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Asks for the un-binding procedure\n+ * Deprecated. Use MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest as indicated below.\n+ */\n #define\tMC_CMD_TSA_BIND_IN_UNBIND_LEN 10\n /* The operation requested. */\n #define\tMC_CMD_TSA_BIND_IN_UNBIND_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_OP_LEN 4\n /* TSAN unique identifier for the network adapter */\n #define\tMC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 4\n #define\tMC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6\n \n+/* MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest: Asks for the un-binding procedure\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMIN 93\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMAX 252\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_LEN(num) (92+1*(num))\n+/* The operation requested. */\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_LEN 4\n+/* TSAN unique identifier for the network adapter */\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_OFST 4\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_LEN 6\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_RSVD_OFST 10\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_RSVD_LEN 2\n+/* This attribute identifies the TSA infrastructure domain. The length of the\n+ * TSAID attribute is limited to 64 bytes. This is how TSA SDK defines the max\n+ * length. Note- The TSAID is the Organizational Unit Name filed as part of the\n+ * root and server certificates.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_OFST 12\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_LEN 1\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_NUM 64\n+/* Unbinding secret token. The adapter validates this unbinding token by\n+ * comparing it against the one stored on the adapter as part of the\n+ * MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest. Refer to SF-115479-TC for\n+ * more information.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_UNBINDTOKEN_OFST 76\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_UNBINDTOKEN_LEN 16\n+/* This is the signature of the above mentioned fields- TSANID, TSAID and\n+ * UNBINDTOKEN. As per current requirements, the SIG opaque data blob contains\n+ * ECDSA ECC-384 based signature. The ECC curve is secp384r1. The signature is\n+ * also ASN-1 encoded. Note- The signature is verified based on the public key\n+ * stored into the root certificate that is provisioned on the adapter side.\n+ * This key is known as the PUKtsaid. Refer to SF-115479-TC for more\n+ * information.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_OFST 92\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_LEN 1\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_MINNUM 1\n+#define\tMC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_MAXNUM 160\n+\n+/* MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest */\n+#define\tMC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_LEN 20\n+/* The operation requested. */\n+#define\tMC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_LEN 4\n+/* Unbinding secret token. TSAN persists the unbinding secret token. Refer to\n+ * SF-115479-TC for more information.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_UNBINDTOKEN_OFST 4\n+#define\tMC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_UNBINDTOKEN_LEN 16\n+/* enum: There are situations when the binding process does not complete\n+ * successfully due to key, other attributes corruption at the database level\n+ * (Controller). Adapter can't connect to the controller anymore. To recover,\n+ * make usage of the decommission command that forces the adapter into\n+ * unbinding state.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_ADAPTER_BINDING_FAILURE 0x1\n+\n+/* MC_CMD_TSA_BIND_IN_DECOMMISSION msgrequest: Asks for the decommissioning\n+ * procedure\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_LENMIN 109\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_LENMAX 252\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_LEN(num) (108+1*(num))\n+/* This is the signature of the above mentioned fields- TSAID, USER and REASON.\n+ * As per current requirements, the SIG opaque data blob contains ECDSA ECC-384\n+ * based signature. The ECC curve is secp384r1. The signature is also ASN-1\n+ * encoded . Note- The signature is verified based on the public key stored\n+ * into the root certificate that is provisioned on the adapter side. This key\n+ * is known as the PUKtsaid. Refer to SF-115479-TC for more information.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_OFST 108\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_LEN 1\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_MINNUM 1\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_MAXNUM 144\n+/* The operation requested. */\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_OP_LEN 4\n+/* This attribute identifies the TSA infrastructure domain. The length of the\n+ * TSAID attribute is limited to 64 bytes. This is how TSA SDK defines the max\n+ * length. Note- The TSAID is the Organizational Unit Name filed as part of the\n+ * root and server certificates.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_OFST 4\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_LEN 1\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_NUM 64\n+/* User ID that comes, as an example, from the Controller. Note- The 33 byte\n+ * length of this attribute is max length of the linux user name plus null\n+ * character.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_USER_OFST 68\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_USER_LEN 1\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_USER_NUM 33\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_USER_RSVD_OFST 101\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_USER_RSVD_LEN 3\n+/* Reason of why decommissioning happens Note- The list of reasons, defined as\n+ * part of the enumeration below, can be extended.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_OFST 104\n+#define\tMC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_LEN 4\n+\n+/* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE msgrequest: Request a certificate. */\n+#define\tMC_CMD_TSA_BIND_IN_GET_CERTIFICATE_LEN 8\n+/* The operation requested, must be MC_CMD_TSA_BIND_OP_GET_CERTIFICATE. */\n+#define\tMC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_LEN 4\n+/* Type of the certificate to be retrieved. */\n+#define\tMC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_OFST 4\n+#define\tMC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_LEN 4\n+#define\tMC_CMD_TSA_BIND_IN_GET_CERTIFICATE_UNUSED  0x0 /* enum */\n+/* enum: Adapter Authentication Certificate (AAC). The AAC is used by the\n+ * controller to verify the authenticity of the adapter.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AAC  0x1\n+/* enum: Adapter Authentication Signing Certificate (AASC). The AASC is used by\n+ * the controller to verify the validity of AAC.\n+ */\n+#define\tMC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AASC  0x2\n+\n /* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse */\n #define\tMC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 15\n #define\tMC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252\n #define\tMC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num))\n-/* The operation completion code. */\n+/* The protocol operation code MC_CMD_TSA_BIND_OP_GET_ID that is sent back to\n+ * the caller.\n+ */\n #define\tMC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_OP_LEN 4\n /* Rules engine type. Note- The rules engine type allows TSAC to further\n  * identify the connected endpoint (e.g. TSAN, NIC Emulator) type and take the\n  * proper action accordingly. As an example, TSAC uses the rules engine type to\n  * select the SF key that differs in the case of TSAN vs. NIC Emulator.\n  */\n #define\tMC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_OFST 4\n+#define\tMC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_LEN 4\n /* enum: Hardware rules engine. */\n #define\tMC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_TSAN 0x1\n /* enum: Nic emulator rules engine. */\n@@ -15209,8 +14836,11 @@\n #define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_LENMIN 5\n #define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252\n #define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num))\n-/* The operation completion code. */\n+/* The protocol operation code MC_CMD_TSA_BIND_OP_GET_TICKET that is sent back\n+ * to the caller.\n+ */\n #define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_OUT_GET_TICKET_OP_LEN 4\n /* The ticket represents the data blob construct that TSAN sends to TSAC as\n  * part of the binding protocol. From the TSAN perspective the ticket is an\n  * opaque construct. For more info refer to SF-115479-TC.\n@@ -15222,15 +14852,21 @@\n \n /* MC_CMD_TSA_BIND_OUT_SET_KEY msgresponse */\n #define\tMC_CMD_TSA_BIND_OUT_SET_KEY_LEN 4\n-/* The operation completion code. */\n+/* The protocol operation code MC_CMD_TSA_BIND_OP_SET_KEY that is sent back to\n+ * the caller.\n+ */\n #define\tMC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_OUT_SET_KEY_OP_LEN 4\n \n-/* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse */\n+/* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse: Response to insecure unbind request.\n+ */\n #define\tMC_CMD_TSA_BIND_OUT_UNBIND_LEN 8\n /* Same as MC_CMD_ERR field, but included as 0 in success cases */\n #define\tMC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_RESULT_LEN 4\n /* Extra status information */\n #define\tMC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_INFO_LEN 4\n /* enum: Unbind successful. */\n #define\tMC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND  0x0\n /* enum: TSANID mismatch */\n@@ -15240,6 +14876,66 @@\n /* enum: TSAN is not bound to a binding ticket. */\n #define\tMC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND  0x3\n \n+/* MC_CMD_TSA_BIND_OUT_UNBIND_EXT msgresponse: Response to secure unbind\n+ * request. (Note! This has same fields as insecure unbind response but is a\n+ * response to a different command.)\n+ */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_LEN 8\n+/* Same as MC_CMD_ERR field, but included as 0 in success cases */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_OFST 0\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_LEN 4\n+/* Extra status information */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_OFST 4\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_LEN 4\n+/* enum: Unbind successful. */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_OK_UNBOUND  0x0\n+/* enum: TSANID mismatch */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TSANID  0x1\n+/* enum: Unable to remove the binding ticket from persistent storage. */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_REMOVE_TICKET  0x2\n+/* enum: TSAN is not bound to a binding ticket. */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_NOT_BOUND  0x3\n+/* enum: Invalid unbind token */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TOKEN  0x4\n+/* enum: Invalid signature */\n+#define\tMC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_SIGNATURE  0x5\n+\n+/* MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN msgresponse */\n+#define\tMC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_LEN 4\n+/* The protocol operation code MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN that is sent\n+ * back to the caller.\n+ */\n+#define\tMC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_LEN 4\n+\n+/* MC_CMD_TSA_BIND_OUT_DECOMMISSION msgresponse */\n+#define\tMC_CMD_TSA_BIND_OUT_DECOMMISSION_LEN 4\n+/* The protocol operation code MC_CMD_TSA_BIND_OP_DECOMMISSION that is sent\n+ * back to the caller.\n+ */\n+#define\tMC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_LEN 4\n+\n+/* MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE msgresponse */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMIN 9\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMAX 252\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LEN(num) (8+1*(num))\n+/* The protocol operation code MC_CMD_TSA_BIND_OP_GET_CERTIFICATE that is sent\n+ * back to the caller.\n+ */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_OFST 0\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_LEN 4\n+/* Type of the certificate. */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_TYPE_OFST 4\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_TYPE_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_TSA_BIND_IN_GET_CERTIFICATE/TYPE */\n+/* The certificate data. */\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_OFST 8\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_LEN 1\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MINNUM 1\n+#define\tMC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MAXNUM 244\n+\n \n /***********************************/\n /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE\n@@ -15264,6 +14960,7 @@\n #define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_LEN 4\n /* the operation to perform */\n #define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_LEN 4\n /* enum: reports the ruleset version that is cached in persistent storage but\n  * performs no other action\n  */\n@@ -15285,6 +14982,7 @@\n  * requested operation in the case of rollback, commit, or invalidate)\n  */\n #define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_LEN 4\n /* enum: persistent cache is invalid (the VERSION field will be empty in this\n  * case)\n  */\n@@ -15317,8 +15015,10 @@\n #define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))\n /* The tag to be appended */\n #define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4\n /* The length of the data */\n #define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4\n /* The data to be contained in the TLV structure */\n #define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8\n #define\tMC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1\n@@ -15344,6 +15044,7 @@\n #define\tMC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4\n /* Data type to be checked */\n #define\tMC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4\n \n /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */\n #define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12\n@@ -15351,10 +15052,13 @@\n #define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))\n /* Number of sectors found (test builds only) */\n #define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4\n /* Number of bytes found (test builds only) */\n #define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4\n /* Length of signature */\n #define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4\n /* Signature */\n #define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12\n #define\tMC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1\n@@ -15380,12 +15084,16 @@\n #define\tMC_CMD_SET_EVQ_TMR_IN_LEN 16\n /* Function-relative queue instance */\n #define\tMC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0\n+#define\tMC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4\n /* Requested value for timer load (in nanoseconds) */\n #define\tMC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4\n+#define\tMC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4\n /* Requested value for timer reload (in nanoseconds) */\n #define\tMC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8\n+#define\tMC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4\n /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */\n #define\tMC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12\n+#define\tMC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4\n #define\tMC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS  0x0 /* enum */\n #define\tMC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START  0x1 /* enum */\n #define\tMC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START  0x2 /* enum */\n@@ -15395,8 +15103,10 @@\n #define\tMC_CMD_SET_EVQ_TMR_OUT_LEN 8\n /* Actual value for timer load (in nanoseconds) */\n #define\tMC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0\n+#define\tMC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4\n /* Actual value for timer reload (in nanoseconds) */\n #define\tMC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4\n+#define\tMC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4\n \n \n /***********************************/\n@@ -15415,29 +15125,35 @@\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36\n /* Reserved for future use. */\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4\n /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in\n  * nanoseconds) for each increment of the timer load/reload count. The\n  * requested duration of a timer is this value multiplied by the timer\n  * load/reload count.\n  */\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4\n /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value\n  * allowed for timer load/reload counts.\n  */\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4\n /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a\n  * multiple of this step size will be rounded in an implementation defined\n  * manner.\n  */\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4\n /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only\n  * meaningful if MC_CMD_SET_EVQ_TMR is implemented.\n  */\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4\n /* Timer durations requested via MCDI that are not a multiple of this step size\n  * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented.\n  */\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4\n /* For timers updated using the bug35388 workaround, this is the time interval\n  * (in nanoseconds) for each increment of the timer load/reload count. The\n  * requested duration of a timer is this value multiplied by the timer\n@@ -15445,17 +15161,20 @@\n  * is enabled.\n  */\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4\n /* For timers updated using the bug35388 workaround, this is the maximum value\n  * allowed for timer load/reload counts. This field is only meaningful if the\n  * bug35388 workaround is enabled.\n  */\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4\n /* For timers updated using the bug35388 workaround, timer load/reload counts\n  * not a multiple of this step size will be rounded in an implementation\n  * defined manner. This field is only meaningful if the bug35388 workaround is\n  * enabled.\n  */\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4\n \n \n /***********************************/\n@@ -15474,19 +15193,24 @@\n  * local queue index.\n  */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4\n /* Will the common pool be used as TX_vFIFO_ULL (1) */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED       0x1 /* enum */\n /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED      0x0\n /* Number of buffers to reserve for the common pool */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4\n /* TX datapath to which the Common Pool is connected to. */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4\n /* enum: Extracts information from function */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE          -0x1\n /* Network port or RX Engine to which the common pool connects. */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4\n /* enum: Extracts information from function */\n /*               MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE          -0x1 */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0          0x0 /* enum */\n@@ -15502,6 +15226,7 @@\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4\n /* ID of the common pool allocated */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4\n \n \n /***********************************/\n@@ -15519,8 +15244,10 @@\n /* Common pool previously allocated to which the new vFIFO will be associated\n  */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4\n /* Port or RX engine to associate the vFIFO egress */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4\n /* enum: Extracts information from common pool */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE   -0x1\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0          0x0 /* enum */\n@@ -15533,12 +15260,15 @@\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1     0x5\n /* Minimum number of buffers that the pool must have */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4\n /* enum: Do not check the space available */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM     0x0\n /* Will the vFIFO be used as TX_vFIFO_ULL */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4\n /* Network priority of the vFIFO,if applicable */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4\n /* enum: Search for the lowest unused priority */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE  -0x1\n \n@@ -15546,8 +15276,10 @@\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8\n /* Short vFIFO ID */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4\n /* Network priority of the vFIFO */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4\n \n \n /***********************************/\n@@ -15564,6 +15296,7 @@\n #define\tMC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4\n /* Short vFIFO ID */\n #define\tMC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0\n+#define\tMC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4\n \n /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */\n #define\tMC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0\n@@ -15583,6 +15316,7 @@\n #define\tMC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4\n /* Common pool ID given when pool allocated */\n #define\tMC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0\n+#define\tMC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4\n \n /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */\n #define\tMC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0\n@@ -15610,6 +15344,7 @@\n #define\tMC_CMD_REKEY_IN_LEN 4\n /* the type of operation requested */\n #define\tMC_CMD_REKEY_IN_OP_OFST 0\n+#define\tMC_CMD_REKEY_IN_OP_LEN 4\n /* enum: Start the rekeying operation */\n #define\tMC_CMD_REKEY_IN_OP_REKEY  0x0\n /* enum: Poll for completion of the rekeying operation */\n@@ -15636,8 +15371,10 @@\n #define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8\n /* Available buffers for the ENG to NET vFIFOs. */\n #define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0\n+#define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4\n /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */\n #define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4\n+#define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4\n \n \n /***********************************/\n@@ -15659,13 +15396,954 @@\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_LEN 4\n /* Flags specifying what type of security features are being set */\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_FLAGS_OFST 0\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_FLAGS_LEN 4\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_LBN 0\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_WIDTH 1\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_LBN 1\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_LBN 31\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_WIDTH 1\n \n /* MC_CMD_SET_SECURITY_FUSES_OUT msgresponse */\n #define\tMC_CMD_SET_SECURITY_FUSES_OUT_LEN 0\n \n+/* MC_CMD_SET_SECURITY_FUSES_V2_OUT msgresponse */\n+#define\tMC_CMD_SET_SECURITY_FUSES_V2_OUT_LEN 4\n+/* Flags specifying which security features are enforced on the NIC after the\n+ * flags in the request have been applied. See\n+ * MC_CMD_SET_SECURITY_FUSES_IN/FLAGS for flag definitions.\n+ */\n+#define\tMC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_TSA_INFO\n+ * Messages sent from TSA adapter to TSA controller. This command is only valid\n+ * when the MCDI header has MESSAGE_TYPE set to MCDI_MESSAGE_TYPE_TSA. This\n+ * command is not sent by the driver to the MC; it is sent from the MC to a TSA\n+ * controller, being treated more like an alert message rather than a command;\n+ * hence the MC does not expect a response in return. Doxbox reference\n+ * SF-117371-SW\n+ */\n+#define\tMC_CMD_TSA_INFO 0x127\n+#undef\tMC_CMD_0x127_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TSA_INFO_IN msgrequest */\n+#define\tMC_CMD_TSA_INFO_IN_LEN 4\n+#define\tMC_CMD_TSA_INFO_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_TSA_INFO_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_TSA_INFO_IN_OP_LBN 0\n+#define\tMC_CMD_TSA_INFO_IN_OP_WIDTH 16\n+/* enum: Information about recently discovered local IP address of the adapter\n+ */\n+#define\tMC_CMD_TSA_INFO_OP_LOCAL_IP 0x1\n+/* enum: Information about a sampled packet that either - did not match any\n+ * black/white-list filters and was allowed by the default filter or - did not\n+ * match any black/white-list filters and was denied by the default filter\n+ */\n+#define\tMC_CMD_TSA_INFO_OP_PKT_SAMPLE 0x2\n+\n+/* MC_CMD_TSA_INFO_IN_LOCAL_IP msgrequest:\n+ *\n+ * The TSA controller maintains a list of IP addresses valid for each port of a\n+ * TSA adapter. The TSA controller requires information from the adapter\n+ * inorder to learn new IP addresses assigned to a physical port and to\n+ * identify those that are no longer assigned to the physical port. For this\n+ * purpose, the TSA adapter snoops ARP replys, gratuitous ARP requests and ARP\n+ * probe packets seen on each physical port. This definition describes the\n+ * format of the notification message sent from a TSA adapter to a TSA\n+ * controller related to any information related to a change in IP address\n+ * assignment for a port. Doxbox reference SF-117371.\n+ *\n+ * There may be a possibility of combining multiple notifications in a single\n+ * message in future. When that happens, a new flag can be defined using the\n+ * reserved bits to describe the extended format of this notification.\n+ */\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_LEN 18\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_OFST 0\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_LEN 4\n+/* Additional metadata describing the IP address information such as source of\n+ * information retrieval, type of IP address, physical port number.\n+ */\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_OFST 4\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_LEN 4\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_LBN 0\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_WIDTH 8\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_LBN 8\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_WIDTH 8\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_LBN 16\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_WIDTH 8\n+/* enum: ARP reply sent out of the physical port */\n+#define\tMC_CMD_TSA_INFO_IP_REASON_TX_ARP 0x0\n+/* enum: ARP probe packet received on the physical port */\n+#define\tMC_CMD_TSA_INFO_IP_REASON_RX_ARP_PROBE 0x1\n+/* enum: Gratuitous ARP packet received on the physical port */\n+#define\tMC_CMD_TSA_INFO_IP_REASON_RX_GRATUITOUS_ARP 0x2\n+/* enum: DHCP ACK packet received on the physical port */\n+#define\tMC_CMD_TSA_INFO_IP_REASON_RX_DHCP_ACK 0x3\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_LBN 24\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_WIDTH 1\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_LBN 25\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_WIDTH 7\n+/* IPV4 address retrieved from the sampled packets. This field is relevant only\n+ * when META_IPV4 is set to 1.\n+ */\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_IPV4_ADDR_OFST 8\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_IPV4_ADDR_LEN 4\n+/* Target MAC address retrieved from the sampled packet. */\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_OFST 12\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_LEN 1\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_NUM 6\n+\n+/* MC_CMD_TSA_INFO_IN_PKT_SAMPLE msgrequest:\n+ *\n+ * It is desireable for the TSA controller to learn the traffic pattern of\n+ * packets seen at the network port being monitored. In order to learn about\n+ * the traffic pattern, the TSA controller may want to sample packets seen at\n+ * the network port. Based on the packet samples that the TSA controller\n+ * receives from the adapter, the controller may choose to configure additional\n+ * black-list or white-list rules to allow or block packets as required.\n+ *\n+ * Although the entire sampled packet as seen on the network port is available\n+ * to the MC the length of sampled packet sent to controller is restricted by\n+ * MCDI payload size. Besides, the TSA controller does not require the entire\n+ * packet to make decisions about filter updates. Hence the packet sample being\n+ * passed to the controller is truncated to 128 bytes. This length is large\n+ * enough to hold the ethernet header, IP header and maximum length of\n+ * supported L4 protocol headers (IPv4 only, but can hold IPv6 header too, if\n+ * required in future).\n+ *\n+ * The intention is that any future changes to this message format that are not\n+ * backwards compatible will be defined with a new operation code.\n+ */\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_LEN 136\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_OFST 0\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_LEN 4\n+/* Additional metadata describing the sampled packet */\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_OFST 4\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_LEN 4\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_LBN 0\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_WIDTH 8\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_LBN 8\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_WIDTH 1\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_LBN 9\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_WIDTH 7\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_LBN 16\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_WIDTH 4\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_LBN 16\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_WIDTH 1\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_LBN 17\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_WIDTH 1\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_LBN 18\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_WIDTH 1\n+/* 128-byte raw prefix of the sampled packet which includes the ethernet\n+ * header, IP header and L4 protocol header (only IPv4 supported initially).\n+ * This provides the controller enough information about the packet sample to\n+ * report traffic patterns seen on a network port and to make decisions\n+ * concerning rule-set updates.\n+ */\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_OFST 8\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_LEN 1\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_NUM 128\n+\n+/* MC_CMD_TSA_INFO_OUT msgresponse */\n+#define\tMC_CMD_TSA_INFO_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_HOST_INFO\n+ * Commands to appply or retrieve host-related information from an adapter.\n+ * Doxbox reference SF-117371-SW\n+ */\n+#define\tMC_CMD_HOST_INFO 0x128\n+#undef\tMC_CMD_0x128_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x128_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_HOST_INFO_IN msgrequest */\n+#define\tMC_CMD_HOST_INFO_IN_LEN 4\n+/* sub-operation code info */\n+#define\tMC_CMD_HOST_INFO_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_HOST_INFO_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_HOST_INFO_IN_OP_LBN 0\n+#define\tMC_CMD_HOST_INFO_IN_OP_WIDTH 16\n+/* enum: Read a 16-byte unique host identifier from the adapter. This UUID\n+ * helps to identify the host that an adapter is plugged into. This identifier\n+ * is ideally the system UUID retrieved and set by the UEFI driver. If the UEFI\n+ * driver is unable to extract the system UUID, it would still set a random\n+ * 16-byte value into each supported SF adapter plugged into it. Host UUIDs may\n+ * change if the system is power-cycled, however, they persist across adapter\n+ * resets. If the host UUID was not set on an adapter, due to an unsupported\n+ * version of UEFI driver, then this command returns an error. Doxbox reference\n+ * - SF-117371-SW section 'Host UUID'.\n+ */\n+#define\tMC_CMD_HOST_INFO_OP_GET_UUID 0x0\n+/* enum: Set a 16-byte unique host identifier on the adapter to identify the\n+ * host that the adapter is plugged into. See MC_CMD_HOST_INFO_OP_GET_UUID for\n+ * further details.\n+ */\n+#define\tMC_CMD_HOST_INFO_OP_SET_UUID 0x1\n+\n+/* MC_CMD_HOST_INFO_IN_GET_UUID msgrequest */\n+#define\tMC_CMD_HOST_INFO_IN_GET_UUID_LEN 4\n+/* sub-operation code info */\n+#define\tMC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_OFST 0\n+#define\tMC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_LEN 4\n+\n+/* MC_CMD_HOST_INFO_OUT_GET_UUID msgresponse */\n+#define\tMC_CMD_HOST_INFO_OUT_GET_UUID_LEN 16\n+/* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID\n+ * for further details.\n+ */\n+#define\tMC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_OFST 0\n+#define\tMC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_LEN 1\n+#define\tMC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_NUM 16\n+\n+/* MC_CMD_HOST_INFO_IN_SET_UUID msgrequest */\n+#define\tMC_CMD_HOST_INFO_IN_SET_UUID_LEN 20\n+/* sub-operation code info */\n+#define\tMC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_OFST 0\n+#define\tMC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_LEN 4\n+/* 16-byte host UUID set on the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID for\n+ * further details.\n+ */\n+#define\tMC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_OFST 4\n+#define\tMC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_LEN 1\n+#define\tMC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_NUM 16\n+\n+/* MC_CMD_HOST_INFO_OUT_SET_UUID msgresponse */\n+#define\tMC_CMD_HOST_INFO_OUT_SET_UUID_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TSAN_INFO\n+ * Get TSA adapter information. TSA controllers query each TSA adapter to learn\n+ * some configuration parameters of each adapter. Doxbox reference SF-117371-SW\n+ * section 'Adapter Information'\n+ */\n+#define\tMC_CMD_TSAN_INFO 0x129\n+#undef\tMC_CMD_0x129_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x129_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TSAN_INFO_IN msgrequest */\n+#define\tMC_CMD_TSAN_INFO_IN_LEN 4\n+/* sub-operation code info */\n+#define\tMC_CMD_TSAN_INFO_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_TSAN_INFO_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_TSAN_INFO_IN_OP_LBN 0\n+#define\tMC_CMD_TSAN_INFO_IN_OP_WIDTH 16\n+/* enum: Read configuration parameters and IDs that uniquely identify an\n+ * adapter. The parameters include - host identification, adapter\n+ * identification string and number of physical ports on the adapter.\n+ */\n+#define\tMC_CMD_TSAN_INFO_OP_GET_CFG 0x0\n+\n+/* MC_CMD_TSAN_INFO_IN_GET_CFG msgrequest */\n+#define\tMC_CMD_TSAN_INFO_IN_GET_CFG_LEN 4\n+/* sub-operation code info */\n+#define\tMC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_OFST 0\n+#define\tMC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_LEN 4\n+\n+/* MC_CMD_TSAN_INFO_OUT_GET_CFG msgresponse */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_LEN 26\n+/* Information about the configuration parameters returned in this response. */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_OFST 0\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_LEN 4\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_LBN 0\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_WIDTH 16\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_LBN 0\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_WIDTH 1\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_LBN 16\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_WIDTH 8\n+/* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID\n+ * for further details.\n+ */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_OFST 4\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_LEN 1\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_NUM 16\n+/* A unique identifier per adapter. The base MAC address of the card is used\n+ * for this purpose.\n+ */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_OFST 20\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_LEN 1\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_NUM 6\n+\n+\n+/***********************************/\n+/* MC_CMD_TSA_STATISTICS\n+ * TSA adapter statistics operations.\n+ */\n+#define\tMC_CMD_TSA_STATISTICS 0x130\n+#undef\tMC_CMD_0x130_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TSA_STATISTICS_IN msgrequest */\n+#define\tMC_CMD_TSA_STATISTICS_IN_LEN 4\n+/* TSA statistics sub-operation code */\n+#define\tMC_CMD_TSA_STATISTICS_IN_OP_CODE_OFST 0\n+#define\tMC_CMD_TSA_STATISTICS_IN_OP_CODE_LEN 4\n+/* enum: Get the configuration parameters that describe the TSA statistics\n+ * layout on the adapter.\n+ */\n+#define\tMC_CMD_TSA_STATISTICS_OP_GET_CONFIG  0x0\n+/* enum: Read and/or clear TSA statistics counters. */\n+#define\tMC_CMD_TSA_STATISTICS_OP_READ_CLEAR  0x1\n+\n+/* MC_CMD_TSA_STATISTICS_IN_GET_CONFIG msgrequest */\n+#define\tMC_CMD_TSA_STATISTICS_IN_GET_CONFIG_LEN 4\n+/* TSA statistics sub-operation code */\n+#define\tMC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_OFST 0\n+#define\tMC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_LEN 4\n+\n+/* MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG msgresponse */\n+#define\tMC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_LEN 8\n+/* Maximum number of TSA statistics counters in each direction of dataflow\n+ * supported on the card. Note that the statistics counters are always\n+ * allocated in pairs, i.e. a counter ID is associated with one Tx and one Rx\n+ * counter.\n+ */\n+#define\tMC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_OFST 0\n+#define\tMC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_LEN 4\n+/* Width of each statistics counter (represented in bits). This gives an\n+ * indication of wrap point to the user.\n+ */\n+#define\tMC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_STATS_WIDTH_OFST 4\n+#define\tMC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_STATS_WIDTH_LEN 4\n+\n+/* MC_CMD_TSA_STATISTICS_IN_READ_CLEAR msgrequest */\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMIN 20\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMAX 252\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LEN(num) (16+4*(num))\n+/* TSA statistics sub-operation code */\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_OFST 0\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_LEN 4\n+/* Parameters describing the statistics operation */\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_OFST 4\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_LEN 4\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_LBN 0\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_WIDTH 1\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_LBN 1\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_WIDTH 1\n+/* Counter ID list specification type */\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_MODE_OFST 8\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_MODE_LEN 4\n+/* enum: The statistics counters are specified as an unordered list of\n+ * individual counter ID.\n+ */\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LIST  0x0\n+/* enum: The statistics counters are specified as a range of consecutive\n+ * counter IDs.\n+ */\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_RANGE  0x1\n+/* Number of statistics counters */\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_OFST 12\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_LEN 4\n+/* Counter IDs to be read/cleared. When mode is set to LIST, this entry holds a\n+ * list of counter IDs to be operated on. When mode is set to RANGE, this entry\n+ * holds a single counter ID representing the start of the range of counter IDs\n+ * to be operated on.\n+ */\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_OFST 16\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_LEN 4\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_MINNUM 1\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_MAXNUM 59\n+\n+/* MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR msgresponse */\n+#define\tMC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMIN 24\n+#define\tMC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMAX 248\n+#define\tMC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LEN(num) (8+16*(num))\n+/* Number of statistics counters returned in this response */\n+#define\tMC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_OFST 0\n+#define\tMC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_LEN 4\n+/* MC_TSA_STATISTICS_ENTRY Note that this field is expected to start at a\n+ * 64-bit aligned offset\n+ */\n+#define\tMC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_OFST 8\n+#define\tMC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_LEN 16\n+#define\tMC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_MINNUM 1\n+#define\tMC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_MAXNUM 15\n+\n+/* MC_TSA_STATISTICS_ENTRY structuredef */\n+#define\tMC_TSA_STATISTICS_ENTRY_LEN 16\n+/* Tx statistics counter */\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_OFST 0\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_LEN 8\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_LO_OFST 0\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_HI_OFST 4\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_LBN 0\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_WIDTH 64\n+/* Rx statistics counter */\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_OFST 8\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_LEN 8\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_LO_OFST 8\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_HI_OFST 12\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_LBN 64\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_WIDTH 64\n+\n+\n+/***********************************/\n+/* MC_CMD_ERASE_INITIAL_NIC_SECRET\n+ * This request causes the NIC to find the initial NIC secret (programmed\n+ * during ATE) in XPM memory and if and only if the NIC has already been\n+ * rekeyed with MC_CMD_REKEY, erase it. This is used by manftest after\n+ * installing TSA binding certificates. See SF-117631-TC.\n+ */\n+#define\tMC_CMD_ERASE_INITIAL_NIC_SECRET 0x131\n+#undef\tMC_CMD_0x131_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_ERASE_INITIAL_NIC_SECRET_IN msgrequest */\n+#define\tMC_CMD_ERASE_INITIAL_NIC_SECRET_IN_LEN 0\n+\n+/* MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT msgresponse */\n+#define\tMC_CMD_ERASE_INITIAL_NIC_SECRET_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TSA_CONFIG\n+ * TSA adapter configuration operations. This command is used to prepare the\n+ * NIC for TSA binding.\n+ */\n+#define\tMC_CMD_TSA_CONFIG 0x64\n+#undef\tMC_CMD_0x64_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x64_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TSA_CONFIG_IN msgrequest */\n+#define\tMC_CMD_TSA_CONFIG_IN_LEN 4\n+/* TSA configuration sub-operation code */\n+#define\tMC_CMD_TSA_CONFIG_IN_OP_OFST 0\n+#define\tMC_CMD_TSA_CONFIG_IN_OP_LEN 4\n+/* enum: Append a single item to the tsa_config partition. Items will be\n+ * encrypted unless they are declared as non-sensitive. Returns\n+ * MC_CMD_ERR_EEXIST if the tag is already present.\n+ */\n+#define\tMC_CMD_TSA_CONFIG_OP_APPEND  0x1\n+/* enum: Reset the tsa_config partition to a clean state. */\n+#define\tMC_CMD_TSA_CONFIG_OP_RESET  0x2\n+/* enum: Read back a configured item from tsa_config partition. Returns\n+ * MC_CMD_ERR_ENOENT if the item doesn't exist, or MC_CMD_ERR_EPERM if the item\n+ * is declared as sensitive (i.e. is encrypted).\n+ */\n+#define\tMC_CMD_TSA_CONFIG_OP_READ  0x3\n+\n+/* MC_CMD_TSA_CONFIG_IN_APPEND msgrequest */\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_LENMIN 12\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_LENMAX 252\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_LEN(num) (12+1*(num))\n+/* TSA configuration sub-operation code. The value shall be\n+ * MC_CMD_TSA_CONFIG_OP_APPEND.\n+ */\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_OP_OFST 0\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_OP_LEN 4\n+/* The tag to be appended */\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_TAG_OFST 4\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_TAG_LEN 4\n+/* The length of the data in bytes */\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_LENGTH_OFST 8\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_LENGTH_LEN 4\n+/* The item data */\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_DATA_OFST 12\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_DATA_LEN 1\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_DATA_MINNUM 0\n+#define\tMC_CMD_TSA_CONFIG_IN_APPEND_DATA_MAXNUM 240\n+\n+/* MC_CMD_TSA_CONFIG_OUT_APPEND msgresponse */\n+#define\tMC_CMD_TSA_CONFIG_OUT_APPEND_LEN 0\n+\n+/* MC_CMD_TSA_CONFIG_IN_RESET msgrequest */\n+#define\tMC_CMD_TSA_CONFIG_IN_RESET_LEN 4\n+/* TSA configuration sub-operation code. The value shall be\n+ * MC_CMD_TSA_CONFIG_OP_RESET.\n+ */\n+#define\tMC_CMD_TSA_CONFIG_IN_RESET_OP_OFST 0\n+#define\tMC_CMD_TSA_CONFIG_IN_RESET_OP_LEN 4\n+\n+/* MC_CMD_TSA_CONFIG_OUT_RESET msgresponse */\n+#define\tMC_CMD_TSA_CONFIG_OUT_RESET_LEN 0\n+\n+/* MC_CMD_TSA_CONFIG_IN_READ msgrequest */\n+#define\tMC_CMD_TSA_CONFIG_IN_READ_LEN 8\n+/* TSA configuration sub-operation code. The value shall be\n+ * MC_CMD_TSA_CONFIG_OP_READ.\n+ */\n+#define\tMC_CMD_TSA_CONFIG_IN_READ_OP_OFST 0\n+#define\tMC_CMD_TSA_CONFIG_IN_READ_OP_LEN 4\n+/* The tag to be read */\n+#define\tMC_CMD_TSA_CONFIG_IN_READ_TAG_OFST 4\n+#define\tMC_CMD_TSA_CONFIG_IN_READ_TAG_LEN 4\n+\n+/* MC_CMD_TSA_CONFIG_OUT_READ msgresponse */\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_LENMIN 8\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_LENMAX 252\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_LEN(num) (8+1*(num))\n+/* The tag that was read */\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_TAG_OFST 0\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_TAG_LEN 4\n+/* The length of the data in bytes */\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_LENGTH_OFST 4\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_LENGTH_LEN 4\n+/* The data of the item. */\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_DATA_OFST 8\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_DATA_LEN 1\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_DATA_MINNUM 0\n+#define\tMC_CMD_TSA_CONFIG_OUT_READ_DATA_MAXNUM 244\n+\n+/* MC_TSA_IPV4_ITEM structuredef */\n+#define\tMC_TSA_IPV4_ITEM_LEN 8\n+/* Additional metadata describing the IP address information such as the\n+ * physical port number the address is being used on. Unused space in this\n+ * field is reserved for future expansion.\n+ */\n+#define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_META_OFST 0\n+#define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_META_LEN 4\n+#define\tMC_TSA_IPV4_ITEM_PORT_IDX_LBN 0\n+#define\tMC_TSA_IPV4_ITEM_PORT_IDX_WIDTH 8\n+#define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_META_LBN 0\n+#define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_META_WIDTH 32\n+/* The IPv4 address in little endian byte order. */\n+#define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_OFST 4\n+#define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_LEN 4\n+#define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_LBN 32\n+#define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_TSA_IPADDR\n+ * TSA operations relating to the monitoring and expiry of local IP addresses\n+ * discovered by the controller. These commands are sent from a TSA controller\n+ * to a TSA adapter.\n+ */\n+#define\tMC_CMD_TSA_IPADDR 0x65\n+#undef\tMC_CMD_0x65_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TSA_IPADDR_IN msgrequest */\n+#define\tMC_CMD_TSA_IPADDR_IN_LEN 4\n+/* Header containing information to identify which sub-operation of this\n+ * command to perform. The header contains a 16-bit op-code. Unused space in\n+ * this field is reserved for future expansion.\n+ */\n+#define\tMC_CMD_TSA_IPADDR_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_TSA_IPADDR_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_TSA_IPADDR_IN_OP_LBN 0\n+#define\tMC_CMD_TSA_IPADDR_IN_OP_WIDTH 16\n+/* enum: Request that the adapter verifies that the IPv4 addresses supplied are\n+ * still in use by the host by sending ARP probes to the host. The MC does not\n+ * wait for a response to the probes and sends an MCDI response to the\n+ * controller once the probes have been sent to the host. The response to the\n+ * probes (if there are any) will be forwarded to the controller using\n+ * MC_CMD_TSA_INFO alerts.\n+ */\n+#define\tMC_CMD_TSA_IPADDR_OP_VALIDATE_IPV4  0x1\n+/* enum: Notify the adapter that one or more IPv4 addresses are no longer valid\n+ * for the host of the adapter. The adapter should remove the IPv4 addresses\n+ * from its local cache.\n+ */\n+#define\tMC_CMD_TSA_IPADDR_OP_REMOVE_IPV4  0x2\n+\n+/* MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4 msgrequest */\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMIN 16\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMAX 248\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LEN(num) (8+8*(num))\n+/* Header containing information to identify which sub-operation of this\n+ * command to perform. The header contains a 16-bit op-code. Unused space in\n+ * this field is reserved for future expansion.\n+ */\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_OFST 0\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_LEN 4\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_LBN 0\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_WIDTH 16\n+/* Number of IPv4 addresses to validate. */\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_NUM_ITEMS_OFST 4\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_NUM_ITEMS_LEN 4\n+/* The IPv4 addresses to validate, in struct MC_TSA_IPV4_ITEM format. */\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_OFST 8\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LEN 8\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_OFST 8\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_OFST 12\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MINNUM 1\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM 30\n+\n+/* MC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4 msgresponse */\n+#define\tMC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4_LEN 0\n+\n+/* MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4 msgrequest */\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMIN 16\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMAX 248\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LEN(num) (8+8*(num))\n+/* Header containing information to identify which sub-operation of this\n+ * command to perform. The header contains a 16-bit op-code. Unused space in\n+ * this field is reserved for future expansion.\n+ */\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_OFST 0\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_LEN 4\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_LBN 0\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_WIDTH 16\n+/* Number of IPv4 addresses to remove. */\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_NUM_ITEMS_OFST 4\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_NUM_ITEMS_LEN 4\n+/* The IPv4 addresses that have expired, in struct MC_TSA_IPV4_ITEM format. */\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_OFST 8\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LEN 8\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_OFST 8\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_OFST 12\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MINNUM 1\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM 30\n+\n+/* MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4 msgresponse */\n+#define\tMC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SECURE_NIC_INFO\n+ * Get secure NIC information. While many of the features reported by these\n+ * commands are related to TSA, they must be supported in firmware where TSA is\n+ * disabled.\n+ */\n+#define\tMC_CMD_SECURE_NIC_INFO 0x132\n+#undef\tMC_CMD_0x132_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SECURE_NIC_INFO_IN msgrequest */\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_LEN 4\n+/* sub-operation code info */\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_OP_LBN 0\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_OP_WIDTH 16\n+/* enum: Get the status of various security settings, all signed along with a\n+ * challenge chosen by the host.\n+ */\n+#define\tMC_CMD_SECURE_NIC_INFO_OP_STATUS  0x0\n+\n+/* MC_CMD_SECURE_NIC_INFO_IN_STATUS msgrequest */\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_LEN 24\n+/* sub-operation code, must be MC_CMD_SECURE_NIC_INFO_OP_STATUS */\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_OFST 0\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_LEN 4\n+/* Type of key to be used to sign response. */\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_OFST 4\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_LEN 4\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_UNUSED  0x0 /* enum */\n+/* enum: Solarflare adapter authentication key, installed by Manftest. */\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_SF_ADAPTER_AUTH  0x1\n+/* enum: TSA binding key, installed after adapter is bound to a TSA controller.\n+ * This is not supported in firmware which does not support TSA.\n+ */\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_TSA_BINDING  0x2\n+/* enum: Customer adapter authentication key. Installed by the customer in the\n+ * field, but otherwise similar to the Solarflare adapter authentication key.\n+ */\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_CUSTOMER_ADAPTER_AUTH  0x3\n+/* Random challenge generated by the host. */\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_OFST 8\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_LEN 16\n+\n+/* MC_CMD_SECURE_NIC_INFO_OUT_STATUS msgresponse */\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_LEN 420\n+/* Length of the signature in MSG_SIGNATURE. */\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_OFST 0\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_LEN 4\n+/* Signature over the message, starting at MESSAGE_TYPE and continuing to the\n+ * end of the MCDI response, allowing the message format to be extended. The\n+ * signature uses ECDSA 384 encoding in ASN.1 format. It has variable length,\n+ * with a maximum of 384 bytes.\n+ */\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_OFST 4\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN 384\n+/* Enum value indicating the type of response. This protects against chosen\n+ * message attacks. The enum values are random rather than sequential to make\n+ * it unlikely that values will be reused should other commands in a different\n+ * namespace need to create signed messages.\n+ */\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_MESSAGE_TYPE_OFST 388\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_MESSAGE_TYPE_LEN 4\n+/* enum: Message type value for the response to a\n+ * MC_CMD_SECURE_NIC_INFO_IN_STATUS message.\n+ */\n+#define\tMC_CMD_SECURE_NIC_INFO_STATUS  0xdb4\n+/* The challenge provided by the host in the MC_CMD_SECURE_NIC_INFO_IN_STATUS\n+ * message\n+ */\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_CHALLENGE_OFST 392\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_CHALLENGE_LEN 16\n+/* The first 32 bits of XPM memory, which include security and flag bits, die\n+ * ID and chip ID revision. The meaning of these bits is defined in\n+ * mc/include/mc/xpm.h in the firmwaresrc repository.\n+ */\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_XPM_STATUS_BITS_OFST 408\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_XPM_STATUS_BITS_LEN 4\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_A_OFST 412\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_A_LEN 2\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_B_OFST 414\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_B_LEN 2\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_C_OFST 416\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_C_LEN 2\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_OFST 418\n+#define\tMC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_LEN 2\n+\n+\n+/***********************************/\n+/* MC_CMD_TSA_TEST\n+ * A simple ping-pong command just to test the adapter<>controller MCDI\n+ * communication channel. This command makes not changes to the TSA adapter's\n+ * internal state. It is used by the controller just to verify that the MCDI\n+ * communication channel is working fine. This command takes no additonal\n+ * parameters in request or response.\n+ */\n+#define\tMC_CMD_TSA_TEST 0x125\n+#undef\tMC_CMD_0x125_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TSA_TEST_IN msgrequest */\n+#define\tMC_CMD_TSA_TEST_IN_LEN 0\n+\n+/* MC_CMD_TSA_TEST_OUT msgresponse */\n+#define\tMC_CMD_TSA_TEST_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TSA_RULESET_OVERRIDE\n+ * Override TSA ruleset that is currently active on the adapter. This operation\n+ * does not modify the ruleset itself. This operation provides a mechanism to\n+ * apply an allow-all or deny-all operation on all packets, thereby completely\n+ * ignoring the rule-set configured on the adapter. The main purpose of this\n+ * operation is to provide a deterministic state to the TSA firewall during\n+ * rule-set transitions.\n+ */\n+#define\tMC_CMD_TSA_RULESET_OVERRIDE 0x12a\n+#undef\tMC_CMD_0x12a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TSA_RULESET_OVERRIDE_IN msgrequest */\n+#define\tMC_CMD_TSA_RULESET_OVERRIDE_IN_LEN 4\n+/* The override state to apply. */\n+#define\tMC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_OFST 0\n+#define\tMC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_LEN 4\n+/* enum: No override in place - the existing ruleset is in operation. */\n+#define\tMC_CMD_TSA_RULESET_OVERRIDE_NONE  0x0\n+/* enum: Block all packets seen on all datapath channel except those packets\n+ * required for basic configuration of the TSA NIC such as ARPs and TSA-\n+ * communication traffic. Such exceptional traffic is handled differently\n+ * compared to TSA rulesets.\n+ */\n+#define\tMC_CMD_TSA_RULESET_OVERRIDE_BLOCK  0x1\n+/* enum: Allow all packets through all datapath channel. The TSA adapter\n+ * behaves like a normal NIC without any firewalls.\n+ */\n+#define\tMC_CMD_TSA_RULESET_OVERRIDE_ALLOW  0x2\n+\n+/* MC_CMD_TSA_RULESET_OVERRIDE_OUT msgresponse */\n+#define\tMC_CMD_TSA_RULESET_OVERRIDE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TSAC_REQUEST\n+ * Generic command to send requests from a TSA controller to a TSA adapter.\n+ * Specific usage is determined by the TYPE field.\n+ */\n+#define\tMC_CMD_TSAC_REQUEST 0x12b\n+#undef\tMC_CMD_0x12b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_TSAC_REQUEST_IN msgrequest */\n+#define\tMC_CMD_TSAC_REQUEST_IN_LEN 4\n+/* The type of request from the controller. */\n+#define\tMC_CMD_TSAC_REQUEST_IN_TYPE_OFST 0\n+#define\tMC_CMD_TSAC_REQUEST_IN_TYPE_LEN 4\n+/* enum: Request the adapter to resend localIP information from it's cache. The\n+ * command does not return any IP address information; IP addresses are sent as\n+ * TSA notifications as descibed in MC_CMD_TSA_INFO_IN_LOCAL_IP.\n+ */\n+#define\tMC_CMD_TSAC_REQUEST_LOCALIP  0x0\n+\n+/* MC_CMD_TSAC_REQUEST_OUT msgresponse */\n+#define\tMC_CMD_TSAC_REQUEST_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SUC_VERSION\n+ * Get the version of the SUC\n+ */\n+#define\tMC_CMD_SUC_VERSION 0x134\n+#undef\tMC_CMD_0x134_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SUC_VERSION_IN msgrequest */\n+#define\tMC_CMD_SUC_VERSION_IN_LEN 0\n+\n+/* MC_CMD_SUC_VERSION_OUT msgresponse */\n+#define\tMC_CMD_SUC_VERSION_OUT_LEN 24\n+/* The SUC firmware version as four numbers - a.b.c.d */\n+#define\tMC_CMD_SUC_VERSION_OUT_VERSION_OFST 0\n+#define\tMC_CMD_SUC_VERSION_OUT_VERSION_LEN 4\n+#define\tMC_CMD_SUC_VERSION_OUT_VERSION_NUM 4\n+/* The date, in seconds since the Unix epoch, when the firmware image was\n+ * built.\n+ */\n+#define\tMC_CMD_SUC_VERSION_OUT_BUILD_DATE_OFST 16\n+#define\tMC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4\n+/* The ID of the SUC chip. This is specific to the platform but typically\n+ * indicates family, memory sizes etc. See SF-116728-SW for further details.\n+ */\n+#define\tMC_CMD_SUC_VERSION_OUT_CHIP_ID_OFST 20\n+#define\tMC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_SUC_MANFTEST\n+ * Operations to support manftest on SUC based systems.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST 0x135\n+#undef\tMC_CMD_0x135_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_SUC_MANFTEST_IN msgrequest */\n+#define\tMC_CMD_SUC_MANFTEST_IN_LEN 4\n+/* The manftest operation to be performed. */\n+#define\tMC_CMD_SUC_MANFTEST_IN_OP_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_IN_OP_LEN 4\n+/* enum: Read serial number and use count. */\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_READ  0x0\n+/* enum: Update use count on wearout adapter. */\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_UPDATE  0x1\n+/* enum: Start an ADC calibration. */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START  0x2\n+/* enum: Read the status of an ADC calibration. */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS  0x3\n+/* enum: Read the results of an ADC calibration. */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT  0x4\n+/* enum: Read the PCIe configuration. */\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ  0x5\n+/* enum: Write the PCIe configuration. */\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE  0x6\n+\n+/* MC_CMD_SUC_MANFTEST_OUT msgresponse */\n+#define\tMC_CMD_SUC_MANFTEST_OUT_LEN 0\n+\n+/* MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN msgrequest */\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_LEN 4\n+/* The manftest operation to be performed. This must be\n+ * MC_CMD_SUC_MANFTEST_WEAROUT_READ.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_LEN 4\n+\n+/* MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT msgresponse */\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_LEN 20\n+/* The serial number of the wearout adapter, see SF-112717-PR for format. */\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_LEN 16\n+/* The use count of the wearout adapter. */\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_USE_COUNT_OFST 16\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_USE_COUNT_LEN 4\n+\n+/* MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN msgrequest */\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_LEN 4\n+/* The manftest operation to be performed. This must be\n+ * MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_LEN 4\n+\n+/* MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT msgresponse */\n+#define\tMC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT_LEN 0\n+\n+/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN msgrequest */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_LEN 4\n+/* The manftest operation to be performed. This must be\n+ * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_LEN 4\n+\n+/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT msgresponse */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT_LEN 0\n+\n+/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN msgrequest */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_LEN 4\n+/* The manftest operation to be performed. This must be\n+ * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_LEN 4\n+\n+/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT msgresponse */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_LEN 4\n+/* The combined status of the calibration operation. */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_LBN 0\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_WIDTH 1\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_LBN 1\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_WIDTH 1\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_LBN 2\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_WIDTH 4\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_LBN 6\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_WIDTH 2\n+\n+/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN msgrequest */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_LEN 4\n+/* The manftest operation to be performed. This must be\n+ * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_LEN 4\n+\n+/* MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT msgresponse */\n+#define\tMC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_LEN 12\n+/* The set of calibration results. */\n+#define\tMC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_OFST 0\n+#define\tMC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_LEN 4\n+#define\tMC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_NUM 3\n+\n+/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN msgrequest */\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_LEN 4\n+/* The manftest operation to be performed. This must be\n+ * MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_LEN 4\n+\n+/* MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT msgresponse */\n+#define\tMC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_LEN 4\n+/* The PCIe vendor ID. */\n+#define\tMC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_VENDOR_ID_OFST 0\n+#define\tMC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_VENDOR_ID_LEN 2\n+/* The PCIe device ID. */\n+#define\tMC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_DEVICE_ID_OFST 2\n+#define\tMC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_DEVICE_ID_LEN 2\n+\n+/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN msgrequest */\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_LEN 8\n+/* The manftest operation to be performed. This must be\n+ * MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_LEN 4\n+/* The PCIe vendor ID. */\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_VENDOR_ID_OFST 4\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_VENDOR_ID_LEN 2\n+/* The PCIe device ID. */\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_DEVICE_ID_OFST 6\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_DEVICE_ID_LEN 2\n+\n+/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT msgresponse */\n+#define\tMC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT_LEN 0\n+\n #endif /* _SIENA_MC_DRIVER_PCOL_H */\n /*! \\cidoxg_end */\ndiff --git a/drivers/net/sfc/base/efx_regs_mcdi_aoe.h b/drivers/net/sfc/base/efx_regs_mcdi_aoe.h\nnew file mode 100644\nindex 0000000..033d281\n--- /dev/null\n+++ b/drivers/net/sfc/base/efx_regs_mcdi_aoe.h\n@@ -0,0 +1,2913 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ *\n+ * Copyright 2008-2018 Solarflare Communications Inc.\n+ * All rights reserved.\n+ */\n+\n+/*! \\cidoxg_firmware_mc_cmd */\n+\n+#ifndef _SIENA_MC_DRIVER_PCOL_AOE_H\n+#define\t_SIENA_MC_DRIVER_PCOL_AOE_H\n+\n+\n+\n+/***********************************/\n+/* MC_CMD_FC\n+ * Perform an FC operation\n+ */\n+#define\tMC_CMD_FC 0x9\n+\n+/* MC_CMD_FC_IN msgrequest */\n+#define\tMC_CMD_FC_IN_LEN 4\n+#define\tMC_CMD_FC_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_FC_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_FC_IN_OP_LBN 0\n+#define\tMC_CMD_FC_IN_OP_WIDTH 8\n+/* enum: NULL MCDI command to FC. */\n+#define\tMC_CMD_FC_OP_NULL 0x1\n+/* enum: Unused opcode */\n+#define\tMC_CMD_FC_OP_UNUSED 0x2\n+/* enum: MAC driver commands */\n+#define\tMC_CMD_FC_OP_MAC 0x3\n+/* enum: Read FC memory */\n+#define\tMC_CMD_FC_OP_READ32 0x4\n+/* enum: Write to FC memory */\n+#define\tMC_CMD_FC_OP_WRITE32 0x5\n+/* enum: Read FC memory */\n+#define\tMC_CMD_FC_OP_TRC_READ 0x6\n+/* enum: Write to FC memory */\n+#define\tMC_CMD_FC_OP_TRC_WRITE 0x7\n+/* enum: FC firmware Version */\n+#define\tMC_CMD_FC_OP_GET_VERSION 0x8\n+/* enum: Read FC memory */\n+#define\tMC_CMD_FC_OP_TRC_RX_READ 0x9\n+/* enum: Write to FC memory */\n+#define\tMC_CMD_FC_OP_TRC_RX_WRITE 0xa\n+/* enum: SFP parameters */\n+#define\tMC_CMD_FC_OP_SFP 0xb\n+/* enum: DDR3 test */\n+#define\tMC_CMD_FC_OP_DDR_TEST 0xc\n+/* enum: Get Crash context from FC */\n+#define\tMC_CMD_FC_OP_GET_ASSERT 0xd\n+/* enum: Get FPGA Build registers */\n+#define\tMC_CMD_FC_OP_FPGA_BUILD 0xe\n+/* enum: Read map support commands */\n+#define\tMC_CMD_FC_OP_READ_MAP 0xf\n+/* enum: FC Capabilities */\n+#define\tMC_CMD_FC_OP_CAPABILITIES 0x10\n+/* enum: FC Global flags */\n+#define\tMC_CMD_FC_OP_GLOBAL_FLAGS 0x11\n+/* enum: FC IO using relative addressing modes */\n+#define\tMC_CMD_FC_OP_IO_REL 0x12\n+/* enum: FPGA link information */\n+#define\tMC_CMD_FC_OP_UHLINK 0x13\n+/* enum: Configure loopbacks and link on FPGA ports */\n+#define\tMC_CMD_FC_OP_SET_LINK 0x14\n+/* enum: Licensing operations relating to AOE */\n+#define\tMC_CMD_FC_OP_LICENSE 0x15\n+/* enum: Startup information to the FC */\n+#define\tMC_CMD_FC_OP_STARTUP 0x16\n+/* enum: Configure a DMA read */\n+#define\tMC_CMD_FC_OP_DMA 0x17\n+/* enum: Configure a timed read */\n+#define\tMC_CMD_FC_OP_TIMED_READ 0x18\n+/* enum: Control UART logging */\n+#define\tMC_CMD_FC_OP_LOG 0x19\n+/* enum: Get the value of a given clock_id */\n+#define\tMC_CMD_FC_OP_CLOCK 0x1a\n+/* enum: DDR3/QDR3 parameters */\n+#define\tMC_CMD_FC_OP_DDR 0x1b\n+/* enum: PTP and timestamp control */\n+#define\tMC_CMD_FC_OP_TIMESTAMP 0x1c\n+/* enum: Commands for SPI Flash interface */\n+#define\tMC_CMD_FC_OP_SPI 0x1d\n+/* enum: Commands for diagnostic components */\n+#define\tMC_CMD_FC_OP_DIAG 0x1e\n+/* enum: External AOE port. */\n+#define\tMC_CMD_FC_IN_PORT_EXT_OFST 0x0\n+/* enum: Internal AOE port. */\n+#define\tMC_CMD_FC_IN_PORT_INT_OFST 0x40\n+\n+/* MC_CMD_FC_IN_NULL msgrequest */\n+#define\tMC_CMD_FC_IN_NULL_LEN 4\n+#define\tMC_CMD_FC_IN_CMD_OFST 0\n+#define\tMC_CMD_FC_IN_CMD_LEN 4\n+\n+/* MC_CMD_FC_IN_PHY msgrequest */\n+#define\tMC_CMD_FC_IN_PHY_LEN 5\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/* FC PHY driver operation code */\n+#define\tMC_CMD_FC_IN_PHY_OP_OFST 4\n+#define\tMC_CMD_FC_IN_PHY_OP_LEN 1\n+/* enum: PHY init handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_INIT 0x1\n+/* enum: PHY reconfigure handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2\n+/* enum: PHY reboot handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_REBOOT 0x3\n+/* enum: PHY get_supported_cap handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4\n+/* enum: PHY get_config handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5\n+/* enum: PHY get_media_info handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6\n+/* enum: PHY set_led handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_SET_LED 0x7\n+/* enum: PHY lasi_interrupt handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8\n+/* enum: PHY check_link handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9\n+/* enum: PHY fill_stats handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa\n+/* enum: PHY bpx_link_state_changed handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb\n+/* enum: PHY get_state handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_STATE 0xc\n+/* enum: PHY start_bist handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_START_BIST 0xd\n+/* enum: PHY poll_bist handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe\n+/* enum: PHY nvram_test handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf\n+/* enum: PHY relinquish handler */\n+#define\tMC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10\n+/* enum: PHY read connection from FC - may be not required */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11\n+/* enum: PHY read flags from FC - may be not required */\n+#define\tMC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12\n+\n+/* MC_CMD_FC_IN_PHY_INIT msgrequest */\n+#define\tMC_CMD_FC_IN_PHY_INIT_LEN 4\n+#define\tMC_CMD_FC_IN_PHY_CMD_OFST 0\n+#define\tMC_CMD_FC_IN_PHY_CMD_LEN 4\n+\n+/* MC_CMD_FC_IN_MAC msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_MAC_HEADER_OFST 4\n+#define\tMC_CMD_FC_IN_MAC_HEADER_LEN 4\n+#define\tMC_CMD_FC_IN_MAC_OP_LBN 0\n+#define\tMC_CMD_FC_IN_MAC_OP_WIDTH 8\n+/* enum: MAC reconfigure handler */\n+#define\tMC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1\n+/* enum: MAC Set command - same as MC_CMD_SET_MAC */\n+#define\tMC_CMD_FC_OP_MAC_OP_SET_LINK 0x2\n+/* enum: MAC statistics */\n+#define\tMC_CMD_FC_OP_MAC_OP_GET_STATS 0x3\n+/* enum: MAC RX statistics */\n+#define\tMC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6\n+/* enum: MAC TX statistics */\n+#define\tMC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7\n+/* enum: MAC Read status */\n+#define\tMC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8\n+#define\tMC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8\n+#define\tMC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8\n+/* enum: External FPGA port. */\n+#define\tMC_CMD_FC_PORT_EXT 0x0\n+/* enum: Internal Siena-facing FPGA ports. */\n+#define\tMC_CMD_FC_PORT_INT 0x1\n+#define\tMC_CMD_FC_IN_MAC_PORT_IDX_LBN 16\n+#define\tMC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8\n+#define\tMC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24\n+#define\tMC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8\n+/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are\n+ * irrelevant. Port number is derived from pci_fn; passed in FC header.\n+ */\n+#define\tMC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0\n+/* enum: Override default port number. Port number determined by fields\n+ * PORT_TYPE and PORT_IDX.\n+ */\n+#define\tMC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1\n+\n+/* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */\n+\n+/* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_LEN 32\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */\n+/* MTU size */\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_MTU_LEN 4\n+/* Drain Tx FIFO */\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_DRAIN_LEN 4\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_FCNTL_LEN 4\n+\n+/* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_READ_STATUS_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */\n+\n+/* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */\n+\n+/* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */\n+\n+/* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */\n+/* MC Statistics index */\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1\n+/* Number of statistics to read */\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_NUM_LEN 4\n+#define\tMC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */\n+#define\tMC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */\n+\n+/* MC_CMD_FC_IN_READ32 msgrequest */\n+#define\tMC_CMD_FC_IN_READ32_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_READ32_ADDR_HI_OFST 4\n+#define\tMC_CMD_FC_IN_READ32_ADDR_HI_LEN 4\n+#define\tMC_CMD_FC_IN_READ32_ADDR_LO_OFST 8\n+#define\tMC_CMD_FC_IN_READ32_ADDR_LO_LEN 4\n+#define\tMC_CMD_FC_IN_READ32_NUMWORDS_OFST 12\n+#define\tMC_CMD_FC_IN_READ32_NUMWORDS_LEN 4\n+\n+/* MC_CMD_FC_IN_WRITE32 msgrequest */\n+#define\tMC_CMD_FC_IN_WRITE32_LENMIN 16\n+#define\tMC_CMD_FC_IN_WRITE32_LENMAX 252\n+#define\tMC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num))\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4\n+#define\tMC_CMD_FC_IN_WRITE32_ADDR_HI_LEN 4\n+#define\tMC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8\n+#define\tMC_CMD_FC_IN_WRITE32_ADDR_LO_LEN 4\n+#define\tMC_CMD_FC_IN_WRITE32_BUFFER_OFST 12\n+#define\tMC_CMD_FC_IN_WRITE32_BUFFER_LEN 4\n+#define\tMC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60\n+\n+/* MC_CMD_FC_IN_TRC_READ msgrequest */\n+#define\tMC_CMD_FC_IN_TRC_READ_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_TRC_READ_TRC_OFST 4\n+#define\tMC_CMD_FC_IN_TRC_READ_TRC_LEN 4\n+#define\tMC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8\n+#define\tMC_CMD_FC_IN_TRC_READ_CHANNEL_LEN 4\n+\n+/* MC_CMD_FC_IN_TRC_WRITE msgrequest */\n+#define\tMC_CMD_FC_IN_TRC_WRITE_LEN 28\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4\n+#define\tMC_CMD_FC_IN_TRC_WRITE_TRC_LEN 4\n+#define\tMC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8\n+#define\tMC_CMD_FC_IN_TRC_WRITE_CHANNEL_LEN 4\n+#define\tMC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12\n+#define\tMC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4\n+#define\tMC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4\n+\n+/* MC_CMD_FC_IN_GET_VERSION msgrequest */\n+#define\tMC_CMD_FC_IN_GET_VERSION_LEN 4\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+\n+/* MC_CMD_FC_IN_TRC_RX_READ msgrequest */\n+#define\tMC_CMD_FC_IN_TRC_RX_READ_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4\n+#define\tMC_CMD_FC_IN_TRC_RX_READ_TRC_LEN 4\n+#define\tMC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8\n+#define\tMC_CMD_FC_IN_TRC_RX_READ_CHANNEL_LEN 4\n+\n+/* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_TRC_LEN 4\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_LEN 4\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4\n+#define\tMC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2\n+\n+/* MC_CMD_FC_IN_SFP msgrequest */\n+#define\tMC_CMD_FC_IN_SFP_LEN 28\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/* Link speed is 100, 1000, 10000, 40000 */\n+#define\tMC_CMD_FC_IN_SFP_SPEED_OFST 4\n+#define\tMC_CMD_FC_IN_SFP_SPEED_LEN 4\n+/* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */\n+#define\tMC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8\n+#define\tMC_CMD_FC_IN_SFP_COPPER_LEN_LEN 4\n+/* Not relevant for cards with QSFP modules. For older cards, true if module is\n+ * a dual speed SFP+ module.\n+ */\n+#define\tMC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12\n+#define\tMC_CMD_FC_IN_SFP_DUAL_SPEED_LEN 4\n+/* True if an SFP Module is present (other fields valid when true) */\n+#define\tMC_CMD_FC_IN_SFP_PRESENT_OFST 16\n+#define\tMC_CMD_FC_IN_SFP_PRESENT_LEN 4\n+/* The type of the SFP+ Module. For later cards with QSFP modules, this field\n+ * is unused and the type is communicated by other means.\n+ */\n+#define\tMC_CMD_FC_IN_SFP_TYPE_OFST 20\n+#define\tMC_CMD_FC_IN_SFP_TYPE_LEN 4\n+/* Capabilities corresponding to 1 bits. */\n+#define\tMC_CMD_FC_IN_SFP_CAPS_OFST 24\n+#define\tMC_CMD_FC_IN_SFP_CAPS_LEN 4\n+\n+/* MC_CMD_FC_IN_DDR_TEST msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_TEST_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4\n+#define\tMC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4\n+#define\tMC_CMD_FC_IN_DDR_TEST_OP_LBN 0\n+#define\tMC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8\n+/* enum: DRAM Test Start */\n+#define\tMC_CMD_FC_OP_DDR_TEST_START 0x1\n+/* enum: DRAM Test Poll */\n+#define\tMC_CMD_FC_OP_DDR_TEST_POLL 0x2\n+\n+/* MC_CMD_FC_IN_DDR_TEST_START msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1\n+\n+/* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_TEST_POLL_LEN 12\n+#define\tMC_CMD_FC_IN_DDR_TEST_CMD_OFST 0\n+#define\tMC_CMD_FC_IN_DDR_TEST_CMD_LEN 4\n+/*            MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */\n+/* Clear previous test result and prepare for restarting DDR test */\n+#define\tMC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8\n+#define\tMC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_LEN 4\n+\n+/* MC_CMD_FC_IN_GET_ASSERT msgrequest */\n+#define\tMC_CMD_FC_IN_GET_ASSERT_LEN 4\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+\n+/* MC_CMD_FC_IN_FPGA_BUILD msgrequest */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/* FPGA build info operation code */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_OP_LEN 4\n+/* enum: Get the build registers */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1\n+/* enum: Get the services registers */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2\n+/* enum: Get the BSP version */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3\n+/* enum: Get build register for V2 (SFA974X) */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4\n+/* enum: GEt the services register for V2 (SFA974X) */\n+#define\tMC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5\n+\n+/* MC_CMD_FC_IN_READ_MAP msgrequest */\n+#define\tMC_CMD_FC_IN_READ_MAP_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_READ_MAP_HEADER_OFST 4\n+#define\tMC_CMD_FC_IN_READ_MAP_HEADER_LEN 4\n+#define\tMC_CMD_FC_IN_READ_MAP_OP_LBN 0\n+#define\tMC_CMD_FC_IN_READ_MAP_OP_WIDTH 8\n+/* enum: Get the number of map regions */\n+#define\tMC_CMD_FC_OP_READ_MAP_COUNT 0x1\n+/* enum: Get the specified map */\n+#define\tMC_CMD_FC_OP_READ_MAP_INDEX 0x2\n+\n+/* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */\n+#define\tMC_CMD_FC_IN_READ_MAP_COUNT_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */\n+\n+/* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */\n+#define\tMC_CMD_FC_IN_READ_MAP_INDEX_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */\n+#define\tMC_CMD_FC_IN_MAP_INDEX_OFST 8\n+#define\tMC_CMD_FC_IN_MAP_INDEX_LEN 4\n+\n+/* MC_CMD_FC_IN_CAPABILITIES msgrequest */\n+#define\tMC_CMD_FC_IN_CAPABILITIES_LEN 4\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+\n+/* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1\n+\n+/* MC_CMD_FC_IN_IO_REL msgrequest */\n+#define\tMC_CMD_FC_IN_IO_REL_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_IO_REL_HEADER_OFST 4\n+#define\tMC_CMD_FC_IN_IO_REL_HEADER_LEN 4\n+#define\tMC_CMD_FC_IN_IO_REL_OP_LBN 0\n+#define\tMC_CMD_FC_IN_IO_REL_OP_WIDTH 8\n+/* enum: Get the base address that the FC applies to relative commands */\n+#define\tMC_CMD_FC_IN_IO_REL_GET_ADDR 0x1\n+/* enum: Read data */\n+#define\tMC_CMD_FC_IN_IO_REL_READ32 0x2\n+/* enum: Write data */\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32 0x3\n+#define\tMC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8\n+#define\tMC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8\n+/* enum: Application address space */\n+#define\tMC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1\n+/* enum: Flash address space */\n+#define\tMC_CMD_FC_COMP_TYPE_FLASH 0x2\n+\n+/* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */\n+#define\tMC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */\n+\n+/* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_LEN 4\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_LEN 4\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16\n+#define\tMC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_LEN 4\n+\n+/* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num))\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_LEN 4\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_LEN 4\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59\n+\n+/* MC_CMD_FC_IN_UHLINK msgrequest */\n+#define\tMC_CMD_FC_IN_UHLINK_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_UHLINK_HEADER_OFST 4\n+#define\tMC_CMD_FC_IN_UHLINK_HEADER_LEN 4\n+#define\tMC_CMD_FC_IN_UHLINK_OP_LBN 0\n+#define\tMC_CMD_FC_IN_UHLINK_OP_WIDTH 8\n+/* enum: Get PHY configuration info */\n+#define\tMC_CMD_FC_OP_UHLINK_PHY 0x1\n+/* enum: Get MAC configuration info */\n+#define\tMC_CMD_FC_OP_UHLINK_MAC 0x2\n+/* enum: Get Rx eye table */\n+#define\tMC_CMD_FC_OP_UHLINK_RX_EYE 0x3\n+/* enum: Get Rx eye plot */\n+#define\tMC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4\n+/* enum: Get Rx eye plot */\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5\n+/* enum: Retune Rx settings */\n+#define\tMC_CMD_FC_OP_UHLINK_RX_TUNE 0x6\n+/* enum: Set loopback mode on fpga port */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7\n+/* enum: Get loopback mode config state on fpga port */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8\n+#define\tMC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8\n+#define\tMC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8\n+#define\tMC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16\n+#define\tMC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8\n+#define\tMC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24\n+#define\tMC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8\n+/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are\n+ * irrelevant. Port number is derived from pci_fn; passed in FC header.\n+ */\n+#define\tMC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0\n+/* enum: Override default port number. Port number determined by fields\n+ * PORT_TYPE and PORT_IDX.\n+ */\n+#define\tMC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1\n+\n+/* MC_CMD_FC_OP_UHLINK_PHY msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_PHY_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */\n+\n+/* MC_CMD_FC_OP_UHLINK_MAC msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_MAC_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */\n+\n+/* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */\n+#define\tMC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8\n+#define\tMC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_LEN 4\n+#define\tMC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */\n+\n+/* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */\n+\n+/* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_LEN 4\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_LEN 4\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16\n+#define\tMC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_LEN 4\n+#define\tMC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */\n+\n+/* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */\n+\n+/* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_LEN 4\n+#define\tMC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */\n+#define\tMC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */\n+#define\tMC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_LEN 4\n+#define\tMC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */\n+#define\tMC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */\n+\n+/* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */\n+/*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8\n+#define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_LEN 4\n+\n+/* MC_CMD_FC_IN_SET_LINK msgrequest */\n+#define\tMC_CMD_FC_IN_SET_LINK_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */\n+#define\tMC_CMD_FC_IN_SET_LINK_MODE_OFST 4\n+#define\tMC_CMD_FC_IN_SET_LINK_MODE_LEN 4\n+#define\tMC_CMD_FC_IN_SET_LINK_SPEED_OFST 8\n+#define\tMC_CMD_FC_IN_SET_LINK_SPEED_LEN 4\n+#define\tMC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12\n+#define\tMC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4\n+#define\tMC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0\n+#define\tMC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1\n+#define\tMC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1\n+#define\tMC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1\n+#define\tMC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2\n+#define\tMC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1\n+\n+/* MC_CMD_FC_IN_LICENSE msgrequest */\n+#define\tMC_CMD_FC_IN_LICENSE_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_LICENSE_OP_OFST 4\n+#define\tMC_CMD_FC_IN_LICENSE_OP_LEN 4\n+#define\tMC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */\n+#define\tMC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_STARTUP msgrequest */\n+#define\tMC_CMD_FC_IN_STARTUP_LEN 40\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_STARTUP_BASE_OFST 4\n+#define\tMC_CMD_FC_IN_STARTUP_BASE_LEN 4\n+#define\tMC_CMD_FC_IN_STARTUP_LENGTH_OFST 8\n+#define\tMC_CMD_FC_IN_STARTUP_LENGTH_LEN 4\n+/* Length of identifier */\n+#define\tMC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12\n+#define\tMC_CMD_FC_IN_STARTUP_IDLENGTH_LEN 4\n+/* Identifier for AOE FPGA */\n+#define\tMC_CMD_FC_IN_STARTUP_ID_OFST 16\n+#define\tMC_CMD_FC_IN_STARTUP_ID_LEN 1\n+#define\tMC_CMD_FC_IN_STARTUP_ID_NUM 24\n+\n+/* MC_CMD_FC_IN_DMA msgrequest */\n+#define\tMC_CMD_FC_IN_DMA_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DMA_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DMA_OP_LEN 4\n+#define\tMC_CMD_FC_IN_DMA_STOP  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DMA_READ  0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_DMA_STOP msgrequest */\n+#define\tMC_CMD_FC_IN_DMA_STOP_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_DMA_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_DMA_OP_LEN 4 */\n+/* FC supplied handle */\n+#define\tMC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8\n+#define\tMC_CMD_FC_IN_DMA_STOP_FC_HANDLE_LEN 4\n+\n+/* MC_CMD_FC_IN_DMA_READ msgrequest */\n+#define\tMC_CMD_FC_IN_DMA_READ_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_DMA_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_DMA_OP_LEN 4 */\n+#define\tMC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8\n+#define\tMC_CMD_FC_IN_DMA_READ_OFFSET_LEN 4\n+#define\tMC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12\n+#define\tMC_CMD_FC_IN_DMA_READ_LENGTH_LEN 4\n+\n+/* MC_CMD_FC_IN_TIMED_READ msgrequest */\n+#define\tMC_CMD_FC_IN_TIMED_READ_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_TIMED_READ_OP_OFST 4\n+#define\tMC_CMD_FC_IN_TIMED_READ_OP_LEN 4\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_TIMED_READ_GET  0x1 /* enum */\n+#define\tMC_CMD_FC_IN_TIMED_READ_CLEAR  0x2 /* enum */\n+\n+/* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_LEN 52\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */\n+/* Host supplied handle (unique) */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_LEN 4\n+/* Address into which to transfer data in host */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16\n+/* AOE address from which to transfer data */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24\n+/* Length of AOE transfer (total) */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4\n+/* Length of host transfer (total) */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_LEN 4\n+/* Offset back from aoe_address to apply operation to */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_OFFSET_LEN 4\n+/* Data to apply at offset */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_NONE  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_READ  0x1 /* enum */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_WRITE  0x2 /* enum */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_READWRITE  0x3 /* enum */\n+/* Period at which reads are performed (100ms units) */\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4\n+\n+/* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */\n+#define\tMC_CMD_FC_IN_TIMED_READ_GET_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */\n+/* FC supplied handle */\n+#define\tMC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8\n+#define\tMC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_LEN 4\n+\n+/* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */\n+#define\tMC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */\n+/* FC supplied handle */\n+#define\tMC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8\n+#define\tMC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_LEN 4\n+\n+/* MC_CMD_FC_IN_LOG msgrequest */\n+#define\tMC_CMD_FC_IN_LOG_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_LOG_OP_OFST 4\n+#define\tMC_CMD_FC_IN_LOG_OP_LEN 4\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_LOG_JTAG_UART  0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_LOG_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_LOG_OP_LEN 4 */\n+/* Partition offset into flash */\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_LEN 4\n+/* Partition length */\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_LEN 4\n+/* Partition erase size */\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16\n+#define\tMC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_LEN 4\n+\n+/* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */\n+#define\tMC_CMD_FC_IN_LOG_JTAG_UART_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_LOG_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_LOG_OP_LEN 4 */\n+/* Enable/disable printing to JTAG UART */\n+#define\tMC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8\n+#define\tMC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4\n+\n+/* MC_CMD_FC_IN_CLOCK msgrequest */\n+#define\tMC_CMD_FC_IN_CLOCK_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_CLOCK_OP_OFST 4\n+#define\tMC_CMD_FC_IN_CLOCK_OP_LEN 4\n+#define\tMC_CMD_FC_IN_CLOCK_GET_TIME  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME  0x1 /* enum */\n+/* Perform a clock operation */\n+#define\tMC_CMD_FC_IN_CLOCK_ID_OFST 8\n+#define\tMC_CMD_FC_IN_CLOCK_ID_LEN 4\n+#define\tMC_CMD_FC_IN_CLOCK_STATS  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_CLOCK_MAC  0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */\n+#define\tMC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_CLOCK_OP_LEN 4 */\n+/* Retrieve the clock value of the specified clock */\n+/*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */\n+/*            MC_CMD_FC_IN_CLOCK_ID_LEN 4 */\n+\n+/* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_CLOCK_OP_LEN 4 */\n+/*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */\n+/*            MC_CMD_FC_IN_CLOCK_ID_LEN 4 */\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16\n+/* Set the clock value of the specified clock */\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4\n+\n+/* MC_CMD_FC_IN_DDR msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DDR_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DDR_OP_LEN 4\n+#define\tMC_CMD_FC_IN_DDR_SET_SPD  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_GET_STATUS  0x1 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_SET_INFO  0x2 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_BANK_OFST 8\n+#define\tMC_CMD_FC_IN_DDR_BANK_LEN 4\n+#define\tMC_CMD_FC_IN_DDR_BANK_B0  0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_BANK_B1  0x1 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_BANK_T0  0x2 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_BANK_T1  0x3 /* enum */\n+#define\tMC_CMD_FC_IN_DDR_NUM_BANKS  0x4 /* enum */\n+\n+/* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_SET_SPD_LEN 148\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_DDR_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_DDR_OP_LEN 4 */\n+/* Affected bank */\n+/*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */\n+/*            MC_CMD_FC_IN_DDR_BANK_LEN 4 */\n+/* Flags */\n+#define\tMC_CMD_FC_IN_DDR_FLAGS_OFST 12\n+#define\tMC_CMD_FC_IN_DDR_FLAGS_LEN 4\n+#define\tMC_CMD_FC_IN_DDR_SET_SPD_ACTIVE  0x1 /* enum */\n+/* 128-byte page of serial presence detect data read from module's EEPROM */\n+#define\tMC_CMD_FC_IN_DDR_SPD_OFST 16\n+#define\tMC_CMD_FC_IN_DDR_SPD_LEN 1\n+#define\tMC_CMD_FC_IN_DDR_SPD_NUM 128\n+/* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */\n+#define\tMC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144\n+#define\tMC_CMD_FC_IN_DDR_SPD_PAGE_ID_LEN 4\n+\n+/* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_SET_INFO_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_DDR_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_DDR_OP_LEN 4 */\n+/* Affected bank */\n+/*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */\n+/*            MC_CMD_FC_IN_DDR_BANK_LEN 4 */\n+/* Size of DDR */\n+#define\tMC_CMD_FC_IN_DDR_SIZE_OFST 12\n+#define\tMC_CMD_FC_IN_DDR_SIZE_LEN 4\n+\n+/* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */\n+#define\tMC_CMD_FC_IN_DDR_GET_STATUS_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/*            MC_CMD_FC_IN_DDR_OP_OFST 4 */\n+/*            MC_CMD_FC_IN_DDR_OP_LEN 4 */\n+/* Affected bank */\n+/*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */\n+/*            MC_CMD_FC_IN_DDR_BANK_LEN 4 */\n+\n+/* MC_CMD_FC_IN_TIMESTAMP msgrequest */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/* FC timestamp operation code */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_OP_OFST 4\n+#define\tMC_CMD_FC_IN_TIMESTAMP_OP_LEN 4\n+/* enum: Read transmit timestamp(s) */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0\n+/* enum: Read snapshot timestamps */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1\n+/* enum: Clear all transmit timestamps */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2\n+\n+/* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_LEN 4\n+/* Control filtering of the returned timestamp and sequence number specified\n+ * here\n+ */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_LEN 4\n+/* enum: Return most recent timestamp. No filtering */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0\n+/* enum: Match timestamp against the PTP clock ID, port number and sequence\n+ * number specified\n+ */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1\n+/* Clock identity of PTP packet for which timestamp required */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16\n+/* Port number of PTP packet for which timestamp required */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4\n+/* Sequence number of PTP packet for which timestamp required */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_LEN 4\n+\n+/* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_LEN 4\n+\n+/* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4\n+#define\tMC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_LEN 4\n+\n+/* MC_CMD_FC_IN_SPI msgrequest */\n+#define\tMC_CMD_FC_IN_SPI_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/* Basic commands for SPI Flash. */\n+#define\tMC_CMD_FC_IN_SPI_OP_OFST 4\n+#define\tMC_CMD_FC_IN_SPI_OP_LEN 4\n+/* enum: SPI Flash read */\n+#define\tMC_CMD_FC_IN_SPI_READ 0x0\n+/* enum: SPI Flash write */\n+#define\tMC_CMD_FC_IN_SPI_WRITE 0x1\n+/* enum: SPI Flash erase */\n+#define\tMC_CMD_FC_IN_SPI_ERASE 0x2\n+\n+/* MC_CMD_FC_IN_SPI_READ msgrequest */\n+#define\tMC_CMD_FC_IN_SPI_READ_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_SPI_READ_OP_OFST 4\n+#define\tMC_CMD_FC_IN_SPI_READ_OP_LEN 4\n+#define\tMC_CMD_FC_IN_SPI_READ_ADDR_OFST 8\n+#define\tMC_CMD_FC_IN_SPI_READ_ADDR_LEN 4\n+#define\tMC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12\n+#define\tMC_CMD_FC_IN_SPI_READ_NUMBYTES_LEN 4\n+\n+/* MC_CMD_FC_IN_SPI_WRITE msgrequest */\n+#define\tMC_CMD_FC_IN_SPI_WRITE_LENMIN 16\n+#define\tMC_CMD_FC_IN_SPI_WRITE_LENMAX 252\n+#define\tMC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num))\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_SPI_WRITE_OP_OFST 4\n+#define\tMC_CMD_FC_IN_SPI_WRITE_OP_LEN 4\n+#define\tMC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8\n+#define\tMC_CMD_FC_IN_SPI_WRITE_ADDR_LEN 4\n+#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12\n+#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4\n+#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60\n+\n+/* MC_CMD_FC_IN_SPI_ERASE msgrequest */\n+#define\tMC_CMD_FC_IN_SPI_ERASE_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_SPI_ERASE_OP_OFST 4\n+#define\tMC_CMD_FC_IN_SPI_ERASE_OP_LEN 4\n+#define\tMC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8\n+#define\tMC_CMD_FC_IN_SPI_ERASE_ADDR_LEN 4\n+#define\tMC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12\n+#define\tMC_CMD_FC_IN_SPI_ERASE_NUMBYTES_LEN 4\n+\n+/* MC_CMD_FC_IN_DIAG msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_LEN 8\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+/* Operation code indicating component type */\n+#define\tMC_CMD_FC_IN_DIAG_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_OP_LEN 4\n+/* enum: Power noise generator. */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE 0x0\n+/* enum: DDR soak test component. */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK 0x1\n+/* enum: Diagnostics datapath control component. */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2\n+\n+/* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_OP_LEN 4\n+/* Sub-opcode describing the operation to be carried out */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_LEN 4\n+/* enum: Read the configuration (the 32-bit values in each of the clock enable\n+ * count and toggle count registers)\n+ */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0\n+/* enum: Write a new configuration to the clock enable count and toggle count\n+ * registers\n+ */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1\n+\n+/* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_LEN 4\n+\n+/* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_LEN 4\n+/* The 32-bit value to be written to the toggle count register */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_LEN 4\n+/* The 32-bit value to be written to the clock enable count register */\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16\n+#define\tMC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_LEN 4\n+\n+/* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_OP_LEN 4\n+/* Sub-opcode describing the operation to be carried out */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_LEN 4\n+/* enum: Starts DDR soak test on selected banks */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0\n+/* enum: Read status of DDR soak test */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1\n+/* enum: Stop test */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2\n+/* enum: Set or clear bit that triggers fake errors. These cause subsequent\n+ * tests to fail until the bit is cleared.\n+ */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3\n+\n+/* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_LEN 4\n+/* Mask of DDR banks to be tested */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_LEN 4\n+/* Pattern to use in the soak test */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */\n+/* Either multiple automatic tests until a STOP command is issued, or one\n+ * single test\n+ */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_LEN 4\n+/* DDR bank to read status from */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_LEN 4\n+#define\tMC_CMD_FC_DDR_BANK0 0x0 /* enum */\n+#define\tMC_CMD_FC_DDR_BANK1 0x1 /* enum */\n+#define\tMC_CMD_FC_DDR_BANK2 0x2 /* enum */\n+#define\tMC_CMD_FC_DDR_BANK3 0x3 /* enum */\n+#define\tMC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */\n+\n+/* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_LEN 4\n+/* Mask of DDR banks to be tested */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_LEN 4\n+\n+/* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_LEN 4\n+/* Mask of DDR banks to set/clear error flag on */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_LEN 4\n+/* Sub-opcode describing the operation to be carried out */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_LEN 4\n+/* enum: Set a known datapath configuration */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0\n+/* enum: Apply raw config to datapath control registers */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1\n+\n+/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_LEN 4\n+/* Datapath configuration identifier */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */\n+\n+/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24\n+/*            MC_CMD_FC_IN_CMD_OFST 0 */\n+/*            MC_CMD_FC_IN_CMD_LEN 4 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_LEN 4\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_LEN 4\n+/* Value to write into control register 1 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_LEN 4\n+/* Value to write into control register 2 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_LEN 4\n+/* Value to write into control register 3 */\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20\n+#define\tMC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_LEN 4\n+\n+/* MC_CMD_FC_OUT msgresponse */\n+#define\tMC_CMD_FC_OUT_LEN 0\n+\n+/* MC_CMD_FC_OUT_NULL msgresponse */\n+#define\tMC_CMD_FC_OUT_NULL_LEN 0\n+\n+/* MC_CMD_FC_OUT_READ32 msgresponse */\n+#define\tMC_CMD_FC_OUT_READ32_LENMIN 4\n+#define\tMC_CMD_FC_OUT_READ32_LENMAX 252\n+#define\tMC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num))\n+#define\tMC_CMD_FC_OUT_READ32_BUFFER_OFST 0\n+#define\tMC_CMD_FC_OUT_READ32_BUFFER_LEN 4\n+#define\tMC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63\n+\n+/* MC_CMD_FC_OUT_WRITE32 msgresponse */\n+#define\tMC_CMD_FC_OUT_WRITE32_LEN 0\n+\n+/* MC_CMD_FC_OUT_TRC_READ msgresponse */\n+#define\tMC_CMD_FC_OUT_TRC_READ_LEN 16\n+#define\tMC_CMD_FC_OUT_TRC_READ_DATA_OFST 0\n+#define\tMC_CMD_FC_OUT_TRC_READ_DATA_LEN 4\n+#define\tMC_CMD_FC_OUT_TRC_READ_DATA_NUM 4\n+\n+/* MC_CMD_FC_OUT_TRC_WRITE msgresponse */\n+#define\tMC_CMD_FC_OUT_TRC_WRITE_LEN 0\n+\n+/* MC_CMD_FC_OUT_GET_VERSION msgresponse */\n+#define\tMC_CMD_FC_OUT_GET_VERSION_LEN 12\n+#define\tMC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0\n+#define\tMC_CMD_FC_OUT_GET_VERSION_FIRMWARE_LEN 4\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8\n+\n+/* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */\n+#define\tMC_CMD_FC_OUT_TRC_RX_READ_LEN 8\n+#define\tMC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0\n+#define\tMC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4\n+#define\tMC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2\n+\n+/* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */\n+#define\tMC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0\n+\n+/* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0\n+\n+/* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_SET_LINK_LEN 0\n+\n+/* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4\n+#define\tMC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_LEN 4\n+\n+/* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3)\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS\n+#define\tMC_CMD_FC_MAC_RX_STATS_OCTETS  0x0 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_OCTETS_OK  0x1 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS  0x2 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES  0x3 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_FRAMES_OK  0x4 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_CRC_ERRORS  0x5 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_VLAN_OK  0x6 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_ERRORS  0x7 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_UCAST_PKTS  0x8 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_MULTICAST_PKTS  0x9 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_BROADCAST_PKTS  0xa /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_DROP_EVENTS  0xb /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS  0xc /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS  0xd /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_64  0xe /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_65_127  0xf /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_128_255  0x10 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_256_511  0x11 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_512_1023  0x12 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518  0x13 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX  0x14 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS  0x15 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_JABBERS  0x16 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_STATS_FRAGMENTS  0x17 /* enum */\n+#define\tMC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES  0x18 /* enum */\n+/* enum: (Last entry) */\n+#define\tMC_CMD_FC_MAC_RX_NSTATS  0x19\n+\n+/* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3)\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS\n+#define\tMC_CMD_FC_MAC_TX_STATS_OCTETS  0x0 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_OCTETS_OK  0x1 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS  0x2 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES  0x3 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_FRAMES_OK  0x4 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_CRC_ERRORS  0x5 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_VLAN_OK  0x6 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_ERRORS  0x7 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_UCAST_PKTS  0x8 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_MULTICAST_PKTS  0x9 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_BROADCAST_PKTS  0xa /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_DROP_EVENTS  0xb /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS  0xc /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS  0xd /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_64  0xe /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_65_127  0xf /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_128_255  0x10 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_256_511  0x11 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_512_1023  0x12 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518  0x13 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU  0x14 /* enum */\n+#define\tMC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES  0x15 /* enum */\n+/* enum: (Last entry) */\n+#define\tMC_CMD_FC_MAC_TX_NSTATS  0x16\n+\n+/* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3)\n+/* MAC Statistics */\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK\n+\n+/* MC_CMD_FC_OUT_MAC msgresponse */\n+#define\tMC_CMD_FC_OUT_MAC_LEN 0\n+\n+/* MC_CMD_FC_OUT_SFP msgresponse */\n+#define\tMC_CMD_FC_OUT_SFP_LEN 0\n+\n+/* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_START_LEN 0\n+\n+/* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8\n+/* enum: Test not yet initiated */\n+#define\tMC_CMD_FC_OP_DDR_TEST_NONE 0x0\n+/* enum: Test is in progress */\n+#define\tMC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1\n+/* enum: Timed completed */\n+#define\tMC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2\n+/* enum: Test did not complete in specified time */\n+#define\tMC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1\n+/* Test result from FPGA */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */\n+\n+/* MC_CMD_FC_OUT_DDR_TEST msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_TEST_LEN 0\n+\n+/* MC_CMD_FC_OUT_GET_ASSERT msgresponse */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_LEN 144\n+/* Assertion status flag. */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8\n+/* enum: No crash data available */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0\n+/* enum: New crash data available */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1\n+/* enum: Crash data has been sent */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8\n+/* enum: No crash has been recorded. */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0\n+/* enum: Crash due to exception. */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1\n+/* enum: Crash due to assertion. */\n+#define\tMC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2\n+/* Failing PC value */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_LEN 4\n+/* Saved GP regs */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31\n+/* Exception Type */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_LEN 4\n+/* Instruction at which exception occurred */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_LEN 4\n+/* BAD Address that triggered address-based exception */\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_LEN 4\n+\n+/* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_LEN 32\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4\n+/* Build timestamp (seconds since epoch) */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8\n+#define\tMC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */\n+#define\tMC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1\n+#define\tMC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */\n+#define\tMC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16\n+\n+/* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4\n+/* Build timestamp (seconds since epoch) */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */\n+#define\tMC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1\n+/*               MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */\n+/*               MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16\n+\n+/* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_LEN 32\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4\n+/* Build timestamp (seconds since epoch) */\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16\n+\n+/* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4\n+/* Build timestamp (seconds since epoch) */\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1\n+/*               MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */\n+/*               MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16\n+\n+/* MC_CMD_FC_OUT_BSP_VERSION msgresponse */\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_LEN 4\n+/* Qsys system ID */\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4\n+\n+/* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */\n+#define\tMC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4\n+/* Number of maps */\n+#define\tMC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0\n+#define\tMC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_LEN 4\n+\n+/* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164\n+/* Index of the map */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_LEN 4\n+/* Options for the map */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8  0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16  0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32  0x2 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64  0x3 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK  0x3 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC  0x4 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM  0x8 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ  0x10 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE  0x20 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE  0x0 /* enum */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED  0x40 /* enum */\n+/* Address of start of map */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12\n+/* Length of address map */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20\n+/* Component information field */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4\n+/* License expiry data for map */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32\n+/* Name of the component */\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128\n+\n+/* MC_CMD_FC_OUT_READ_MAP msgresponse */\n+#define\tMC_CMD_FC_OUT_READ_MAP_LEN 0\n+\n+/* MC_CMD_FC_OUT_CAPABILITIES msgresponse */\n+#define\tMC_CMD_FC_OUT_CAPABILITIES_LEN 8\n+/* Number of internal ports */\n+#define\tMC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0\n+#define\tMC_CMD_FC_OUT_CAPABILITIES_INTERNAL_LEN 4\n+/* Number of external ports */\n+#define\tMC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4\n+#define\tMC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_LEN 4\n+\n+/* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */\n+#define\tMC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4\n+#define\tMC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0\n+#define\tMC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_LEN 4\n+\n+/* MC_CMD_FC_OUT_IO_REL msgresponse */\n+#define\tMC_CMD_FC_OUT_IO_REL_LEN 0\n+\n+/* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */\n+#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8\n+#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0\n+#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_LEN 4\n+\n+/* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num))\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63\n+\n+/* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */\n+#define\tMC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0\n+\n+/* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LEN 48\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16\n+/* Transceiver Transmit settings */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16\n+/* Transceiver Receive settings */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16\n+/* Rx eye opening */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16\n+/* PCS status word */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_LEN 4\n+/* Link status word */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1\n+/* Current SFp parameters applied */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20\n+/* Link speed is 100, 1000, 10000 */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_LEN 4\n+/* Length of copper cable - zero when not relevant */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_LEN 4\n+/* True if a dual speed SFP+ module */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_LEN 4\n+/* True if an SFP Module is present (other fields valid when true) */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_LEN 4\n+/* The type of the SFP+ Module */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_LEN 4\n+/* PHY config flags */\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1\n+\n+/* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_LEN 20\n+/* MAC configuration applied */\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_CONFIG_LEN 4\n+/* MTU size */\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_MTU_LEN 4\n+/* IF Mode status */\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_LEN 4\n+/* MAC address configured */\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16\n+\n+/* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)\n+/* Rx Eye measurements */\n+#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0\n+#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK\n+\n+/* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0\n+\n+/* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3)\n+/* Has the eye plot dump completed and data returned is valid? */\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_LEN 4\n+/* Rx Eye binary plot */\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK\n+\n+/* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0\n+\n+/* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0\n+\n+/* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0\n+#define\tMC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_LEN 4\n+\n+/* MC_CMD_FC_OUT_UHLINK msgresponse */\n+#define\tMC_CMD_FC_OUT_UHLINK_LEN 0\n+\n+/* MC_CMD_FC_OUT_SET_LINK msgresponse */\n+#define\tMC_CMD_FC_OUT_SET_LINK_LEN 0\n+\n+/* MC_CMD_FC_OUT_LICENSE msgresponse */\n+#define\tMC_CMD_FC_OUT_LICENSE_LEN 12\n+/* Count of valid keys */\n+#define\tMC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0\n+#define\tMC_CMD_FC_OUT_LICENSE_VALID_KEYS_LEN 4\n+/* Count of invalid keys */\n+#define\tMC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4\n+#define\tMC_CMD_FC_OUT_LICENSE_INVALID_KEYS_LEN 4\n+/* Count of blacklisted keys */\n+#define\tMC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8\n+#define\tMC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_LEN 4\n+\n+/* MC_CMD_FC_OUT_STARTUP msgresponse */\n+#define\tMC_CMD_FC_OUT_STARTUP_LEN 4\n+/* Capabilities of the FPGA/FC */\n+#define\tMC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0\n+#define\tMC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4\n+#define\tMC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0\n+#define\tMC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1\n+\n+/* MC_CMD_FC_OUT_DMA_READ msgresponse */\n+#define\tMC_CMD_FC_OUT_DMA_READ_LENMIN 1\n+#define\tMC_CMD_FC_OUT_DMA_READ_LENMAX 252\n+#define\tMC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num))\n+/* The data read */\n+#define\tMC_CMD_FC_OUT_DMA_READ_DATA_OFST 0\n+#define\tMC_CMD_FC_OUT_DMA_READ_DATA_LEN 1\n+#define\tMC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1\n+#define\tMC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252\n+\n+/* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_SET_LEN 4\n+/* Timer handle */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_LEN 4\n+\n+/* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_LEN 52\n+/* Host supplied handle (unique) */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_LEN 4\n+/* Address into which to transfer data in host */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8\n+/* AOE address from which to transfer data */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16\n+/* Length of AOE transfer (total) */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4\n+/* Length of host transfer (total) */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_LEN 4\n+/* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_LEN 4\n+/* When active, start read time */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40\n+/* When active, end read time */\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48\n+\n+/* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */\n+#define\tMC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0\n+\n+/* MC_CMD_FC_OUT_LOG msgresponse */\n+#define\tMC_CMD_FC_OUT_LOG_LEN 0\n+\n+/* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_LEN 4\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_LEN 4\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_LEN 4\n+\n+/* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */\n+#define\tMC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0\n+\n+/* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_SET_SPD_LEN 0\n+\n+/* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_SET_INFO_LEN 0\n+\n+/* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1\n+\n+/* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_LEN 4\n+\n+/* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num))\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31\n+\n+/* MC_CMD_FC_OUT_SPI_READ msgresponse */\n+#define\tMC_CMD_FC_OUT_SPI_READ_LENMIN 4\n+#define\tMC_CMD_FC_OUT_SPI_READ_LENMAX 252\n+#define\tMC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num))\n+#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0\n+#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4\n+#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1\n+#define\tMC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63\n+\n+/* MC_CMD_FC_OUT_SPI_WRITE msgresponse */\n+#define\tMC_CMD_FC_OUT_SPI_WRITE_LEN 0\n+\n+/* MC_CMD_FC_OUT_SPI_ERASE msgresponse */\n+#define\tMC_CMD_FC_OUT_SPI_ERASE_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8\n+/* The 32-bit value read from the toggle count register */\n+#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0\n+#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_LEN 4\n+/* The 32-bit value read from the clock enable count register */\n+#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4\n+#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_LEN 4\n+\n+/* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8\n+/* DDR soak test status word; bits [4:0] are relevant. */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1\n+/* DDR soak test error count */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_LEN 4\n+\n+/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0\n+\n+/* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */\n+#define\tMC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_AOE\n+ * AOE operations on MC\n+ */\n+#define\tMC_CMD_AOE 0xa\n+\n+/* MC_CMD_AOE_IN msgrequest */\n+#define\tMC_CMD_AOE_IN_LEN 4\n+#define\tMC_CMD_AOE_IN_OP_HDR_OFST 0\n+#define\tMC_CMD_AOE_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_AOE_IN_OP_LBN 0\n+#define\tMC_CMD_AOE_IN_OP_WIDTH 8\n+/* enum: FPGA and CPLD information */\n+#define\tMC_CMD_AOE_OP_INFO 0x1\n+/* enum: Currents and voltages read from MCP3424s; DEBUG */\n+#define\tMC_CMD_AOE_OP_CURRENTS 0x2\n+/* enum: Temperatures at locations around the PCB; DEBUG */\n+#define\tMC_CMD_AOE_OP_TEMPERATURES 0x3\n+/* enum: Set CPLD to idle */\n+#define\tMC_CMD_AOE_OP_CPLD_IDLE 0x4\n+/* enum: Read from CPLD register */\n+#define\tMC_CMD_AOE_OP_CPLD_READ 0x5\n+/* enum: Write to CPLD register */\n+#define\tMC_CMD_AOE_OP_CPLD_WRITE 0x6\n+/* enum: Execute CPLD instruction */\n+#define\tMC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7\n+/* enum: Reprogram the CPLD on the AOE device */\n+#define\tMC_CMD_AOE_OP_CPLD_REPROGRAM 0x8\n+/* enum: AOE power control */\n+#define\tMC_CMD_AOE_OP_POWER 0x9\n+/* enum: AOE image loading */\n+#define\tMC_CMD_AOE_OP_LOAD 0xa\n+/* enum: Fan monitoring */\n+#define\tMC_CMD_AOE_OP_FAN_CONTROL 0xb\n+/* enum: Fan failures since last reset */\n+#define\tMC_CMD_AOE_OP_FAN_FAILURES 0xc\n+/* enum: Get generic AOE MAC statistics */\n+#define\tMC_CMD_AOE_OP_MAC_STATS 0xd\n+/* enum: Retrieve PHY specific information */\n+#define\tMC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe\n+/* enum: Write a number of JTAG primitive commands, return will give data */\n+#define\tMC_CMD_AOE_OP_JTAG_WRITE 0xf\n+/* enum: Control access to the FPGA via the Siena JTAG Chain */\n+#define\tMC_CMD_AOE_OP_FPGA_ACCESS 0x10\n+/* enum: Set the MTU offset between Siena and AOE MACs */\n+#define\tMC_CMD_AOE_OP_SET_MTU_OFFSET 0x11\n+/* enum: How link state is handled */\n+#define\tMC_CMD_AOE_OP_LINK_STATE 0x12\n+/* enum: How Siena MAC statistics are reported (deprecated - use\n+ * MC_CMD_AOE_OP_ASIC_STATS)\n+ */\n+#define\tMC_CMD_AOE_OP_SIENA_STATS 0x13\n+/* enum: How native ASIC MAC statistics are reported - replaces the deprecated\n+ * command MC_CMD_AOE_OP_SIENA_STATS\n+ */\n+#define\tMC_CMD_AOE_OP_ASIC_STATS 0x13\n+/* enum: DDR memory information */\n+#define\tMC_CMD_AOE_OP_DDR 0x14\n+/* enum: FC control */\n+#define\tMC_CMD_AOE_OP_FC 0x15\n+/* enum: DDR ECC status reads */\n+#define\tMC_CMD_AOE_OP_DDR_ECC_STATUS 0x16\n+/* enum: Commands for MC-SPI Master emulation */\n+#define\tMC_CMD_AOE_OP_MC_SPI_MASTER 0x17\n+/* enum: Commands for FC boot control */\n+#define\tMC_CMD_AOE_OP_FC_BOOT 0x18\n+/* enum: Get number of internal ports */\n+#define\tMC_CMD_AOE_OP_GET_ASIC_PORTS 0x19\n+/* enum: Get FC assert information and register dump */\n+#define\tMC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a\n+\n+/* MC_CMD_AOE_OUT msgresponse */\n+#define\tMC_CMD_AOE_OUT_LEN 0\n+\n+/* MC_CMD_AOE_IN_INFO msgrequest */\n+#define\tMC_CMD_AOE_IN_INFO_LEN 4\n+#define\tMC_CMD_AOE_IN_CMD_OFST 0\n+#define\tMC_CMD_AOE_IN_CMD_LEN 4\n+\n+/* MC_CMD_AOE_IN_CURRENTS msgrequest */\n+#define\tMC_CMD_AOE_IN_CURRENTS_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+\n+/* MC_CMD_AOE_IN_TEMPERATURES msgrequest */\n+#define\tMC_CMD_AOE_IN_TEMPERATURES_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+\n+/* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */\n+#define\tMC_CMD_AOE_IN_CPLD_IDLE_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+\n+/* MC_CMD_AOE_IN_CPLD_READ msgrequest */\n+#define\tMC_CMD_AOE_IN_CPLD_READ_LEN 12\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+#define\tMC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4\n+#define\tMC_CMD_AOE_IN_CPLD_READ_REGISTER_LEN 4\n+#define\tMC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8\n+#define\tMC_CMD_AOE_IN_CPLD_READ_WIDTH_LEN 4\n+\n+/* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_LEN 16\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_REGISTER_LEN 4\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_WIDTH_LEN 4\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12\n+#define\tMC_CMD_AOE_IN_CPLD_WRITE_VALUE_LEN 4\n+\n+/* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */\n+#define\tMC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+#define\tMC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4\n+#define\tMC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_LEN 4\n+\n+/* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_OP_LEN 4\n+/* enum: Reprogram CPLD, poll for completion */\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1\n+/* enum: Reprogram CPLD, send event on completion */\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3\n+/* enum: Get status of reprogramming operation */\n+#define\tMC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4\n+\n+/* MC_CMD_AOE_IN_POWER msgrequest */\n+#define\tMC_CMD_AOE_IN_POWER_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* Turn on or off AOE power */\n+#define\tMC_CMD_AOE_IN_POWER_OP_OFST 4\n+#define\tMC_CMD_AOE_IN_POWER_OP_LEN 4\n+/* enum: Turn off FPGA power */\n+#define\tMC_CMD_AOE_IN_POWER_OFF  0x0\n+/* enum: Turn on FPGA power */\n+#define\tMC_CMD_AOE_IN_POWER_ON  0x1\n+/* enum: Clear peak power measurement */\n+#define\tMC_CMD_AOE_IN_POWER_CLEAR  0x2\n+/* enum: Show current power in sensors output */\n+#define\tMC_CMD_AOE_IN_POWER_SHOW_CURRENT  0x3\n+/* enum: Show peak power in sensors output */\n+#define\tMC_CMD_AOE_IN_POWER_SHOW_PEAK  0x4\n+/* enum: Show current DDR current */\n+#define\tMC_CMD_AOE_IN_POWER_DDR_LAST  0x5\n+/* enum: Show peak DDR current */\n+#define\tMC_CMD_AOE_IN_POWER_DDR_PEAK  0x6\n+/* enum: Clear peak DDR current */\n+#define\tMC_CMD_AOE_IN_POWER_DDR_CLEAR  0x7\n+\n+/* MC_CMD_AOE_IN_LOAD msgrequest */\n+#define\tMC_CMD_AOE_IN_LOAD_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence\n+ */\n+#define\tMC_CMD_AOE_IN_LOAD_IMAGE_OFST 4\n+#define\tMC_CMD_AOE_IN_LOAD_IMAGE_LEN 4\n+\n+/* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */\n+#define\tMC_CMD_AOE_IN_FAN_CONTROL_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* If non zero report measured fan RPM rather than nominal */\n+#define\tMC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4\n+#define\tMC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_LEN 4\n+\n+/* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */\n+#define\tMC_CMD_AOE_IN_FAN_FAILURES_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+\n+/* MC_CMD_AOE_IN_MAC_STATS msgrequest */\n+#define\tMC_CMD_AOE_IN_MAC_STATS_LEN 24\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* AOE port */\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PORT_LEN 4\n+/* Host memory address for statistics */\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12\n+#define\tMC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16\n+#define\tMC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16\n+/* Length of DMA data (optional) */\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_LEN_LEN 4\n+\n+/* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */\n+#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* AOE port */\n+#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4\n+#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_LEN 4\n+#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8\n+#define\tMC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_LEN 4\n+\n+/* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num))\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATALEN_LEN 4\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1\n+#define\tMC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61\n+\n+/* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */\n+#define\tMC_CMD_AOE_IN_FPGA_ACCESS_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* Enable or disable access */\n+#define\tMC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4\n+#define\tMC_CMD_AOE_IN_FPGA_ACCESS_OP_LEN 4\n+/* enum: Enable access */\n+#define\tMC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1\n+/* enum: Disable access */\n+#define\tMC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2\n+\n+/* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_LEN 4\n+/* enum: Apply to all external ports */\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000\n+/* enum: Apply to all internal ports */\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000\n+/* The MTU offset to be applied to the external ports */\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8\n+#define\tMC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_LEN 4\n+\n+/* MC_CMD_AOE_IN_LINK_STATE msgrequest */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4\n+#define\tMC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4\n+#define\tMC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0\n+#define\tMC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8\n+/* enum: AOE and associated external port */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE  0x0\n+/* enum: AOE and OR of all external ports */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED  0x1\n+/* enum: Individual ports */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC  0x2\n+/* enum: Configure link state mode on given AOE port */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_CUSTOM  0x3\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8\n+/* enum: No-op */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OP_NONE  0x0\n+/* enum: logical OR of all SFP ports link status */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OP_OR  0x1\n+/* enum: logical AND of all SFP ports link status */\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OP_AND  0x2\n+#define\tMC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16\n+#define\tMC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16\n+\n+/* MC_CMD_AOE_IN_GET_ASIC_PORTS msgrequest */\n+#define\tMC_CMD_AOE_IN_GET_ASIC_PORTS_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+\n+/* MC_CMD_AOE_IN_GET_FC_ASSERT_INFO msgrequest */\n+#define\tMC_CMD_AOE_IN_GET_FC_ASSERT_INFO_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+\n+/* MC_CMD_AOE_IN_SIENA_STATS msgrequest */\n+#define\tMC_CMD_AOE_IN_SIENA_STATS_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* How MAC statistics are reported */\n+#define\tMC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4\n+#define\tMC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4\n+/* enum: Statistics from Siena (default) */\n+#define\tMC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA  0x0\n+/* enum: Statistics from AOE external ports */\n+#define\tMC_CMD_AOE_IN_SIENA_STATS_STATS_AOE  0x1\n+\n+/* MC_CMD_AOE_IN_ASIC_STATS msgrequest */\n+#define\tMC_CMD_AOE_IN_ASIC_STATS_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* How MAC statistics are reported */\n+#define\tMC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4\n+#define\tMC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4\n+/* enum: Statistics from the ASIC (default) */\n+#define\tMC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC  0x0\n+/* enum: Statistics from AOE external ports */\n+#define\tMC_CMD_AOE_IN_ASIC_STATS_STATS_AOE  0x1\n+\n+/* MC_CMD_AOE_IN_DDR msgrequest */\n+#define\tMC_CMD_AOE_IN_DDR_LEN 12\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+#define\tMC_CMD_AOE_IN_DDR_BANK_OFST 4\n+#define\tMC_CMD_AOE_IN_DDR_BANK_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */\n+/* Page index of SPD data */\n+#define\tMC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8\n+#define\tMC_CMD_AOE_IN_DDR_SPD_PAGE_ID_LEN 4\n+\n+/* MC_CMD_AOE_IN_FC msgrequest */\n+#define\tMC_CMD_AOE_IN_FC_LEN 4\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+\n+/* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */\n+#define\tMC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+#define\tMC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4\n+#define\tMC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */\n+\n+/* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* Basic commands for MC SPI Master emulation. */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_OP_LEN 4\n+/* enum: MC SPI read */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0\n+/* enum: MC SPI write */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1\n+\n+/* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_LEN 4\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_LEN 4\n+\n+/* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_LEN 4\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_LEN 4\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12\n+#define\tMC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_LEN 4\n+\n+/* MC_CMD_AOE_IN_FC_BOOT msgrequest */\n+#define\tMC_CMD_AOE_IN_FC_BOOT_LEN 8\n+/*            MC_CMD_AOE_IN_CMD_OFST 0 */\n+/*            MC_CMD_AOE_IN_CMD_LEN 4 */\n+/* FC boot control flags */\n+#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4\n+#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4\n+#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0\n+#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1\n+\n+/* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144\n+/* Assertion status flag. */\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8\n+/* enum: No crash data available */\n+/*               MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 */\n+/* enum: New crash data available */\n+/*               MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */\n+/* enum: Crash data has been sent */\n+/*               MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8\n+/* enum: No crash has been recorded. */\n+/*               MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 */\n+/* enum: Crash due to exception. */\n+/*               MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 */\n+/* enum: Crash due to assertion. */\n+/*               MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 */\n+/* Failing PC value */\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_OFST 4\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_LEN 4\n+/* Saved GP regs */\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_OFST 8\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_LEN 4\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_NUM 31\n+/* Exception Type */\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_OFST 132\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_LEN 4\n+/* Instruction at which exception occurred */\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_OFST 136\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_LEN 4\n+/* BAD Address that triggered address-based exception */\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_OFST 140\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_LEN 4\n+\n+/* MC_CMD_AOE_OUT_INFO msgresponse */\n+#define\tMC_CMD_AOE_OUT_INFO_LEN 44\n+/* JTAG IDCODE of CPLD */\n+#define\tMC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0\n+#define\tMC_CMD_AOE_OUT_INFO_CPLD_IDCODE_LEN 4\n+/* Version of CPLD */\n+#define\tMC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4\n+#define\tMC_CMD_AOE_OUT_INFO_CPLD_VERSION_LEN 4\n+/* JTAG IDCODE of FPGA */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_IDCODE_LEN 4\n+/* JTAG USERCODE of FPGA */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_VERSION_LEN 4\n+/* FPGA type - read from CPLD straps */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2   0x1 /* enum */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2   0x2 /* enum */\n+/* FPGA state (debug) */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4\n+/* FPGA image - partition from which loaded */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_IMAGE_LEN 4\n+/* FC state */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28\n+#define\tMC_CMD_AOE_OUT_INFO_FC_STATE_LEN 4\n+/* enum: Set if watchdog working */\n+#define\tMC_CMD_AOE_OUT_INFO_WATCHDOG 0x1\n+/* enum: Set if MC-FC communications working */\n+#define\tMC_CMD_AOE_OUT_INFO_COMMS 0x2\n+/* Random pieces of information */\n+#define\tMC_CMD_AOE_OUT_INFO_FLAGS_OFST 32\n+#define\tMC_CMD_AOE_OUT_INFO_FLAGS_LEN 4\n+/* enum: Power to FPGA supplied by PEG connector, not PCIe bus */\n+#define\tMC_CMD_AOE_OUT_INFO_PEG_POWER            0x1\n+/* enum: CPLD apparently good */\n+#define\tMC_CMD_AOE_OUT_INFO_CPLD_GOOD            0x2\n+/* enum: FPGA working normally */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_GOOD            0x4\n+/* enum: FPGA is powered */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_POWER           0x8\n+/* enum: Board has incompatible SODIMMs fitted */\n+#define\tMC_CMD_AOE_OUT_INFO_BAD_SODIMM           0x10\n+/* enum: Board has ByteBlaster connected */\n+#define\tMC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER      0x20\n+/* enum: FPGA Boot flash has an invalid header. */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR    0x40\n+/* enum: FPGA Application flash is accessible. */\n+#define\tMC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD  0x80\n+/* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */\n+#define\tMC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36\n+#define\tMC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4\n+#define\tMC_CMD_AOE_OUT_INFO_UNKNOWN  0x0 /* enum */\n+#define\tMC_CMD_AOE_OUT_INFO_R1_0  0x10 /* enum */\n+#define\tMC_CMD_AOE_OUT_INFO_R1_1  0x11 /* enum */\n+#define\tMC_CMD_AOE_OUT_INFO_R1_2  0x12 /* enum */\n+#define\tMC_CMD_AOE_OUT_INFO_R1_3  0x13 /* enum */\n+/* Result of FC booting - not valid while a ByteBlaster is connected. */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4\n+/* enum: No error */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0\n+/* enum: Bad address set in CPLD */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1\n+/* enum: Bad header */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2\n+/* enum: Bad text section details */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3\n+/* enum: Bad checksum */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4\n+/* enum: Bad BSP */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5\n+/* enum: Flash mode is invalid */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6\n+/* enum: FC application loaded and execution attempted */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80\n+/* enum: FC application Started */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81\n+/* enum: No bootrom in FPGA */\n+#define\tMC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff\n+\n+/* MC_CMD_AOE_OUT_CURRENTS msgresponse */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_LEN 68\n+/* Set of currents and voltages (mA or mV as appropriate) */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0\n+#define\tMC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4\n+#define\tMC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */\n+#define\tMC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */\n+\n+/* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_LEN 40\n+/* Set of temperatures */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10\n+/* enum: The first set of enum values are for Modena code. */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */\n+/* enum: The second set of enum values are for Sorrento code. */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */\n+#define\tMC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */\n+\n+/* MC_CMD_AOE_OUT_CPLD_READ msgresponse */\n+#define\tMC_CMD_AOE_OUT_CPLD_READ_LEN 4\n+/* The value read from the CPLD */\n+#define\tMC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0\n+#define\tMC_CMD_AOE_OUT_CPLD_READ_VALUE_LEN 4\n+\n+/* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num))\n+/* Failure counts for each fan */\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1\n+#define\tMC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63\n+\n+/* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */\n+#define\tMC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4\n+/* Results of status command (only) */\n+#define\tMC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0\n+#define\tMC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_LEN 4\n+\n+/* MC_CMD_AOE_OUT_POWER_OFF msgresponse */\n+#define\tMC_CMD_AOE_OUT_POWER_OFF_LEN 0\n+\n+/* MC_CMD_AOE_OUT_POWER_ON msgresponse */\n+#define\tMC_CMD_AOE_OUT_POWER_ON_LEN 0\n+\n+/* MC_CMD_AOE_OUT_LOAD msgresponse */\n+#define\tMC_CMD_AOE_OUT_LOAD_LEN 0\n+\n+/* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0\n+\n+/* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA\n+ * for details\n+ */\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS\n+\n+/* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num))\n+/* in bytes */\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1\n+#define\tMC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248\n+\n+/* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num))\n+/* Used to align the in and out data blocks so the MC can re-use the cmd */\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4\n+/* out bytes */\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_PAD_LEN 4\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1\n+#define\tMC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61\n+\n+/* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */\n+#define\tMC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0\n+\n+/* MC_CMD_AOE_OUT_DDR msgresponse */\n+#define\tMC_CMD_AOE_OUT_DDR_LENMIN 17\n+#define\tMC_CMD_AOE_OUT_DDR_LENMAX 252\n+#define\tMC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num))\n+/* Information on the module. */\n+#define\tMC_CMD_AOE_OUT_DDR_FLAGS_OFST 0\n+#define\tMC_CMD_AOE_OUT_DDR_FLAGS_LEN 4\n+#define\tMC_CMD_AOE_OUT_DDR_PRESENT_LBN 0\n+#define\tMC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_POWERED_LBN 1\n+#define\tMC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2\n+#define\tMC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3\n+#define\tMC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1\n+/* Memory size, in MB. */\n+#define\tMC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4\n+#define\tMC_CMD_AOE_OUT_DDR_CAPACITY_LEN 4\n+/* The memory type, as reported from SPD information */\n+#define\tMC_CMD_AOE_OUT_DDR_TYPE_OFST 8\n+#define\tMC_CMD_AOE_OUT_DDR_TYPE_LEN 4\n+/* Nominal voltage of the module (as applied) */\n+#define\tMC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12\n+#define\tMC_CMD_AOE_OUT_DDR_VOLTAGE_LEN 4\n+/* SPD data read from the module */\n+#define\tMC_CMD_AOE_OUT_DDR_SPD_OFST 16\n+#define\tMC_CMD_AOE_OUT_DDR_SPD_LEN 1\n+#define\tMC_CMD_AOE_OUT_DDR_SPD_MINNUM 1\n+#define\tMC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236\n+\n+/* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */\n+#define\tMC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0\n+\n+/* MC_CMD_AOE_OUT_LINK_STATE msgresponse */\n+#define\tMC_CMD_AOE_OUT_LINK_STATE_LEN 0\n+\n+/* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */\n+#define\tMC_CMD_AOE_OUT_SIENA_STATS_LEN 0\n+\n+/* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */\n+#define\tMC_CMD_AOE_OUT_ASIC_STATS_LEN 0\n+\n+/* MC_CMD_AOE_OUT_FC msgresponse */\n+#define\tMC_CMD_AOE_OUT_FC_LEN 0\n+\n+/* MC_CMD_AOE_OUT_GET_ASIC_PORTS msgresponse */\n+#define\tMC_CMD_AOE_OUT_GET_ASIC_PORTS_LEN 4\n+/* get the number of internal ports */\n+#define\tMC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_OFST 0\n+#define\tMC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_LEN 4\n+\n+/* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8\n+/* Flags describing status info on the module. */\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1\n+/* DDR ECC status on the module. */\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8\n+\n+/* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */\n+#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4\n+#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0\n+#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_LEN 4\n+\n+/* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */\n+#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0\n+\n+/* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */\n+#define\tMC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0\n+\n+/* MC_CMD_AOE_OUT_FC_BOOT msgresponse */\n+#define\tMC_CMD_AOE_OUT_FC_BOOT_LEN 0\n+\n+#endif /* _SIENA_MC_DRIVER_PCOL_AOE_H */\n+/*! \\cidoxg_end */\n",
    "prefixes": [
        "dpdk-dev",
        "03/80"
    ]
}