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GET /api/patches/35285/?format=api
{ "id": 35285, "url": "http://patches.dpdk.org/api/patches/35285/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-53-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1519112078-20113-53-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1519112078-20113-53-git-send-email-arybchenko@solarflare.com", "date": "2018-02-20T07:34:10", "name": "[dpdk-dev,52/80] net/sfc/base: move PHY/link config to ef10 NIC board cfg", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "de0a288f02fef61e76be3916b669441bd93c96cb", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-53-git-send-email-arybchenko@solarflare.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/35285/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/35285/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 317A81B654;\n\tTue, 20 Feb 2018 08:36:29 +0100 (CET)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 23C7D1B336\n\tfor <dev@dpdk.org>; Tue, 20 Feb 2018 08:35:48 +0100 (CET)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\t2EE8F980066 for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:47 +0000 (UTC)", "from sfocexch01r.SolarFlarecom.com (10.20.40.34) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 19 Feb 2018 23:35:44 -0800", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tsfocexch01r.SolarFlarecom.com (10.20.40.34) with Microsoft SMTP\n\tServer (TLS) id 15.0.1044.25; Mon, 19 Feb 2018 23:35:15 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 19 Feb 2018 23:35:15 -0800", "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZESw025149; Tue, 20 Feb 2018 07:35:14 GMT", "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZBu4020529; Tue, 20 Feb 2018 07:35:14 GMT" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Andy Moreton <amoreton@solarflare.com>", "Date": "Tue, 20 Feb 2018 07:34:10 +0000", "Message-ID": "<1519112078-20113-53-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.2.3", "In-Reply-To": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "References": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MDID": "1519112147-PsM3xJrmTSXj", "Subject": "[dpdk-dev] [PATCH 52/80] net/sfc/base: move PHY/link config to ef10\n\tNIC board cfg", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Andy Moreton <amoreton@solarflare.com>\n\nSigned-off-by: Andy Moreton <amoreton@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_nic.c | 18 +++++++++++++++++-\n drivers/net/sfc/base/hunt_nic.c | 31 ++++++++-----------------------\n drivers/net/sfc/base/medford2_nic.c | 30 +++++++-----------------------\n drivers/net/sfc/base/medford_nic.c | 30 +++++++-----------------------\n 4 files changed, 39 insertions(+), 70 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c\nindex 5f4357b..8e9d7a1 100644\n--- a/drivers/net/sfc/base/ef10_nic.c\n+++ b/drivers/net/sfc/base/ef10_nic.c\n@@ -1548,6 +1548,8 @@ ef10_nic_board_cfg(\n \tconst efx_nic_ops_t *enop = enp->en_enop;\n \tefx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);\n \tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tef10_link_state_t els;\n+\tefx_port_t *epp = &(enp->en_port);\n \tuint32_t board_type = 0;\n \tuint32_t port;\n \tuint32_t pf;\n@@ -1619,13 +1621,27 @@ ef10_nic_board_cfg(\n \tencp->enc_board_type = board_type;\n \tencp->enc_clk_mult = 1; /* not used for EF10 */\n \n+\t/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */\n+\tif ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)\n+\t\tgoto fail6;\n+\n+\t/* Obtain the default PHY advertised capabilities */\n+\tif ((rc = ef10_phy_get_link(enp, &els)) != 0)\n+\t\tgoto fail7;\n+\tepp->ep_default_adv_cap_mask = els.els_adv_cap_mask;\n+\tepp->ep_adv_cap_mask = els.els_adv_cap_mask;\n+\n \t/* Get remaining controller-specific board config */\n \tif ((rc = enop->eno_board_cfg(enp)) != 0)\n \t\tif (rc != EACCES)\n-\t\t\tgoto fail6;\n+\t\t\tgoto fail8;\n \n \treturn (0);\n \n+fail8:\n+\tEFSYS_PROBE(fail8);\n+fail7:\n+\tEFSYS_PROBE(fail7);\n fail6:\n \tEFSYS_PROBE(fail6);\n fail5:\ndiff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c\nindex 58c2d13..d33d2db 100644\n--- a/drivers/net/sfc/base/hunt_nic.c\n+++ b/drivers/net/sfc/base/hunt_nic.c\n@@ -77,7 +77,6 @@ hunt_board_cfg(\n \t__in\t\tefx_nic_t *enp)\n {\n \tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n-\tef10_link_state_t els;\n \tefx_port_t *epp = &(enp->en_port);\n \tuint32_t mask;\n \tuint32_t flags;\n@@ -96,16 +95,6 @@ hunt_board_cfg(\n \tEFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K\t== 8192);\n \tencp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;\n \n-\t/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */\n-\tif ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)\n-\t\tgoto fail1;\n-\n-\t/* Obtain the default PHY advertised capabilities */\n-\tif ((rc = ef10_phy_get_link(enp, &els)) != 0)\n-\t\tgoto fail2;\n-\tepp->ep_default_adv_cap_mask = els.els_adv_cap_mask;\n-\tepp->ep_adv_cap_mask = els.els_adv_cap_mask;\n-\n \t/*\n \t * Enable firmware workarounds for hardware errata.\n \t * Expected responses are:\n@@ -133,7 +122,7 @@ hunt_board_cfg(\n \telse if ((rc == ENOTSUP) || (rc == ENOENT))\n \t\tencp->enc_bug35388_workaround = B_FALSE;\n \telse\n-\t\tgoto fail3;\n+\t\tgoto fail1;\n \n \t/*\n \t * If the bug41750 workaround is enabled, then do not test interrupts,\n@@ -152,7 +141,7 @@ hunt_board_cfg(\n \t} else if ((rc == ENOTSUP) || (rc == ENOENT)) {\n \t\tencp->enc_bug41750_workaround = B_FALSE;\n \t} else {\n-\t\tgoto fail4;\n+\t\tgoto fail2;\n \t}\n \tif (EFX_PCI_FUNCTION_IS_VF(encp)) {\n \t\t/* Interrupt testing does not work for VFs. See bug50084. */\n@@ -190,12 +179,12 @@ hunt_board_cfg(\n \t} else if ((rc == ENOTSUP) || (rc == ENOENT)) {\n \t\tencp->enc_bug26807_workaround = B_FALSE;\n \t} else {\n-\t\tgoto fail5;\n+\t\tgoto fail3;\n \t}\n \n \t/* Get clock frequencies (in MHz). */\n \tif ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)\n-\t\tgoto fail6;\n+\t\tgoto fail4;\n \n \t/*\n \t * The Huntington timer quantum is 1536 sysclk cycles, documented for\n@@ -214,7 +203,7 @@ hunt_board_cfg(\n \n \t/* Check capabilities of running datapath firmware */\n \tif ((rc = ef10_get_datapath_caps(enp)) != 0)\n-\t\tgoto fail7;\n+\t\tgoto fail5;\n \n \t/* Alignment for receive packet DMA buffers */\n \tencp->enc_rx_buf_align_start = 1;\n@@ -264,13 +253,13 @@ hunt_board_cfg(\n \t * can result in time-of-check/time-of-use bugs.\n \t */\n \tif ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)\n-\t\tgoto fail8;\n+\t\tgoto fail6;\n \tencp->enc_privilege_mask = mask;\n \n \t/* Get interrupt vector limits */\n \tif ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {\n \t\tif (EFX_PCI_FUNCTION_IS_PF(encp))\n-\t\t\tgoto fail9;\n+\t\t\tgoto fail7;\n \n \t\t/* Ignore error (cannot query vector limits from a VF). */\n \t\tbase = 0;\n@@ -286,7 +275,7 @@ hunt_board_cfg(\n \tencp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;\n \n \tif ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)\n-\t\tgoto fail10;\n+\t\tgoto fail8;\n \tencp->enc_required_pcie_bandwidth_mbps = bandwidth;\n \n \t/* All Huntington devices have a PCIe Gen3, 8 lane connector */\n@@ -294,10 +283,6 @@ hunt_board_cfg(\n \n \treturn (0);\n \n-fail10:\n-\tEFSYS_PROBE(fail10);\n-fail9:\n-\tEFSYS_PROBE(fail9);\n fail8:\n \tEFSYS_PROBE(fail8);\n fail7:\ndiff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c\nindex 2bd3d83..afaafb9 100644\n--- a/drivers/net/sfc/base/medford2_nic.c\n+++ b/drivers/net/sfc/base/medford2_nic.c\n@@ -49,8 +49,6 @@ medford2_board_cfg(\n \t__in\t\tefx_nic_t *enp)\n {\n \tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n-\tef10_link_state_t els;\n-\tefx_port_t *epp = &(enp->en_port);\n \tuint32_t mask;\n \tuint32_t sysclk, dpcpu_clk;\n \tuint32_t base, nvec;\n@@ -72,16 +70,6 @@ medford2_board_cfg(\n \tencp->enc_vi_window_shift = vi_window_shift;\n \n \n-\t/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */\n-\tif ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)\n-\t\tgoto fail2;\n-\n-\t/* Obtain the default PHY advertised capabilities */\n-\tif ((rc = ef10_phy_get_link(enp, &els)) != 0)\n-\t\tgoto fail3;\n-\tepp->ep_default_adv_cap_mask = els.els_adv_cap_mask;\n-\tepp->ep_adv_cap_mask = els.els_adv_cap_mask;\n-\n \t/*\n \t * Enable firmware workarounds for hardware errata.\n \t * Expected responses are:\n@@ -122,11 +110,11 @@ medford2_board_cfg(\n \telse if ((rc == ENOTSUP) || (rc == ENOENT))\n \t\tencp->enc_bug61265_workaround = B_FALSE;\n \telse\n-\t\tgoto fail4;\n+\t\tgoto fail2;\n \n \t/* Get clock frequencies (in MHz). */\n \tif ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)\n-\t\tgoto fail5;\n+\t\tgoto fail3;\n \n \t/*\n \t * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for\n@@ -138,7 +126,7 @@ medford2_board_cfg(\n \n \t/* Check capabilities of running datapath firmware */\n \tif ((rc = ef10_get_datapath_caps(enp)) != 0)\n-\t\tgoto fail6;\n+\t\tgoto fail4;\n \n \t/* Alignment for receive packet DMA buffers */\n \tencp->enc_rx_buf_align_start = 1;\n@@ -146,7 +134,7 @@ medford2_board_cfg(\n \t/* Get the RX DMA end padding alignment configuration */\n \tif ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {\n \t\tif (rc != EACCES)\n-\t\t\tgoto fail7;\n+\t\t\tgoto fail5;\n \n \t\t/* Assume largest tail padding size supported by hardware */\n \t\tend_padding = 256;\n@@ -198,13 +186,13 @@ medford2_board_cfg(\n \t * can result in time-of-check/time-of-use bugs.\n \t */\n \tif ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)\n-\t\tgoto fail8;\n+\t\tgoto fail6;\n \tencp->enc_privilege_mask = mask;\n \n \t/* Get interrupt vector limits */\n \tif ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {\n \t\tif (EFX_PCI_FUNCTION_IS_PF(encp))\n-\t\t\tgoto fail9;\n+\t\t\tgoto fail7;\n \n \t\t/* Ignore error (cannot query vector limits from a VF). */\n \t\tbase = 0;\n@@ -227,16 +215,12 @@ medford2_board_cfg(\n \n \trc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);\n \tif (rc != 0)\n-\t\tgoto fail10;\n+\t\tgoto fail8;\n \tencp->enc_required_pcie_bandwidth_mbps = bandwidth;\n \tencp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;\n \n \treturn (0);\n \n-fail10:\n-\tEFSYS_PROBE(fail10);\n-fail9:\n-\tEFSYS_PROBE(fail9);\n fail8:\n \tEFSYS_PROBE(fail8);\n fail7:\ndiff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c\nindex 7840c33..afa6493 100644\n--- a/drivers/net/sfc/base/medford_nic.c\n+++ b/drivers/net/sfc/base/medford_nic.c\n@@ -47,8 +47,6 @@ medford_board_cfg(\n \t__in\t\tefx_nic_t *enp)\n {\n \tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n-\tef10_link_state_t els;\n-\tefx_port_t *epp = &(enp->en_port);\n \tuint32_t mask;\n \tuint32_t sysclk, dpcpu_clk;\n \tuint32_t base, nvec;\n@@ -71,16 +69,6 @@ medford_board_cfg(\n \tEFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K\t== 8192);\n \tencp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;\n \n-\t/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */\n-\tif ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)\n-\t\tgoto fail1;\n-\n-\t/* Obtain the default PHY advertised capabilities */\n-\tif ((rc = ef10_phy_get_link(enp, &els)) != 0)\n-\t\tgoto fail2;\n-\tepp->ep_default_adv_cap_mask = els.els_adv_cap_mask;\n-\tepp->ep_adv_cap_mask = els.els_adv_cap_mask;\n-\n \t/*\n \t * Enable firmware workarounds for hardware errata.\n \t * Expected responses are:\n@@ -121,11 +109,11 @@ medford_board_cfg(\n \telse if ((rc == ENOTSUP) || (rc == ENOENT))\n \t\tencp->enc_bug61265_workaround = B_FALSE;\n \telse\n-\t\tgoto fail3;\n+\t\tgoto fail1;\n \n \t/* Get clock frequencies (in MHz). */\n \tif ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)\n-\t\tgoto fail4;\n+\t\tgoto fail2;\n \n \t/*\n \t * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for\n@@ -137,7 +125,7 @@ medford_board_cfg(\n \n \t/* Check capabilities of running datapath firmware */\n \tif ((rc = ef10_get_datapath_caps(enp)) != 0)\n-\t\tgoto fail5;\n+\t\tgoto fail3;\n \n \t/* Alignment for receive packet DMA buffers */\n \tencp->enc_rx_buf_align_start = 1;\n@@ -145,7 +133,7 @@ medford_board_cfg(\n \t/* Get the RX DMA end padding alignment configuration */\n \tif ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {\n \t\tif (rc != EACCES)\n-\t\t\tgoto fail6;\n+\t\t\tgoto fail4;\n \n \t\t/* Assume largest tail padding size supported by hardware */\n \t\tend_padding = 256;\n@@ -197,13 +185,13 @@ medford_board_cfg(\n \t * can result in time-of-check/time-of-use bugs.\n \t */\n \tif ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)\n-\t\tgoto fail7;\n+\t\tgoto fail5;\n \tencp->enc_privilege_mask = mask;\n \n \t/* Get interrupt vector limits */\n \tif ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {\n \t\tif (EFX_PCI_FUNCTION_IS_PF(encp))\n-\t\t\tgoto fail8;\n+\t\t\tgoto fail6;\n \n \t\t/* Ignore error (cannot query vector limits from a VF). */\n \t\tbase = 0;\n@@ -226,16 +214,12 @@ medford_board_cfg(\n \n \trc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);\n \tif (rc != 0)\n-\t\tgoto fail9;\n+\t\tgoto fail7;\n \tencp->enc_required_pcie_bandwidth_mbps = bandwidth;\n \tencp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;\n \n \treturn (0);\n \n-fail9:\n-\tEFSYS_PROBE(fail9);\n-fail8:\n-\tEFSYS_PROBE(fail8);\n fail7:\n \tEFSYS_PROBE(fail7);\n fail6:\n", "prefixes": [ "dpdk-dev", "52/80" ] }