Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/35271/?format=api
{ "id": 35271, "url": "http://patches.dpdk.org/api/patches/35271/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-31-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1519112078-20113-31-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1519112078-20113-31-git-send-email-arybchenko@solarflare.com", "date": "2018-02-20T07:33:48", "name": "[dpdk-dev,30/80] net/sfc/base: report memory BAR number", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0d131edb704e363c38370b6d74920be96588c5f2", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-31-git-send-email-arybchenko@solarflare.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/35271/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/35271/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 290851B3D5;\n\tTue, 20 Feb 2018 08:36:06 +0100 (CET)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 19C221B1CA\n\tfor <dev@dpdk.org>; Tue, 20 Feb 2018 08:35:32 +0100 (CET)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\tCE2F29C005C for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:30 +0000 (UTC)", "from sfocexch01r.SolarFlarecom.com (10.20.40.34) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 19 Feb 2018 23:35:28 -0800", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tsfocexch01r.SolarFlarecom.com (10.20.40.34) with Microsoft SMTP\n\tServer (TLS) id 15.0.1044.25; Mon, 19 Feb 2018 23:35:14 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 19 Feb 2018 23:35:14 -0800", "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZDt1025003; Tue, 20 Feb 2018 07:35:13 GMT", "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZBtg020529; Tue, 20 Feb 2018 07:35:13 GMT" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Andy Moreton <amoreton@solarflare.com>", "Date": "Tue, 20 Feb 2018 07:33:48 +0000", "Message-ID": "<1519112078-20113-31-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.2.3", "In-Reply-To": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "References": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MDID": "1519112131-JYefSz2VyDpu", "Subject": "[dpdk-dev] [PATCH 30/80] net/sfc/base: report memory BAR number", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Andy Moreton <amoreton@solarflare.com>\n\nOn Medford and earlier controllers the BAR layout is:\n PF BAR 0: (32bit I/O) I/O mapped registers\n PF BAR 2: (64bit Mem) Memory mapped registers (VI aperture)\n PF BAR 4: (64bit Mem) MSI-X tables\n\n VF BAR 0: (64bit Mem) Memory mapped registers (VI aperture)\n VF BAR 2: (64bit Mem) MSI-X tables\n\nOn Medford2, the layout is:\n PF/VF BAR 0: (64bit Mem) Memory mapped registers (VI aperture)\n PF/VF BAR 2: (64bit Mem) MSI-X tables\n\nMake the VI aperture BAR number available for drivers that need it.\nRemove EFX_MEM_BAR define as it it is not correct on all platforms.\n\nSigned-off-by: Andy Moreton <amoreton@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/efx.h | 15 +++++++++++++--\n drivers/net/sfc/base/efx_nic.c | 26 ++++++++++----------------\n drivers/net/sfc/sfc.c | 40 ++++++++++++++++------------------------\n 3 files changed, 39 insertions(+), 42 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h\nindex b038029..6149abf 100644\n--- a/drivers/net/sfc/base/efx.h\n+++ b/drivers/net/sfc/base/efx.h\n@@ -48,7 +48,8 @@ extern\t__checkReturn\tefx_rc_t\n efx_family(\n \t__in\t\tuint16_t venid,\n \t__in\t\tuint16_t devid,\n-\t__out\t\tefx_family_t *efp);\n+\t__out\t\tefx_family_t *efp,\n+\t__out\t\tunsigned int *membarp);\n \n \n #define\tEFX_PCI_VENID_SFC\t\t\t0x1924\n@@ -74,7 +75,17 @@ efx_family(\n #define\tEFX_PCI_DEVID_MEDFORD2\t\t\t0x0B03\t/* SFC9250 PF */\n #define\tEFX_PCI_DEVID_MEDFORD2_VF\t\t0x1B03\t/* SFC9250 VF */\n \n-#define\tEFX_MEM_BAR\t2\n+\n+#define\tEFX_MEM_BAR_SIENA\t\t\t2\n+\n+#define\tEFX_MEM_BAR_HUNTINGTON_PF\t\t2\n+#define\tEFX_MEM_BAR_HUNTINGTON_VF\t\t0\n+\n+#define\tEFX_MEM_BAR_MEDFORD_PF\t\t\t2\n+#define\tEFX_MEM_BAR_MEDFORD_VF\t\t\t0\n+\n+#define\tEFX_MEM_BAR_MEDFORD2\t\t\t0\n+\n \n /* Error codes */\n \ndiff --git a/drivers/net/sfc/base/efx_nic.c b/drivers/net/sfc/base/efx_nic.c\nindex 7f32959..bce0def 100644\n--- a/drivers/net/sfc/base/efx_nic.c\n+++ b/drivers/net/sfc/base/efx_nic.c\n@@ -7,11 +7,13 @@\n #include \"efx.h\"\n #include \"efx_impl.h\"\n \n+\n \t__checkReturn\tefx_rc_t\n efx_family(\n \t__in\t\tuint16_t venid,\n \t__in\t\tuint16_t devid,\n-\t__out\t\tefx_family_t *efp)\n+\t__out\t\tefx_family_t *efp,\n+\t__out\t\tunsigned int *membarp)\n {\n \tif (venid == EFX_PCI_VENID_SFC) {\n \t\tswitch (devid) {\n@@ -21,12 +23,10 @@ efx_family(\n \t\t\t * Hardware default for PF0 of uninitialised Siena.\n \t\t\t * manftest must be able to cope with this device id.\n \t\t\t */\n-\t\t\t*efp = EFX_FAMILY_SIENA;\n-\t\t\treturn (0);\n-\n \t\tcase EFX_PCI_DEVID_BETHPAGE:\n \t\tcase EFX_PCI_DEVID_SIENA:\n \t\t\t*efp = EFX_FAMILY_SIENA;\n+\t\t\t*membarp = EFX_MEM_BAR_SIENA;\n \t\t\treturn (0);\n #endif /* EFSYS_OPT_SIENA */\n \n@@ -36,17 +36,16 @@ efx_family(\n \t\t\t * Hardware default for PF0 of uninitialised Huntington.\n \t\t\t * manftest must be able to cope with this device id.\n \t\t\t */\n-\t\t\t*efp = EFX_FAMILY_HUNTINGTON;\n-\t\t\treturn (0);\n-\n \t\tcase EFX_PCI_DEVID_FARMINGDALE:\n \t\tcase EFX_PCI_DEVID_GREENPORT:\n \t\t\t*efp = EFX_FAMILY_HUNTINGTON;\n+\t\t\t*membarp = EFX_MEM_BAR_HUNTINGTON_PF;\n \t\t\treturn (0);\n \n \t\tcase EFX_PCI_DEVID_FARMINGDALE_VF:\n \t\tcase EFX_PCI_DEVID_GREENPORT_VF:\n \t\t\t*efp = EFX_FAMILY_HUNTINGTON;\n+\t\t\t*membarp = EFX_MEM_BAR_HUNTINGTON_VF;\n \t\t\treturn (0);\n #endif /* EFSYS_OPT_HUNTINGTON */\n \n@@ -56,15 +55,14 @@ efx_family(\n \t\t\t * Hardware default for PF0 of uninitialised Medford.\n \t\t\t * manftest must be able to cope with this device id.\n \t\t\t */\n-\t\t\t*efp = EFX_FAMILY_MEDFORD;\n-\t\t\treturn (0);\n-\n \t\tcase EFX_PCI_DEVID_MEDFORD:\n \t\t\t*efp = EFX_FAMILY_MEDFORD;\n+\t\t\t*membarp = EFX_MEM_BAR_MEDFORD_PF;\n \t\t\treturn (0);\n \n \t\tcase EFX_PCI_DEVID_MEDFORD_VF:\n \t\t\t*efp = EFX_FAMILY_MEDFORD;\n+\t\t\t*membarp = EFX_MEM_BAR_MEDFORD_VF;\n \t\t\treturn (0);\n #endif /* EFSYS_OPT_MEDFORD */\n \n@@ -74,15 +72,10 @@ efx_family(\n \t\t\t * Hardware default for PF0 of uninitialised Medford2.\n \t\t\t * manftest must be able to cope with this device id.\n \t\t\t */\n-\t\t\t*efp = EFX_FAMILY_MEDFORD2;\n-\t\t\treturn (0);\n-\n \t\tcase EFX_PCI_DEVID_MEDFORD2:\n-\t\t\t*efp = EFX_FAMILY_MEDFORD2;\n-\t\t\treturn (0);\n-\n \t\tcase EFX_PCI_DEVID_MEDFORD2_VF:\n \t\t\t*efp = EFX_FAMILY_MEDFORD2;\n+\t\t\t*membarp = EFX_MEM_BAR_MEDFORD2;\n \t\t\treturn (0);\n #endif /* EFSYS_OPT_MEDFORD2 */\n \n@@ -96,6 +89,7 @@ efx_family(\n \treturn (ENOTSUP);\n }\n \n+\n #if EFSYS_OPT_SIENA\n \n static const efx_nic_ops_t\t__efx_nic_siena_ops = {\ndiff --git a/drivers/net/sfc/sfc.c b/drivers/net/sfc/sfc.c\nindex ac5fdca..7eb9305 100644\n--- a/drivers/net/sfc/sfc.c\n+++ b/drivers/net/sfc/sfc.c\n@@ -530,27 +530,18 @@ sfc_close(struct sfc_adapter *sa)\n }\n \n static int\n-sfc_mem_bar_init(struct sfc_adapter *sa)\n+sfc_mem_bar_init(struct sfc_adapter *sa, unsigned int membar)\n {\n \tstruct rte_eth_dev *eth_dev = sa->eth_dev;\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n \tefsys_bar_t *ebp = &sa->mem_bar;\n-\tunsigned int i;\n-\tstruct rte_mem_resource *res;\n-\n-\tfor (i = 0; i < RTE_DIM(pci_dev->mem_resource); i++) {\n-\t\tres = &pci_dev->mem_resource[i];\n-\t\tif ((res->len != 0) && (res->phys_addr != 0)) {\n-\t\t\t/* Found first memory BAR */\n-\t\t\tSFC_BAR_LOCK_INIT(ebp, eth_dev->data->name);\n-\t\t\tebp->esb_rid = i;\n-\t\t\tebp->esb_dev = pci_dev;\n-\t\t\tebp->esb_base = res->addr;\n-\t\t\treturn 0;\n-\t\t}\n-\t}\n+\tstruct rte_mem_resource *res = &pci_dev->mem_resource[membar];\n \n-\treturn EFAULT;\n+\tSFC_BAR_LOCK_INIT(ebp, eth_dev->data->name);\n+\tebp->esb_rid = membar;\n+\tebp->esb_dev = pci_dev;\n+\tebp->esb_base = res->addr;\n+\treturn 0;\n }\n \n static void\n@@ -753,6 +744,7 @@ int\n sfc_probe(struct sfc_adapter *sa)\n {\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(sa->eth_dev);\n+\tunsigned int membar;\n \tefx_nic_t *enp;\n \tint rc;\n \n@@ -763,17 +755,17 @@ sfc_probe(struct sfc_adapter *sa)\n \tsa->socket_id = rte_socket_id();\n \trte_atomic32_init(&sa->restart_required);\n \n-\tsfc_log_init(sa, \"init mem bar\");\n-\trc = sfc_mem_bar_init(sa);\n-\tif (rc != 0)\n-\t\tgoto fail_mem_bar_init;\n-\n \tsfc_log_init(sa, \"get family\");\n \trc = efx_family(pci_dev->id.vendor_id, pci_dev->id.device_id,\n-\t\t\t&sa->family);\n+\t\t\t&sa->family, &membar);\n \tif (rc != 0)\n \t\tgoto fail_family;\n-\tsfc_log_init(sa, \"family is %u\", sa->family);\n+\tsfc_log_init(sa, \"family is %u, membar is %u\", sa->family, membar);\n+\n+\tsfc_log_init(sa, \"init mem bar\");\n+\trc = sfc_mem_bar_init(sa, membar);\n+\tif (rc != 0)\n+\t\tgoto fail_mem_bar_init;\n \n \tsfc_log_init(sa, \"create nic\");\n \trte_spinlock_init(&sa->nic_lock);\n@@ -804,10 +796,10 @@ sfc_probe(struct sfc_adapter *sa)\n \tefx_nic_destroy(enp);\n \n fail_nic_create:\n-fail_family:\n \tsfc_mem_bar_fini(sa);\n \n fail_mem_bar_init:\n+fail_family:\n \tsfc_log_init(sa, \"failed %d\", rc);\n \treturn rc;\n }\n", "prefixes": [ "dpdk-dev", "30/80" ] }