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GET /api/patches/35258/?format=api
{ "id": 35258, "url": "http://patches.dpdk.org/api/patches/35258/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-81-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1519112078-20113-81-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1519112078-20113-81-git-send-email-arybchenko@solarflare.com", "date": "2018-02-20T07:34:38", "name": "[dpdk-dev,80/80] net/sfc/base: sync MCDI headers and TLV layout", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "92e0aab51dc70eaf690dd31c6365d15bb4c0d539", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-81-git-send-email-arybchenko@solarflare.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/35258/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/35258/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F045C1B355;\n\tTue, 20 Feb 2018 08:35:52 +0100 (CET)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id E1ECA1B1CE\n\tfor <dev@dpdk.org>; Tue, 20 Feb 2018 08:35:24 +0100 (CET)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\t960866C0053 for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:23 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 19 Feb 2018 23:35:17 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 19 Feb 2018 23:35:16 -0800", "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZF45025317 for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:15 GMT", "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZBuW020529 for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:15 GMT" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "Date": "Tue, 20 Feb 2018 07:34:38 +0000", "Message-ID": "<1519112078-20113-81-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.2.3", "In-Reply-To": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "References": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MDID": "1519112124-Du429NIseNjV", "Subject": "[dpdk-dev] [PATCH 80/80] net/sfc/base: sync MCDI headers and TLV\n\tlayout", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Regenerate MCDI and TLV layout headers from firmwaresrc to\npick up DPDK firmware variant and related Rx queue and filtering\nextensions.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_tlv_layout.h | 67 ++--\n drivers/net/sfc/base/efx_regs_mcdi.h | 699 ++++++++++++++++++++++++++++++++-\n 2 files changed, 709 insertions(+), 57 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/ef10_tlv_layout.h b/drivers/net/sfc/base/ef10_tlv_layout.h\nindex e94bc3e..b19dc2a 100644\n--- a/drivers/net/sfc/base/ef10_tlv_layout.h\n+++ b/drivers/net/sfc/base/ef10_tlv_layout.h\n@@ -408,6 +408,7 @@ struct tlv_firmware_options {\n #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \\\n MC_CMD_FW_PACKED_STREAM_HASH_MODE_1\n #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE\n+#define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK\n };\n \n /* Voltage settings\n@@ -547,6 +548,17 @@ struct tlv_global_port_mode {\n uint32_t length;\n uint32_t port_mode;\n #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */\n+\n+/* Huntington port modes */\n+#define TLV_PORT_MODE_10G (0)\n+#define TLV_PORT_MODE_40G (1)\n+#define TLV_PORT_MODE_10G_10G (2)\n+#define TLV_PORT_MODE_40G_40G (3)\n+#define TLV_PORT_MODE_10G_10G_10G_10G (4)\n+#define TLV_PORT_MODE_40G_10G_10G (6)\n+#define TLV_PORT_MODE_10G_10G_40G (7)\n+\n+/* Medford (and later) port modes */\n #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */\n #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */\n #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */\n@@ -554,8 +566,8 @@ struct tlv_global_port_mode {\n #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */\n #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */\n #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */\n-#define TLV_PORT_MODE_2x1_2x1 (4) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 - WARNING: bug3720: On Newport only, this is actually Quad 10G on mdi0 */\n-#define TLV_PORT_MODE_4x1_NA (5) /* Quad 10G/25G on mdi0 */\n+#define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */\n+#define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */\n #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */\n #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */\n #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */\n@@ -566,7 +578,13 @@ struct tlv_global_port_mode {\n #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */\n #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */\n #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */\n-/* Below modes are eftest only, to allow snapper explicit selection between multi-channel and LLPCS. In production, this selection is automatic and outside world should not care about LLPCS */\n+\n+/* Snapper-only Medford2 port modes.\n+ * These modes are eftest only, to allow snapper explicit\n+ * selection between multi-channel and LLPCS. In production,\n+ * this selection is automatic and outside world should not\n+ * care about LLPCS.\n+ */\n #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */\n #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */\n #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */\n@@ -575,42 +593,13 @@ struct tlv_global_port_mode {\n #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */\n #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL\n \n-/* Deprecated aliases */\n-#define TLV_PORT_MODE_10G TLV_PORT_MODE_1x1_NA\n-#define TLV_PORT_MODE_40G TLV_PORT_MODE_1x4_NA\n-#define TLV_PORT_MODE_10G_10G TLV_PORT_MODE_1x1_1x1\n-#define TLV_PORT_MODE_40G_40G TLV_PORT_MODE_1x4_1x4\n-#define TLV_PORT_MODE_10G_10G_10G_10G TLV_PORT_MODE_2x1_2x1\n-#define TLV_PORT_MODE_10G_10G_10G_10G_Q1 TLV_PORT_MODE_2x1_2x1 /* bug63720: Do not use */\n-#define TLV_PORT_MODE_10G_10G_10G_10G_Q TLV_PORT_MODE_4x1_NA\n-#define TLV_PORT_MODE_40G_10G_10G TLV_PORT_MODE_1x4_2x1\n-#define TLV_PORT_MODE_10G_10G_40G TLV_PORT_MODE_2x1_1x4\n-#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 TLV_PORT_MODE_NA_4x1\n-#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 TLV_PORT_MODE_BUG63720_DO_NOT_USE /* bug63720: Do not use */\n-#define TLV_PORT_MODE_25G TLV_PORT_MODE_1x1_NA /* Single 25G on mdi0 */\n-#define TLV_PORT_MODE_100G_Q1 TLV_PORT_MODE_1x4_NA /* Single 100G on mdi0 */\n-#define TLV_PORT_MODE_100G_Q2 TLV_PORT_MODE_NA_1x4 /* Single 100G on mdi1 */\n-#define TLV_PORT_MODE_50G_Q1 TLV_PORT_MODE_1x2_NA /* Single 50G on mdi0 */\n-#define TLV_PORT_MODE_50G_Q2 TLV_PORT_MODE_NA_1x2 /* Single 50G on mdi1 */\n-#define TLV_PORT_MODE_25G_25G TLV_PORT_MODE_1x1_1x1 /* Single 25G on mdi0, single 25G on mdi1 */\n-#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2 TLV_PORT_MODE_2x1_2x1 /* Dual 25G on mdi0, dual 25G on mdi1 */\n-#define TLV_PORT_MODE_25G_25G_25G_25G_Q1 TLV_PORT_MODE_4x1_NA /* Quad 25G on mdi0 */\n-#define TLV_PORT_MODE_25G_25G_25G_25G_Q2 TLV_PORT_MODE_NA_4x1 /* Quad 25G on mdi1 */\n-#define TLV_PORT_MODE_40G_25G_25G TLV_PORT_MODE_1x4_2x1 /* Single 40G on mdi0, dual 25G on mdi1 */\n-#define TLV_PORT_MODE_25G_25G_40G TLV_PORT_MODE_2x1_1x4 /* Dual 25G on mdi0, single 40G on mdi1 */\n-#define TLV_PORT_MODE_50G_50G_Q1_Q2 TLV_PORT_MODE_1x2_1x2 /* Single 50G on mdi0, single 50G on mdi1 */\n-#define TLV_PORT_MODE_50G_50G_Q1 TLV_PORT_MODE_2x2_NA /* Dual 50G on mdi0 */\n-#define TLV_PORT_MODE_50G_50G_Q2 TLV_PORT_MODE_NA_2x2 /* Dual 50G on mdi1 */\n-#define TLV_PORT_MODE_40G_50G TLV_PORT_MODE_1x4_1x2 /* Single 40G on mdi0, single 50G on mdi1 */\n-#define TLV_PORT_MODE_50G_40G TLV_PORT_MODE_1x2_1x4 /* Single 50G on mdi0, single 40G on mdi1 */\n-#define TLV_PORT_MODE_50G_25G_25G TLV_PORT_MODE_1x2_2x1 /* Single 50G on mdi0, dual 25G on mdi1 */\n-#define TLV_PORT_MODE_25G_25G_50G TLV_PORT_MODE_2x1_1x2 /* Dual 25G on mdi0, single 50G on mdi1 */\n-/* eftest only, see comments for _LL modes above */\n-#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2_LL TLV_PORT_MODE_2x1_2x1_LL /* Dual 25G on mdi0, dual 25G on mdi1, low-latency PCS */\n-#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_LL TLV_PORT_MODE_4x1_NA_LL /* Quad 25G on mdi0, low-latency PCS */\n-#define TLV_PORT_MODE_25G_25G_25G_25G_Q2_LL TLV_PORT_MODE_NA_4x1_LL /* Quad 25G on mdi1, low-latency PCS */\n-#define TLV_PORT_MODE_25G_LL TLV_PORT_MODE_1x1_NA_LL /* Single 10G/25G on mdi0, low-latency PCS */\n-#define TLV_PORT_MODE_25G_25G_LL TLV_PORT_MODE_1x1_1x1_LL /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */\n+/* Deprecated Medford aliases - DO NOT USE IN NEW CODE */\n+#define TLV_PORT_MODE_10G_10G_10G_10G_Q (5)\n+#define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4)\n+#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8)\n+#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9)\n+\n+#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL\n };\n \n /* Type of the v-switch created implicitly by the firmware */\ndiff --git a/drivers/net/sfc/base/efx_regs_mcdi.h b/drivers/net/sfc/base/efx_regs_mcdi.h\nindex efddb1f..cb2c094 100644\n--- a/drivers/net/sfc/base/efx_regs_mcdi.h\n+++ b/drivers/net/sfc/base/efx_regs_mcdi.h\n@@ -319,10 +319,17 @@\n #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)\n #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)\n #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)\n-/* Points to the recovery mode entry point. */\n+/* Points to the recovery mode entry point. Misnamed but kept for compatibility. */\n #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)\n #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)\n #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)\n+/* Points to the recovery mode entry point. Same as above, but the right name. */\n+#define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)\n+#define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)\n+#define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)\n+\n+/* Points to noflash mode entry point. */\n+#define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)\n \n /* The command set exported by the boot ROM (MCDI v0) */\n #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS {\t\t\\\n@@ -395,6 +402,8 @@\n #define\tMCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16\n #define\tMCDI_EVENT_LINKCHANGE_SPEED_LBN 16\n #define\tMCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4\n+/* enum: Link is down or link speed could not be determined */\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0\n /* enum: 100Mbs */\n #define\tMCDI_EVENT_LINKCHANGE_SPEED_100M 0x1\n /* enum: 1Gbs */\n@@ -2721,6 +2730,8 @@\n * support\n */\n #define\tMC_CMD_FW_RULES_ENGINE 0x5\n+/* enum: Prefer to use firmware with additional DPDK support */\n+#define\tMC_CMD_FW_DPDK 0x6\n /* enum: Only this option is allowed for non-admin functions */\n #define\tMC_CMD_FW_DONT_CARE 0xffffffff\n \n@@ -6694,6 +6705,12 @@\n #define\tLICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800\n /* enum: Capture SolarSystem 1G */\n #define\tLICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000\n+/* enum: ScaleOut Onload */\n+#define\tLICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000\n+/* enum: SCS Network Analytics Dashboard */\n+#define\tLICENSED_APP_ID_DSHBRD 0x4000\n+/* enum: SolarCapture Trading Analytics */\n+#define\tLICENSED_APP_ID_SCATRD 0x8000\n #define\tLICENSED_APP_ID_ID_LBN 0\n #define\tLICENSED_APP_ID_ID_WIDTH 32\n \n@@ -6760,6 +6777,12 @@\n #define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1\n #define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12\n #define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1\n+#define\tLICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13\n+#define\tLICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1\n+#define\tLICENSED_V3_APPS_DSHBRD_LBN 14\n+#define\tLICENSED_V3_APPS_DSHBRD_WIDTH 1\n+#define\tLICENSED_V3_APPS_SCATRD_LBN 15\n+#define\tLICENSED_V3_APPS_SCATRD_WIDTH 1\n #define\tLICENSED_V3_APPS_MASK_LBN 0\n #define\tLICENSED_V3_APPS_MASK_WIDTH 64\n \n@@ -6810,6 +6833,14 @@\n * is the same as for TX_EV_COMPLETION.\n */\n #define\tTX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11\n+/* enum: This is the low part of a TX timestamp for a CTPIO transmission. The\n+ * event format is the same as for TX_EV_TSTAMP_LO\n+ */\n+#define\tTX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12\n+/* enum: This is the high part of a TX timestamp for a CTPIO transmission. The\n+ * event format is the same as for TX_EV_TSTAMP_HI\n+ */\n+#define\tTX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13\n /* enum: This is the low part of a TX timestamp event */\n #define\tTX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51\n /* enum: This is the high part of a TX timestamp event */\n@@ -7182,11 +7213,15 @@\n /* Size, in entries */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0\n #define\tMC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4\n-/* The EVQ to send events to. This is an index originally specified to INIT_EVQ\n+/* The EVQ to send events to. This is an index originally specified to\n+ * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.\n */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4\n #define\tMC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4\n-/* The value to put in the event data. Check hardware spec. for valid range. */\n+/* The value to put in the event data. Check hardware spec. for valid range.\n+ * This field is ignored if DMA_MODE == EQUAL_STRIDE_PACKED_STREAM or DMA_MODE\n+ * == PACKED_STREAM.\n+ */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8\n #define\tMC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n@@ -7217,6 +7252,13 @@\n #define\tMC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0\n /* enum: Pack multiple packets into large descriptors (for SolarCapture) */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1\n+/* enum: Pack multiple packets into large descriptors using the format designed\n+ * to maximise packet rate. This mode uses 1 \"bucket\" per descriptor with\n+ * multiple fixed-size packet buffers within each bucket. For a full\n+ * description see SF-119419-TC. This mode is only supported by \"dpdk\" datapath\n+ * firmware.\n+ */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1\n #define\tMC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15\n@@ -7246,12 +7288,122 @@\n #define\tMC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540\n #define\tMC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4\n \n+/* MC_CMD_INIT_RXQ_V3_IN msgrequest */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_LEN 560\n+/* Size, in entries */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0\n+#define\tMC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4\n+/* The EVQ to send events to. This is an index originally specified to\n+ * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.\n+ */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4\n+#define\tMC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4\n+/* The value to put in the event data. Check hardware spec. for valid range.\n+ * This field is ignored if DMA_MODE == EQUAL_STRIDE_PACKED_STREAM or DMA_MODE\n+ * == PACKED_STREAM.\n+ */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8\n+#define\tMC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4\n+/* Desired instance. Must be set to a specific instance, which is a function\n+ * local queue index.\n+ */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12\n+#define\tMC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4\n+/* There will be more flags here. */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3\n+#define\tMC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4\n+/* enum: One packet per descriptor (for normal networking) */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0\n+/* enum: Pack multiple packets into large descriptors (for SolarCapture) */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1\n+/* enum: Pack multiple packets into large descriptors using the format designed\n+ * to maximise packet rate. This mode uses 1 \"bucket\" per descriptor with\n+ * multiple fixed-size packet buffers within each bucket. For a full\n+ * description see SF-119419-TC. This mode is only supported by \"dpdk\" datapath\n+ * firmware.\n+ */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1\n+/* Owner ID to use if in buffer mode (zero if physical) */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20\n+#define\tMC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4\n+/* The port ID associated with the v-adaptor which should contain this DMAQ. */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4\n+/* 64-bit address of 4k of 4k-aligned host memory buffer */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64\n+/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540\n+#define\tMC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4\n+/* The number of packet buffers that will be contained within each\n+ * EQUAL_STRIDE_PACKED_STREAM format bucket supplied by the driver. This field\n+ * is ignored unless DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.\n+ */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544\n+#define\tMC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4\n+/* The length in bytes of the area in each packet buffer that can be written to\n+ * by the adapter. This is used to store the packet prefix and the packet\n+ * payload. This length does not include any end padding added by the driver.\n+ * This field is ignored unless DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.\n+ */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548\n+#define\tMC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4\n+/* The length in bytes of a single packet buffer within a\n+ * EQUAL_STRIDE_PACKED_STREAM format bucket. This field is ignored unless\n+ * DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.\n+ */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552\n+#define\tMC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4\n+/* The maximum time in nanoseconds that the datapath will be backpressured if\n+ * there are no RX descriptors available. If the timeout is reached and there\n+ * are still no descriptors then the packet will be dropped. A timeout of 0\n+ * means the datapath will never be blocked. This field is ignored unless\n+ * DMA_MODE == EQUAL_STRIDE_PACKED_STREAM.\n+ */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556\n+#define\tMC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4\n+\n /* MC_CMD_INIT_RXQ_OUT msgresponse */\n #define\tMC_CMD_INIT_RXQ_OUT_LEN 0\n \n /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */\n #define\tMC_CMD_INIT_RXQ_EXT_OUT_LEN 0\n \n+/* MC_CMD_INIT_RXQ_V3_OUT msgresponse */\n+#define\tMC_CMD_INIT_RXQ_V3_OUT_LEN 0\n+\n \n /***********************************/\n /* MC_CMD_INIT_TXQ\n@@ -8168,6 +8320,273 @@\n #define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156\n #define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16\n \n+/* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional\n+ * filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via\n+ * its rte_flow API. This extension is only useful with the sfc_efx driver\n+ * included as part of DPDK, used in conjunction with the dpdk datapath\n+ * firmware variant.\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_LEN 180\n+/* identifies the type of operation requested */\n+#define\tMC_CMD_FILTER_OP_V3_IN_OP_OFST 0\n+#define\tMC_CMD_FILTER_OP_V3_IN_OP_LEN 4\n+/* Enum values, see field(s): */\n+/* MC_CMD_FILTER_OP_IN/OP */\n+/* filter handle (for remove / unsubscribe operations) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8\n+#define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8\n+/* The port ID associated with the v-adaptor which should contain this filter.\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12\n+#define\tMC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4\n+/* fields to include in match criteria */\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1\n+/* receive destination */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4\n+/* enum: drop packets */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0\n+/* enum: receive to host */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1\n+/* enum: receive to MC */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2\n+/* enum: loop back to TXDP 0 */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3\n+/* enum: loop back to TXDP 1 */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4\n+/* receive queue handle (for multiple queue modes, this is the base queue) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4\n+/* receive mode */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4\n+/* enum: receive to just the specified queue */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0\n+/* enum: receive to multiple queues using RSS context */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1\n+/* enum: receive to multiple queues using .1p mapping */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2\n+/* enum: install a filter entry that will never match; for test purposes only\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000\n+/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for\n+ * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or\n+ * MC_CMD_DOT1P_MAPPING_ALLOC.\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32\n+#define\tMC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4\n+/* transmit domain (reserved; set to 0) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4\n+/* transmit destination (either set the MAC and/or PM bits for explicit\n+ * control, or set this field to TX_DEST_DEFAULT for sensible default\n+ * behaviour)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4\n+/* enum: request default behaviour (based on filter type) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1\n+/* source MAC address to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44\n+#define\tMC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6\n+/* source port to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50\n+#define\tMC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2\n+/* destination MAC address to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52\n+#define\tMC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6\n+/* destination port to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58\n+#define\tMC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2\n+/* Ethernet type to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60\n+#define\tMC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2\n+/* Inner VLAN tag to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62\n+#define\tMC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2\n+/* Outer VLAN tag to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64\n+#define\tMC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2\n+/* IP protocol to match (in low byte; set high byte to 0) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66\n+#define\tMC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2\n+/* Firmware defined register 0 to match (reserved; set to 0) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68\n+#define\tMC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4\n+/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP\n+ * protocol is GRE) to match (as bytes in network order; set last byte to 0 for\n+ * VXLAN/NVGRE, or 1 for Geneve)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8\n+/* enum: Match VXLAN traffic with this VNI */\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0\n+/* enum: Match Geneve traffic with this VNI */\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1\n+/* enum: Reserved for experimental development use */\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe\n+#define\tMC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0\n+#define\tMC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24\n+#define\tMC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24\n+#define\tMC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8\n+/* enum: Match NVGRE traffic with this VSID */\n+#define\tMC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0\n+/* source IP address to match (as bytes in network order; set last 12 bytes to\n+ * 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76\n+#define\tMC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16\n+/* destination IP address to match (as bytes in network order; set last 12\n+ * bytes to 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92\n+#define\tMC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16\n+/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network\n+ * order)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6\n+/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2\n+/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in\n+ * network order)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6\n+/* VXLAN/NVGRE inner frame destination port to match (as bytes in network\n+ * order)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2\n+/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2\n+/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2\n+/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2\n+/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to\n+ * 0)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2\n+/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set\n+ * to 0)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4\n+/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set\n+ * to 0)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4\n+/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network\n+ * order; set last 12 bytes to 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16\n+/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network\n+ * order; set last 12 bytes to 0 for IPv4 address)\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156\n+#define\tMC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16\n+/* Set an action for all packets matching this filter. The DPDK driver and dpdk\n+ * f/w variant use their own specific delivery structures, which are documented\n+ * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything\n+ * other than MATCH_ACTION_NONE when the NIC is running another f/w variant\n+ * will cause the filter insertion to fail with ENOTSUP.\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4\n+/* enum: do nothing extra */\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0\n+/* enum: Set the match flag in the packet prefix for packets matching the\n+ * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to\n+ * support the DPDK rte_flow \"FLAG\" action.\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1\n+/* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching\n+ * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to\n+ * support the DPDK rte_flow \"MARK\" action.\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2\n+/* the mark value for MATCH_ACTION_MARK */\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4\n+\n /* MC_CMD_FILTER_OP_OUT msgresponse */\n #define\tMC_CMD_FILTER_OP_OUT_LEN 12\n /* identifies the type of operation requested */\n@@ -9198,6 +9617,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2\n /* enum: Rules engine RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5\n+/* enum: Packet rate RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6\n /* enum: BIST RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a\n /* enum: RXDP Test firmware image 1 */\n@@ -9231,6 +9652,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3\n /* enum: Rules engine TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5\n+/* enum: Packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6\n /* enum: BIST TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d\n /* enum: TXDP Test firmware image 1 */\n@@ -9275,6 +9698,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7\n /* enum: Rules engine RX PD production firmware */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: reserved value - do not use (bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED_9 0x9\n+/* enum: Packet rate RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa\n /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n /* enum: RX PD firmware parsing but not filtering network overlay tunnel\n@@ -9314,6 +9741,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7\n /* enum: Rules engine TX PD production firmware */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: reserved value - do not use (bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED_9 0x9\n+/* enum: Packet rate TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa\n /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n /* Hardware capabilities of NIC */\n@@ -9400,6 +9831,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2\n /* enum: Rules engine RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5\n+/* enum: Packet rate RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6\n /* enum: BIST RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a\n /* enum: RXDP Test firmware image 1 */\n@@ -9433,6 +9866,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3\n /* enum: Rules engine TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5\n+/* enum: Packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6\n /* enum: BIST TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d\n /* enum: TXDP Test firmware image 1 */\n@@ -9477,6 +9912,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7\n /* enum: Rules engine RX PD production firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: reserved value - do not use (bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED_9 0x9\n+/* enum: Packet rate RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa\n /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n /* enum: RX PD firmware parsing but not filtering network overlay tunnel\n@@ -9516,6 +9955,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7\n /* enum: Rules engine TX PD production firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: reserved value - do not use (bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED_9 0x9\n+/* enum: Packet rate TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa\n /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n /* Hardware capabilities of NIC */\n@@ -9559,6 +10002,18 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present\n * on older firmware (check the length).\n */\n@@ -9689,6 +10144,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2\n /* enum: Rules engine RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5\n+/* enum: Packet rate RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6\n /* enum: BIST RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a\n /* enum: RXDP Test firmware image 1 */\n@@ -9722,6 +10179,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3\n /* enum: Rules engine TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5\n+/* enum: Packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6\n /* enum: BIST TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d\n /* enum: TXDP Test firmware image 1 */\n@@ -9766,6 +10225,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7\n /* enum: Rules engine RX PD production firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: reserved value - do not use (bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED_9 0x9\n+/* enum: Packet rate RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa\n /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n /* enum: RX PD firmware parsing but not filtering network overlay tunnel\n@@ -9805,6 +10268,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7\n /* enum: Rules engine TX PD production firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: reserved value - do not use (bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED_9 0x9\n+/* enum: Packet rate TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa\n /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n /* Hardware capabilities of NIC */\n@@ -9848,6 +10315,18 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present\n * on older firmware (check the length).\n */\n@@ -10003,6 +10482,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2\n /* enum: Rules engine RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5\n+/* enum: Packet rate RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6\n /* enum: BIST RXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a\n /* enum: RXDP Test firmware image 1 */\n@@ -10036,6 +10517,8 @@\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3\n /* enum: Rules engine TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5\n+/* enum: Packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6\n /* enum: BIST TXDP firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d\n /* enum: TXDP Test firmware image 1 */\n@@ -10080,6 +10563,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7\n /* enum: Rules engine RX PD production firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: reserved value - do not use (bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED_9 0x9\n+/* enum: Packet rate RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa\n /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n /* enum: RX PD firmware parsing but not filtering network overlay tunnel\n@@ -10119,6 +10606,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7\n /* enum: Rules engine TX PD production firmware */\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: reserved value - do not use (bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED_9 0x9\n+/* enum: Packet rate TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa\n /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n /* Hardware capabilities of NIC */\n@@ -10162,6 +10653,18 @@\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present\n * on older firmware (check the length).\n */\n@@ -12187,6 +12690,10 @@\n #define\tMC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6\n /* enum: Read Figure Of Merit (eye quality, higher is better). */\n #define\tMC_CMD_KR_TUNE_IN_READ_FOM 0x7\n+/* enum: Start/stop link training frames */\n+#define\tMC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8\n+/* enum: Issue KR link training command (control training coefficients) */\n+#define\tMC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9\n /* Align the arguments to 32 bits */\n #define\tMC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1\n #define\tMC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3\n@@ -12257,34 +12764,54 @@\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc\n /* enum: CTLE peaking (0-31, Medford2) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd\n-/* enum: DFE Tap1 - even path (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe\n-/* enum: DFE Tap1 - odd path (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf\n-/* enum: DFE Tap2 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10\n-/* enum: DFE Tap3 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11\n-/* enum: DFE Tap4 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12\n-/* enum: DFE Tap5 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13\n-/* enum: DFE Tap6 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14\n-/* enum: DFE Tap7 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15\n-/* enum: DFE Tap8 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16\n-/* enum: DFE Tap9 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17\n-/* enum: DFE Tap10 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18\n-/* enum: DFE Tap11 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19\n-/* enum: DFE Tap12 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */\n+/* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a\n-/* enum: I/Q clk offset (Medford2 - 0-5, sign-magnitude (-5 - +5)) */\n+/* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b\n+/* enum: Negative h1 polarity data sampler offset calibration code, even path\n+ * (Medford2 - 6 bit signed (-29 - +29)))\n+ */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c\n+/* enum: Negative h1 polarity data sampler offset calibration code, odd path\n+ * (Medford2 - 6 bit signed (-29 - +29)))\n+ */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d\n+/* enum: Positive h1 polarity data sampler offset calibration code, even path\n+ * (Medford2 - 6 bit signed (-29 - +29)))\n+ */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e\n+/* enum: Positive h1 polarity data sampler offset calibration code, odd path\n+ * (Medford2 - 6 bit signed (-29 - +29)))\n+ */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f\n+/* enum: CDR calibration loop code (Medford2) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20\n+/* enum: CDR integral loop code (Medford2) */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */\n@@ -12461,9 +12988,12 @@\n /* Align the arguments to 32 bits */\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3\n-/* Port-relative lane to scan eye on */\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1\n /* Scan duration / cycle count */\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4\n@@ -12499,12 +13029,91 @@\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1\n \n /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */\n #define\tMC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4\n #define\tMC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0\n #define\tMC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4\n \n+/* MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_LEN 8\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_LEN 3\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */\n+\n+/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN msgrequest */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LEN 28\n+/* Requested operation */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1\n+/* Align the arguments to 32 bits */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_LEN 3\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4\n+/* Set INITIALIZE state */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_OFST 8\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4\n+/* Set PRESET state */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_OFST 12\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4\n+/* C(-1) request */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_OFST 16\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */\n+/* C(0) request */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_OFST 20\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4\n+/* Enum values, see field(s): */\n+/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */\n+/* C(+1) request */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_OFST 24\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4\n+/* Enum values, see field(s): */\n+/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */\n+\n+/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT msgresponse */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_LEN 24\n+/* C(-1) status */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */\n+/* C(0) status */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4\n+/* Enum values, see field(s): */\n+/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT/CM1 */\n+/* C(+1) status */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_OFST 8\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4\n+/* Enum values, see field(s): */\n+/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT/CM1 */\n+/* C(-1) value */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_OFST 12\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4\n+/* C(0) value */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_OFST 16\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4\n+/* C(+1) status */\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_OFST 20\n+#define\tMC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4\n+\n \n /***********************************/\n /* MC_CMD_PCIE_TUNE\n@@ -15760,6 +16369,45 @@\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_LEN 1\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_NUM 6\n \n+/* MC_CMD_TSAN_INFO_OUT_GET_CFG_V2 msgresponse */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_LEN 36\n+/* Information about the configuration parameters returned in this response. */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CONFIG_WORD_OFST 0\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CONFIG_WORD_LEN 4\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CAP_FLAGS_LBN 0\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CAP_FLAGS_WIDTH 16\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_FLAG_HOST_UUID_VALID_LBN 0\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_FLAG_HOST_UUID_VALID_WIDTH 1\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_NUM_PORTS_LBN 16\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_NUM_PORTS_WIDTH 8\n+/* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID\n+ * for further details.\n+ */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_HOST_UUID_OFST 4\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_HOST_UUID_LEN 1\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_HOST_UUID_NUM 16\n+/* A unique identifier per adapter. The base MAC address of the card is used\n+ * for this purpose.\n+ */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_GUID_OFST 20\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_GUID_LEN 1\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_GUID_NUM 6\n+/* Unused bytes, defined for 32-bit alignment of new fields. */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_UNUSED_OFST 26\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_UNUSED_LEN 2\n+/* Maximum number of TSA statistics counters in each direction of dataflow\n+ * supported on the card. Note that the statistics counters are always\n+ * allocated in pairs, i.e. a counter ID is associated with one Tx and one Rx\n+ * counter.\n+ */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_MAX_STATS_OFST 28\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_MAX_STATS_LEN 4\n+/* Width of each statistics counter (represented in bits). This gives an\n+ * indication of wrap point to the user.\n+ */\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_STATS_WIDTH_OFST 32\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_STATS_WIDTH_LEN 4\n+\n \n /***********************************/\n /* MC_CMD_TSA_STATISTICS\n@@ -16290,6 +16938,21 @@\n #define\tMC_CMD_SUC_VERSION_OUT_CHIP_ID_OFST 20\n #define\tMC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4\n \n+/* MC_CMD_SUC_BOOT_VERSION_IN msgrequest: Get the version of the SUC boot\n+ * loader.\n+ */\n+#define\tMC_CMD_SUC_BOOT_VERSION_IN_LEN 4\n+#define\tMC_CMD_SUC_BOOT_VERSION_IN_MAGIC_OFST 0\n+#define\tMC_CMD_SUC_BOOT_VERSION_IN_MAGIC_LEN 4\n+/* enum: Requests the SUC boot version. */\n+#define\tMC_CMD_SUC_VERSION_GET_BOOT_VERSION 0xb007700b\n+\n+/* MC_CMD_SUC_BOOT_VERSION_OUT msgresponse */\n+#define\tMC_CMD_SUC_BOOT_VERSION_OUT_LEN 4\n+/* The SUC boot version */\n+#define\tMC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0\n+#define\tMC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4\n+\n \n /***********************************/\n /* MC_CMD_SUC_MANFTEST\n", "prefixes": [ "dpdk-dev", "80/80" ] }