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GET /api/patches/35256/?format=api
{ "id": 35256, "url": "http://patches.dpdk.org/api/patches/35256/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-64-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1519112078-20113-64-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1519112078-20113-64-git-send-email-arybchenko@solarflare.com", "date": "2018-02-20T07:34:21", "name": "[dpdk-dev,63/80] net/sfc/base: clarify port mode names and masks", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ae56ce35aa7fc3b5ae40b794a4b2cb3147ffe324", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-64-git-send-email-arybchenko@solarflare.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/35256/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/35256/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E3DF91B34B;\n\tTue, 20 Feb 2018 08:35:50 +0100 (CET)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 955181B1C6\n\tfor <dev@dpdk.org>; Tue, 20 Feb 2018 08:35:24 +0100 (CET)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\t82FC16C0053 for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:21 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 19 Feb 2018 23:35:16 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 19 Feb 2018 23:35:15 -0800", "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZEc8025189; Tue, 20 Feb 2018 07:35:14 GMT", "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZBuF020529; Tue, 20 Feb 2018 07:35:14 GMT" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Andy Moreton <amoreton@solarflare.com>", "Date": "Tue, 20 Feb 2018 07:34:21 +0000", "Message-ID": "<1519112078-20113-64-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.2.3", "In-Reply-To": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "References": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MDID": "1519112124-NGU72+9RKy7h", "Subject": "[dpdk-dev] [PATCH 63/80] net/sfc/base: clarify port mode names and\n\tmasks", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Andy Moreton <amoreton@solarflare.com>\n\nNew port mode names are defined for Medford2 and later, and\nthe existing names are aliased to them. Add comments with the\nnumeric port mode to clarify the external port modes table.\n\nSigned-off-by: Andy Moreton <amoreton@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_nic.c | 60 +++++++++++++++++++++--------------------\n drivers/net/sfc/base/hunt_nic.c | 6 ++---\n 2 files changed, 34 insertions(+), 32 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c\nindex cd871c4..2b8b043 100644\n--- a/drivers/net/sfc/base/ef10_nic.c\n+++ b/drivers/net/sfc/base/ef10_nic.c\n@@ -1345,11 +1345,11 @@ static struct ef10_external_port_map_s {\n \t */\n \t{\n \t\tEFX_FAMILY_HUNTINGTON,\n-\t\t(1 << TLV_PORT_MODE_10G) |\n-\t\t(1 << TLV_PORT_MODE_10G_10G) |\n-\t\t(1 << TLV_PORT_MODE_10G_10G_10G_10G),\n-\t\t1,\n-\t\t1\n+\t\t(1U << TLV_PORT_MODE_10G) |\t\t\t/* mode 0 */\n+\t\t(1U << TLV_PORT_MODE_10G_10G) |\t\t\t/* mode 2 */\n+\t\t(1U << TLV_PORT_MODE_10G_10G_10G_10G),\t\t/* mode 4 */\n+\t\t1,\t/* ports per cage */\n+\t\t1\t/* first cage */\n \t},\n \t/*\n \t * Modes that on Medford allocate each port number to a separate\n@@ -1361,10 +1361,10 @@ static struct ef10_external_port_map_s {\n \t */\n \t{\n \t\tEFX_FAMILY_MEDFORD,\n-\t\t(1 << TLV_PORT_MODE_10G) |\n-\t\t(1 << TLV_PORT_MODE_10G_10G),\n-\t\t1,\n-\t\t1\n+\t\t(1U << TLV_PORT_MODE_10G) |\t\t\t/* mode 0 */\n+\t\t(1U << TLV_PORT_MODE_10G_10G),\t\t\t/* mode 2 */\n+\t\t1,\t/* ports per cage */\n+\t\t1\t/* first cage */\n \t},\n \t/*\n \t * Modes which for Huntington identify a chip variant where 2\n@@ -1377,12 +1377,12 @@ static struct ef10_external_port_map_s {\n \t */\n \t{\n \t\tEFX_FAMILY_HUNTINGTON,\n-\t\t(1 << TLV_PORT_MODE_40G) |\n-\t\t(1 << TLV_PORT_MODE_40G_40G) |\n-\t\t(1 << TLV_PORT_MODE_40G_10G_10G) |\n-\t\t(1 << TLV_PORT_MODE_10G_10G_40G),\n-\t\t2,\n-\t\t1\n+\t\t(1U << TLV_PORT_MODE_40G) |\t\t\t/* mode 1 */\n+\t\t(1U << TLV_PORT_MODE_40G_40G) |\t\t\t/* mode 3 */\n+\t\t(1U << TLV_PORT_MODE_40G_10G_10G) |\t\t/* mode 6 */\n+\t\t(1U << TLV_PORT_MODE_10G_10G_40G),\t\t/* mode 7 */\n+\t\t2,\t/* ports per cage */\n+\t\t1\t/* first cage */\n \t},\n \t/*\n \t * Modes that on Medford allocate 2 adjacent port numbers to each\n@@ -1394,13 +1394,14 @@ static struct ef10_external_port_map_s {\n \t */\n \t{\n \t\tEFX_FAMILY_MEDFORD,\n-\t\t(1 << TLV_PORT_MODE_40G) |\n-\t\t(1 << TLV_PORT_MODE_40G_40G) |\n-\t\t(1 << TLV_PORT_MODE_40G_10G_10G) |\n-\t\t(1 << TLV_PORT_MODE_10G_10G_40G) |\n-\t\t(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),\n-\t\t2,\n-\t\t1\n+\t\t(1U << TLV_PORT_MODE_40G) |\t\t\t/* mode 1 */\n+\t\t(1U << TLV_PORT_MODE_40G_40G) |\t\t\t/* mode 3 */\n+\t\t(1U << TLV_PORT_MODE_40G_10G_10G) |\t\t/* mode 6 */\n+\t\t(1U << TLV_PORT_MODE_10G_10G_40G) |\t\t/* mode 7 */\n+\t\t/* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */\n+\t\t(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),\t/* mode 9 */\n+\t\t2,\t/* ports per cage */\n+\t\t1\t/* first cage */\n \t},\n \t/*\n \t * Modes that on Medford allocate 4 adjacent port numbers to each\n@@ -1412,10 +1413,11 @@ static struct ef10_external_port_map_s {\n \t */\n \t{\n \t\tEFX_FAMILY_MEDFORD,\n-\t\t(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |\n-\t\t(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),\n-\t\t4,\n-\t\t1,\n+\t\t(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) |\t/* mode 5 */\n+\t\t/* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */\n+\t\t(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1),\t/* mode 4 */\n+\t\t4,\t/* ports per cage */\n+\t\t1\t/* first cage */\n \t},\n \t/*\n \t * Modes that on Medford allocate 4 adjacent port numbers to each\n@@ -1427,9 +1429,9 @@ static struct ef10_external_port_map_s {\n \t */\n \t{\n \t\tEFX_FAMILY_MEDFORD,\n-\t\t(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),\n-\t\t4,\n-\t\t2\n+\t\t(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2),\t/* mode 8 */\n+\t\t4,\t/* ports per cage */\n+\t\t2\t/* first cage */\n \t},\n };\n \ndiff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c\nindex e39f817..16ea81d 100644\n--- a/drivers/net/sfc/base/hunt_nic.c\n+++ b/drivers/net/sfc/base/hunt_nic.c\n@@ -36,7 +36,7 @@ hunt_nic_get_required_pcie_bandwidth(\n \t\tgoto out;\n \t}\n \n-\tif (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {\n+\tif (port_modes & (1U << TLV_PORT_MODE_40G_40G)) {\n \t\t/*\n \t\t * This needs the full PCIe bandwidth (and could use\n \t\t * more) - roughly 64 Gbit/s for 8 lanes of Gen3.\n@@ -45,9 +45,9 @@ hunt_nic_get_required_pcie_bandwidth(\n \t\t\t EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)\n \t\t\tgoto fail1;\n \t} else {\n-\t\tif (port_modes & (1 << TLV_PORT_MODE_40G)) {\n+\t\tif (port_modes & (1U << TLV_PORT_MODE_40G)) {\n \t\t\tmax_port_mode = TLV_PORT_MODE_40G;\n-\t\t} else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {\n+\t\t} else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) {\n \t\t\tmax_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;\n \t\t} else {\n \t\t\t/* Assume two 10G ports */\n", "prefixes": [ "dpdk-dev", "63/80" ] }