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GET /api/patches/35231/?format=api
{ "id": 35231, "url": "http://patches.dpdk.org/api/patches/35231/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-27-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1519112078-20113-27-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1519112078-20113-27-git-send-email-arybchenko@solarflare.com", "date": "2018-02-20T07:33:44", "name": "[dpdk-dev,26/80] net/sfc/base: update hardware headers for Medford2", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a41fb01a119589416269e04ca386f99448b3a77e", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-27-git-send-email-arybchenko@solarflare.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/35231/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/35231/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D00C31B2B4;\n\tTue, 20 Feb 2018 08:35:32 +0100 (CET)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 321A81B1A1\n\tfor <dev@dpdk.org>; Tue, 20 Feb 2018 08:35:19 +0100 (CET)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\t16D43400056 for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:18 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 19 Feb 2018 23:35:14 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 19 Feb 2018 23:35:14 -0800", "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZDmW024974; Tue, 20 Feb 2018 07:35:13 GMT", "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZBtc020529; Tue, 20 Feb 2018 07:35:13 GMT" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Andy Moreton <amoreton@solarflare.com>", "Date": "Tue, 20 Feb 2018 07:33:44 +0000", "Message-ID": "<1519112078-20113-27-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.2.3", "In-Reply-To": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "References": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MDID": "1519112118-xnJVWb34gHJJ", "Subject": "[dpdk-dev] [PATCH 26/80] net/sfc/base: update hardware headers for\n\tMedford2", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Andy Moreton <amoreton@solarflare.com>\n\nThe changes to efx_regs_ef10.h are auto-generated and include:\n\n - Updated event RX_L4_CLASS which is now 2 bits (was 3).\n The encoding of TCP, UDP and UNKNOWN are unchanged so\n the narrower Medford2 field definition is compatible with\n all controllers.\n\n - Fix definition of FATSOv2 option descriptors. These were\n added manually and differ from the auto-generated values\n in some fields (not yet used in common code). The field\n definitions have been corrected to agree with the Linux net\n driver headers and SF-108452-SW.\n\nThe remaining changes adapt the common code to use the updated\nheaders.\n\nSigned-off-by: Andy Moreton <amoreton@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_ev.c | 47 +++++++-\n drivers/net/sfc/base/efx_regs_ef10.h | 207 ++++++++++++++++++++++++++++++-----\n drivers/net/sfc/sfc_ef10_rx.c | 18 ++-\n 3 files changed, 237 insertions(+), 35 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/ef10_ev.c b/drivers/net/sfc/base/ef10_ev.c\nindex 36ff2cb..c7173c3 100644\n--- a/drivers/net/sfc/base/ef10_ev.c\n+++ b/drivers/net/sfc/base/ef10_ev.c\n@@ -868,12 +868,23 @@ ef10_ev_rx(\n #endif\n \n \tsize = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);\n+\tcont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);\n \tnext_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);\n \teth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);\n \tmac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);\n \tl3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);\n-\tl4_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L4_CLASS);\n-\tcont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);\n+\n+\t/*\n+\t * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only\n+\t * 2 bits wide on Medford2. Check it is safe to use the Medford2 field\n+\t * and values for all EF10 controllers.\n+\t */\n+\tEFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);\n+\tEFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);\n+\tEFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);\n+\tEFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);\n+\n+\tl4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);\n \n \tif (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {\n \t\t/* Drop this event */\n@@ -952,10 +963,22 @@ ef10_ev_rx(\n \t\t\tflags |= EFX_CKSUM_IPV4;\n \t\t}\n \n-\t\tif (l4_class == ESE_DZ_L4_CLASS_TCP) {\n+\t\t/*\n+\t\t * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is\n+\t\t * only 2 bits wide on Medford2. Check it is safe to use the\n+\t\t * Medford2 field and values for all EF10 controllers.\n+\t\t */\n+\t\tEFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==\n+\t\t ESF_DE_RX_L4_CLASS_LBN);\n+\t\tEFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);\n+\t\tEFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);\n+\t\tEFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==\n+\t\t ESE_DE_L4_CLASS_UNKNOWN);\n+\n+\t\tif (l4_class == ESE_FZ_L4_CLASS_TCP) {\n \t\t\tEFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);\n \t\t\tflags |= EFX_PKT_TCP;\n-\t\t} else if (l4_class == ESE_DZ_L4_CLASS_UDP) {\n+\t\t} else if (l4_class == ESE_FZ_L4_CLASS_UDP) {\n \t\t\tEFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);\n \t\t\tflags |= EFX_PKT_UDP;\n \t\t} else {\n@@ -967,10 +990,22 @@ ef10_ev_rx(\n \tcase ESE_DZ_L3_CLASS_IP6_FRAG:\n \t\tflags |= EFX_PKT_IPV6;\n \n-\t\tif (l4_class == ESE_DZ_L4_CLASS_TCP) {\n+\t\t/*\n+\t\t * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is\n+\t\t * only 2 bits wide on Medford2. Check it is safe to use the\n+\t\t * Medford2 field and values for all EF10 controllers.\n+\t\t */\n+\t\tEFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==\n+\t\t ESF_DE_RX_L4_CLASS_LBN);\n+\t\tEFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);\n+\t\tEFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);\n+\t\tEFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==\n+\t\t ESE_DE_L4_CLASS_UNKNOWN);\n+\n+\t\tif (l4_class == ESE_FZ_L4_CLASS_TCP) {\n \t\t\tEFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);\n \t\t\tflags |= EFX_PKT_TCP;\n-\t\t} else if (l4_class == ESE_DZ_L4_CLASS_UDP) {\n+\t\t} else if (l4_class == ESE_FZ_L4_CLASS_UDP) {\n \t\t\tEFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);\n \t\t\tflags |= EFX_PKT_UDP;\n \t\t} else {\ndiff --git a/drivers/net/sfc/base/efx_regs_ef10.h b/drivers/net/sfc/base/efx_regs_ef10.h\nindex 5f97830..025dc08 100644\n--- a/drivers/net/sfc/base/efx_regs_ef10.h\n+++ b/drivers/net/sfc/base/efx_regs_ef10.h\n@@ -24,7 +24,7 @@ extern \"C\" {\n */\n \n #define\tER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000\n-/* hunta0,medforda0=pcie_pf_bar2 */\n+/* hunta0,medforda0,medford2a0=pf_dbell_bar */\n #define\tER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face\n \n \n@@ -38,7 +38,7 @@ extern \"C\" {\n */\n \n #define\tER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010\n-/* hunta0,medforda0=pcie_pf_bar2 */\n+/* hunta0,medforda0,medford2a0=pf_dbell_bar */\n #define\tER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4\n #define\tER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8\n #define\tER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face\n@@ -54,7 +54,7 @@ extern \"C\" {\n */\n \n #define\tER_DZ_BIU_INT_ISR_REG_OFST 0x00000090\n-/* hunta0,medforda0=pcie_pf_bar2 */\n+/* hunta0,medforda0,medford2a0=pf_dbell_bar */\n #define\tER_DZ_BIU_INT_ISR_REG_RESET 0x0\n \n \n@@ -68,7 +68,7 @@ extern \"C\" {\n */\n \n #define\tER_DZ_MC_DB_LWRD_REG_OFST 0x00000200\n-/* hunta0,medforda0=pcie_pf_bar2 */\n+/* hunta0,medforda0,medford2a0=pf_dbell_bar */\n #define\tER_DZ_MC_DB_LWRD_REG_RESET 0x0\n \n \n@@ -82,7 +82,7 @@ extern \"C\" {\n */\n \n #define\tER_DZ_MC_DB_HWRD_REG_OFST 0x00000204\n-/* hunta0,medforda0=pcie_pf_bar2 */\n+/* hunta0,medforda0,medford2a0=pf_dbell_bar */\n #define\tER_DZ_MC_DB_HWRD_REG_RESET 0x0\n \n \n@@ -96,7 +96,7 @@ extern \"C\" {\n */\n \n #define\tER_DZ_EVQ_RPTR_REG_OFST 0x00000400\n-/* hunta0,medforda0=pcie_pf_bar2 */\n+/* hunta0,medforda0,medford2a0=pf_dbell_bar */\n #define\tER_DZ_EVQ_RPTR_REG_STEP 8192\n #define\tER_DZ_EVQ_RPTR_REG_ROWS 2048\n #define\tER_DZ_EVQ_RPTR_REG_RESET 0x0\n@@ -109,12 +109,84 @@ extern \"C\" {\n \n \n /*\n+ * EVQ_RPTR_REG_64K(32bit):\n+ *\n+ */\n+\n+#define\tER_FZ_EVQ_RPTR_REG_64K_OFST 0x00000400\n+/* medford2a0=pf_dbell_bar */\n+#define\tER_FZ_EVQ_RPTR_REG_64K_STEP 65536\n+#define\tER_FZ_EVQ_RPTR_REG_64K_ROWS 2048\n+#define\tER_FZ_EVQ_RPTR_REG_64K_RESET 0x0\n+\n+\n+#define\tERF_FZ_EVQ_RPTR_VLD_LBN 15\n+#define\tERF_FZ_EVQ_RPTR_VLD_WIDTH 1\n+#define\tERF_FZ_EVQ_RPTR_LBN 0\n+#define\tERF_FZ_EVQ_RPTR_WIDTH 15\n+\n+\n+/*\n+ * EVQ_RPTR_REG_16K(32bit):\n+ *\n+ */\n+\n+#define\tER_FZ_EVQ_RPTR_REG_16K_OFST 0x00000400\n+/* medford2a0=pf_dbell_bar */\n+#define\tER_FZ_EVQ_RPTR_REG_16K_STEP 16384\n+#define\tER_FZ_EVQ_RPTR_REG_16K_ROWS 2048\n+#define\tER_FZ_EVQ_RPTR_REG_16K_RESET 0x0\n+\n+\n+/* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */\n+/* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */\n+/* defined as ERF_FZ_EVQ_RPTR_LBN 0; */\n+/* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */\n+\n+\n+/*\n+ * EVQ_TMR_REG_64K(32bit):\n+ *\n+ */\n+\n+#define\tER_FZ_EVQ_TMR_REG_64K_OFST 0x00000420\n+/* medford2a0=pf_dbell_bar */\n+#define\tER_FZ_EVQ_TMR_REG_64K_STEP 65536\n+#define\tER_FZ_EVQ_TMR_REG_64K_ROWS 2048\n+#define\tER_FZ_EVQ_TMR_REG_64K_RESET 0x0\n+\n+\n+#define\tERF_FZ_TC_TIMER_MODE_LBN 14\n+#define\tERF_FZ_TC_TIMER_MODE_WIDTH 2\n+#define\tERF_FZ_TC_TIMER_VAL_LBN 0\n+#define\tERF_FZ_TC_TIMER_VAL_WIDTH 14\n+\n+\n+/*\n+ * EVQ_TMR_REG_16K(32bit):\n+ *\n+ */\n+\n+#define\tER_FZ_EVQ_TMR_REG_16K_OFST 0x00000420\n+/* medford2a0=pf_dbell_bar */\n+#define\tER_FZ_EVQ_TMR_REG_16K_STEP 16384\n+#define\tER_FZ_EVQ_TMR_REG_16K_ROWS 2048\n+#define\tER_FZ_EVQ_TMR_REG_16K_RESET 0x0\n+\n+\n+/* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */\n+/* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */\n+/* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */\n+/* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */\n+\n+\n+/*\n * EVQ_TMR_REG(32bit):\n *\n */\n \n #define\tER_DZ_EVQ_TMR_REG_OFST 0x00000420\n-/* hunta0,medforda0=pcie_pf_bar2 */\n+/* hunta0,medforda0,medford2a0=pf_dbell_bar */\n #define\tER_DZ_EVQ_TMR_REG_STEP 8192\n #define\tER_DZ_EVQ_TMR_REG_ROWS 2048\n #define\tER_DZ_EVQ_TMR_REG_RESET 0x0\n@@ -127,12 +199,28 @@ extern \"C\" {\n \n \n /*\n+ * RX_DESC_UPD_REG_16K(32bit):\n+ *\n+ */\n+\n+#define\tER_FZ_RX_DESC_UPD_REG_16K_OFST 0x00000830\n+/* medford2a0=pf_dbell_bar */\n+#define\tER_FZ_RX_DESC_UPD_REG_16K_STEP 16384\n+#define\tER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048\n+#define\tER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0\n+\n+\n+#define\tERF_FZ_RX_DESC_WPTR_LBN 0\n+#define\tERF_FZ_RX_DESC_WPTR_WIDTH 12\n+\n+\n+/*\n * RX_DESC_UPD_REG(32bit):\n *\n */\n \n #define\tER_DZ_RX_DESC_UPD_REG_OFST 0x00000830\n-/* hunta0,medforda0=pcie_pf_bar2 */\n+/* hunta0,medforda0,medford2a0=pf_dbell_bar */\n #define\tER_DZ_RX_DESC_UPD_REG_STEP 8192\n #define\tER_DZ_RX_DESC_UPD_REG_ROWS 2048\n #define\tER_DZ_RX_DESC_UPD_REG_RESET 0x0\n@@ -141,13 +229,74 @@ extern \"C\" {\n #define\tERF_DZ_RX_DESC_WPTR_LBN 0\n #define\tERF_DZ_RX_DESC_WPTR_WIDTH 12\n \n+\n+/*\n+ * RX_DESC_UPD_REG_64K(32bit):\n+ *\n+ */\n+\n+#define\tER_FZ_RX_DESC_UPD_REG_64K_OFST 0x00000830\n+/* medford2a0=pf_dbell_bar */\n+#define\tER_FZ_RX_DESC_UPD_REG_64K_STEP 65536\n+#define\tER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048\n+#define\tER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0\n+\n+\n+/* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */\n+/* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */\n+\n+\n+/*\n+ * TX_DESC_UPD_REG_64K(96bit):\n+ *\n+ */\n+\n+#define\tER_FZ_TX_DESC_UPD_REG_64K_OFST 0x00000a10\n+/* medford2a0=pf_dbell_bar */\n+#define\tER_FZ_TX_DESC_UPD_REG_64K_STEP 65536\n+#define\tER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048\n+#define\tER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0\n+\n+\n+#define\tERF_FZ_RSVD_LBN 76\n+#define\tERF_FZ_RSVD_WIDTH 20\n+#define\tERF_FZ_TX_DESC_WPTR_LBN 64\n+#define\tERF_FZ_TX_DESC_WPTR_WIDTH 12\n+#define\tERF_FZ_TX_DESC_HWORD_LBN 32\n+#define\tERF_FZ_TX_DESC_HWORD_WIDTH 32\n+#define\tERF_FZ_TX_DESC_LWORD_LBN 0\n+#define\tERF_FZ_TX_DESC_LWORD_WIDTH 32\n+\n+\n+/*\n+ * TX_DESC_UPD_REG_16K(96bit):\n+ *\n+ */\n+\n+#define\tER_FZ_TX_DESC_UPD_REG_16K_OFST 0x00000a10\n+/* medford2a0=pf_dbell_bar */\n+#define\tER_FZ_TX_DESC_UPD_REG_16K_STEP 16384\n+#define\tER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048\n+#define\tER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0\n+\n+\n+/* defined as ERF_FZ_RSVD_LBN 76; */\n+/* defined as ERF_FZ_RSVD_WIDTH 20 */\n+/* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */\n+/* defined as ERF_FZ_TX_DESC_WPTR_WIDTH 12 */\n+/* defined as ERF_FZ_TX_DESC_HWORD_LBN 32; */\n+/* defined as ERF_FZ_TX_DESC_HWORD_WIDTH 32 */\n+/* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */\n+/* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */\n+\n+\n /*\n * TX_DESC_UPD_REG(96bit):\n *\n */\n \n #define\tER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10\n-/* hunta0,medforda0=pcie_pf_bar2 */\n+/* hunta0,medforda0,medford2a0=pf_dbell_bar */\n #define\tER_DZ_TX_DESC_UPD_REG_STEP 8192\n #define\tER_DZ_TX_DESC_UPD_REG_ROWS 2048\n #define\tER_DZ_TX_DESC_UPD_REG_RESET 0x0\n@@ -233,16 +382,24 @@ extern \"C\" {\n #define\tESF_DZ_RX_EV_SOFT2_WIDTH 2\n #define\tESF_DZ_RX_DSC_PTR_LBITS_LBN 48\n #define\tESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4\n-#define\tESF_DZ_RX_L4_CLASS_LBN 45\n-#define\tESF_DZ_RX_L4_CLASS_WIDTH 3\n-#define\tESE_DZ_L4_CLASS_RSVD7 7\n-#define\tESE_DZ_L4_CLASS_RSVD6 6\n-#define\tESE_DZ_L4_CLASS_RSVD5 5\n-#define\tESE_DZ_L4_CLASS_RSVD4 4\n-#define\tESE_DZ_L4_CLASS_RSVD3 3\n-#define\tESE_DZ_L4_CLASS_UDP 2\n-#define\tESE_DZ_L4_CLASS_TCP 1\n-#define\tESE_DZ_L4_CLASS_UNKNOWN 0\n+#define\tESF_DE_RX_L4_CLASS_LBN 45\n+#define\tESF_DE_RX_L4_CLASS_WIDTH 3\n+#define\tESE_DE_L4_CLASS_RSVD7 7\n+#define\tESE_DE_L4_CLASS_RSVD6 6\n+#define\tESE_DE_L4_CLASS_RSVD5 5\n+#define\tESE_DE_L4_CLASS_RSVD4 4\n+#define\tESE_DE_L4_CLASS_RSVD3 3\n+#define\tESE_DE_L4_CLASS_UDP 2\n+#define\tESE_DE_L4_CLASS_TCP 1\n+#define\tESE_DE_L4_CLASS_UNKNOWN 0\n+#define\tESF_FZ_RX_FASTPD_INDCTR_LBN 47\n+#define\tESF_FZ_RX_FASTPD_INDCTR_WIDTH 1\n+#define\tESF_FZ_RX_L4_CLASS_LBN 45\n+#define\tESF_FZ_RX_L4_CLASS_WIDTH 2\n+#define\tESE_FZ_L4_CLASS_RSVD3 3\n+#define\tESE_FZ_L4_CLASS_UDP 2\n+#define\tESE_FZ_L4_CLASS_TCP 1\n+#define\tESE_FZ_L4_CLASS_UNKNOWN 0\n #define\tESF_DZ_RX_L3_CLASS_LBN 42\n #define\tESF_DZ_RX_L3_CLASS_WIDTH 3\n #define\tESE_DZ_L3_CLASS_RSVD7 7\n@@ -419,6 +576,8 @@ extern \"C\" {\n #define\tESE_DZ_TX_OPTION_DESC_CRC_CSUM 0\n #define\tESF_DZ_TX_TSO_OPTION_TYPE_LBN 56\n #define\tESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4\n+#define\tESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3\n+#define\tESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2\n #define\tESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1\n #define\tESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0\n #define\tESF_DZ_TX_TSO_TCP_FLAGS_LBN 48\n@@ -429,7 +588,7 @@ extern \"C\" {\n #define\tESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32\n \n \n-/* TX_TSO_FATSO2A_DESC */\n+/* ES_TX_TSO_V2_DESC_A */\n #define\tESF_DZ_TX_DESC_IS_OPT_LBN 63\n #define\tESF_DZ_TX_DESC_IS_OPT_WIDTH 1\n #define\tESF_DZ_TX_OPTION_TYPE_LBN 60\n@@ -449,7 +608,7 @@ extern \"C\" {\n #define\tESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32\n \n \n-/* TX_TSO_FATSO2B_DESC */\n+/* ES_TX_TSO_V2_DESC_B */\n #define\tESF_DZ_TX_DESC_IS_OPT_LBN 63\n #define\tESF_DZ_TX_DESC_IS_OPT_WIDTH 1\n #define\tESF_DZ_TX_OPTION_TYPE_LBN 60\n@@ -463,12 +622,10 @@ extern \"C\" {\n #define\tESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2\n #define\tESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1\n #define\tESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0\n-#define\tESF_DZ_TX_TSO_OUTER_IP_ID_LBN 16\n-#define\tESF_DZ_TX_TSO_OUTER_IP_ID_WIDTH 16\n #define\tESF_DZ_TX_TSO_TCP_MSS_LBN 32\n #define\tESF_DZ_TX_TSO_TCP_MSS_WIDTH 16\n-#define\tESF_DZ_TX_TSO_INNER_PE_CSUM_LBN 0\n-#define\tESF_DZ_TX_TSO_INNER_PE_CSUM_WIDTH 16\n+#define\tESF_DZ_TX_TSO_OUTER_IPID_LBN 0\n+#define\tESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16\n \n \n /* ES_TX_VLAN_DESC */\ndiff --git a/drivers/net/sfc/sfc_ef10_rx.c b/drivers/net/sfc/sfc_ef10_rx.c\nindex 0b3e8fb..f31a7e0 100644\n--- a/drivers/net/sfc/sfc_ef10_rx.c\n+++ b/drivers/net/sfc/sfc_ef10_rx.c\n@@ -325,22 +325,32 @@ sfc_ef10_rx_ev_to_offloads(struct sfc_ef10_rxq *rxq, const efx_qword_t rx_ev,\n \t\tSFC_ASSERT(false);\n \t}\n \n-\tswitch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L4_CLASS)) {\n-\tcase ESE_DZ_L4_CLASS_TCP:\n+\t/*\n+\t * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only\n+\t * 2 bits wide on Medford2. Check it is safe to use the Medford2 field\n+\t * and values for all EF10 controllers.\n+\t */\n+\tRTE_BUILD_BUG_ON(ESF_FZ_RX_L4_CLASS_LBN != ESF_DE_RX_L4_CLASS_LBN);\n+\tswitch (EFX_QWORD_FIELD(rx_ev, ESF_FZ_RX_L4_CLASS)) {\n+\tcase ESE_FZ_L4_CLASS_TCP:\n+\t\t RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_TCP != ESE_DE_L4_CLASS_TCP);\n \t\tl4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP :\n \t\t\tRTE_PTYPE_INNER_L4_TCP;\n \t\tol_flags |=\n \t\t\t(EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?\n \t\t\tPKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;\n \t\tbreak;\n-\tcase ESE_DZ_L4_CLASS_UDP:\n+\tcase ESE_FZ_L4_CLASS_UDP:\n+\t\t RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UDP != ESE_DE_L4_CLASS_UDP);\n \t\tl4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP :\n \t\t\tRTE_PTYPE_INNER_L4_UDP;\n \t\tol_flags |=\n \t\t\t(EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?\n \t\t\tPKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;\n \t\tbreak;\n-\tcase ESE_DZ_L4_CLASS_UNKNOWN:\n+\tcase ESE_FZ_L4_CLASS_UNKNOWN:\n+\t\t RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UNKNOWN !=\n+\t\t\t\t ESE_DE_L4_CLASS_UNKNOWN);\n \t\tbreak;\n \tdefault:\n \t\t/* Unexpected Layer 4 class */\n", "prefixes": [ "dpdk-dev", "26/80" ] }