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GET /api/patches/35206/?format=api
{ "id": 35206, "url": "http://patches.dpdk.org/api/patches/35206/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180216213700.3415-7-pbhagavatula@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180216213700.3415-7-pbhagavatula@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180216213700.3415-7-pbhagavatula@caviumnetworks.com", "date": "2018-02-16T21:36:56", "name": "[dpdk-dev,06/10] event/octeontx: add single producer timer arm variant", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1260a146418d693010f61c1c1c9a19b90ca614f3", "submitter": { "id": 768, "url": "http://patches.dpdk.org/api/people/768/?format=api", "name": "Pavan Nikhilesh", "email": "pbhagavatula@caviumnetworks.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180216213700.3415-7-pbhagavatula@caviumnetworks.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/35206/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/35206/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CAEFC1B31E;\n\tFri, 16 Feb 2018 22:37:51 +0100 (CET)", "from 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)\n\tsmtp.mailfrom=Pavan.Bhagavatula@cavium.com; ", "From": "Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>", "To": "jerin.jacob@caviumnetworks.com, santosh.shukla@caviumnetworks.com,\n\terik.g.carrillo@intel.com", "Cc": "dev@dpdk.org,\n\tPavan Nikhilesh <pbhagavatula@caviumnetworks.com>", "Date": "Sat, 17 Feb 2018 03:06:56 +0530", "Message-Id": "<20180216213700.3415-7-pbhagavatula@caviumnetworks.com>", "X-Mailer": "git-send-email 2.16.1", "In-Reply-To": "<20180216213700.3415-1-pbhagavatula@caviumnetworks.com>", "References": "<20180216213700.3415-1-pbhagavatula@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[111.93.218.67]", "X-ClientProxiedBy": "SG2PR01CA0090.apcprd01.prod.exchangelabs.com\n\t(2603:1096:3:15::16) To DM5PR07MB3467.namprd07.prod.outlook.com\n\t(2603:10b6:4:67::22)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "519cdb1f-d401-4f7e-a915-08d57585862b", "X-Microsoft-Antispam": "UriScan:; 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"SFV:NSPM;\n\tSFS:(10009020)(6069001)(346002)(366004)(396003)(39860400002)(39380400002)(376002)(189003)(199004)(6486002)(25786009)(2950100002)(386003)(6506007)(53936002)(42882006)(5009440100003)(4326008)(107886003)(6666003)(59450400001)(6512007)(16586007)(106356001)(316002)(105586002)(36756003)(478600001)(2906002)(47776003)(6116002)(76176011)(3846002)(1076002)(97736004)(66066001)(8676002)(51416003)(50466002)(48376002)(81156014)(5660300001)(68736007)(8936002)(575784001)(52116002)(16526019)(26005)(305945005)(1857600001)(72206003)(81166006)(50226002)(7736002)(42262002);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR07MB3467; H:localhost.localdomain;\n\tFPR:; \n\tSPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Feb 2018 21:37:46.6464\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "519cdb1f-d401-4f7e-a915-08d57585862b", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR07MB3467", "Subject": "[dpdk-dev] [PATCH 06/10] event/octeontx: add single producer timer\n\tarm variant", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When application creates the timer adapter by passing\n`RTE_EVENT_TIMER_ADAPTER_F_SP_PUT` flag, we can optimize the arm sequence\nby removing the locking overhead.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>\n---\n drivers/event/octeontx/timvf_evdev.c | 22 +++-\n drivers/event/octeontx/timvf_evdev.h | 5 +\n drivers/event/octeontx/timvf_worker.c | 65 ++++++++++++\n drivers/event/octeontx/timvf_worker.h | 183 ++++++++++++++++++++++++++++++++++\n 4 files changed, 270 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/event/octeontx/timvf_evdev.c b/drivers/event/octeontx/timvf_evdev.c\nindex d0ba42263..6cf5d4846 100644\n--- a/drivers/event/octeontx/timvf_evdev.c\n+++ b/drivers/event/octeontx/timvf_evdev.c\n@@ -174,6 +174,7 @@ timvf_ring_create(struct rte_event_timer_adapter *adptr)\n \tstruct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;\n \tstruct timvf_ring *timr;\n \tstruct octeontx_timvf_info tinfo;\n+\tunsigned int mp_flags = 0;\n \n \tif (octeontx_timvf_info(&tinfo) < 0)\n \t\treturn -ENODEV;\n@@ -224,6 +225,11 @@ timvf_ring_create(struct rte_event_timer_adapter *adptr)\n \n \ttimr->nb_chunks = nb_timers / nb_chunk_slots;\n \n+\tif (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {\n+\t\tmp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;\n+\t\ttimvf_log_info(\"Using single producer mode\");\n+\t}\n+\n \ttimr->meta.bkt = rte_zmalloc(\"octeontx_timvf_bucket\",\n \t\t\t(timr->meta.nb_bkts) * sizeof(struct tim_mem_bucket),\n \t\t\t0);\n@@ -261,8 +267,12 @@ timvf_ring_create(struct rte_event_timer_adapter *adptr)\n \ttimvf_write64(0x7, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_ENA_W1C);\n \ttimvf_write64(0x7, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_ENA_W1S);\n \n-\tadptr->arm_burst = timvf_timer_reg_burst_mp;\n-\tadptr->arm_tmo_tick_burst = NULL;\n+\tif (mp_flags)\n+\t\tadptr->arm_burst = timvf_timer_reg_burst_sp;\n+\telse\n+\t\tadptr->arm_burst = timvf_timer_reg_burst_mp;\n+\n+\tadptr->arm_tmo_tick_burst = timvf_timer_reg_brst;\n \tadptr->cancel_burst = timvf_timer_unreg_burst;\n \n \treturn 0;\n@@ -297,11 +307,13 @@ timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n \t\tuint32_t *caps, const struct rte_event_timer_adapter_ops **ops)\n {\n \tRTE_SET_USED(dev);\n-\tRTE_SET_USED(flags);\n \n-\ttimvf_ops.arm_burst = timvf_timer_reg_burst_mp;\n-\ttimvf_ops.arm_tmo_tick_burst = NULL;\n+\tif (flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT)\n+\t\ttimvf_ops.arm_burst = timvf_timer_reg_burst_sp;\n+\telse\n+\t\ttimvf_ops.arm_burst = timvf_timer_reg_burst_mp;\n \n+\ttimvf_ops.arm_tmo_tick_burst = timvf_timer_reg_brst;\n \ttimvf_ops.cancel_burst = timvf_timer_unreg_burst;\n \t*caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;\n \t*ops = &timvf_ops;\ndiff --git a/drivers/event/octeontx/timvf_evdev.h b/drivers/event/octeontx/timvf_evdev.h\nindex c80e147e8..b5db233bb 100644\n--- a/drivers/event/octeontx/timvf_evdev.h\n+++ b/drivers/event/octeontx/timvf_evdev.h\n@@ -186,8 +186,13 @@ bkt_mod(uint32_t rel_bkt, uint32_t nb_bkts)\n \n int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n \t\tuint32_t *caps, const struct rte_event_timer_adapter_ops **ops);\n+int timvf_timer_reg_brst(const struct rte_event_timer_adapter *adptr,\n+\t\tstruct rte_event_timer **tim, const uint64_t timeout_tick,\n+\t\tconst uint16_t nb_timers);\n int timvf_timer_unreg_burst(const struct rte_event_timer_adapter *adptr,\n \t\tstruct rte_event_timer **tim, const uint16_t nb_timers);\n+int timvf_timer_reg_burst_sp(const struct rte_event_timer_adapter *adptr,\n+\t\tstruct rte_event_timer **tim, const uint16_t nb_timers);\n int timvf_timer_reg_burst_mp(const struct rte_event_timer_adapter *adptr,\n \t\tstruct rte_event_timer **tim, const uint16_t nb_timers);\n \ndiff --git a/drivers/event/octeontx/timvf_worker.c b/drivers/event/octeontx/timvf_worker.c\nindex 7a924fd11..3e48f3ca6 100644\n--- a/drivers/event/octeontx/timvf_worker.c\n+++ b/drivers/event/octeontx/timvf_worker.c\n@@ -5,6 +5,42 @@\n \n #include \"timvf_worker.h\"\n \n+int\n+timvf_timer_reg_brst(const struct rte_event_timer_adapter *adptr,\n+\t\tstruct rte_event_timer **tim, const uint64_t timeout_tick,\n+\t\tconst uint16_t nb_timers)\n+{\n+\tint ret;\n+\tuint16_t set_timers = 0;\n+\tuint16_t idx;\n+\tuint16_t arr_idx = 0;\n+\tstruct timvf_ring *timr = adptr->data->adapter_priv;\n+\tstruct tim_mem_entry entry[TIMVF_MAX_BURST] __rte_cache_aligned;\n+\n+\tif (unlikely(timeout_tick > timr->meta.nb_bkts)) {\n+\t\tfor (idx = 0; idx < nb_timers; idx++)\n+\t\t\ttim[idx]->state = RTE_EVENT_TIMER_ERROR_TOOLATE;\n+\t\trte_errno = -EINVAL;\n+\t\treturn 0;\n+\t}\n+\n+\twhile (arr_idx < nb_timers) {\n+\t\tfor (idx = 0; idx < TIMVF_MAX_BURST && (arr_idx < nb_timers);\n+\t\t\t\tidx++, arr_idx++) {\n+\t\t\tentry[idx].w0 =\n+\t\t\t\t(tim[arr_idx]->ev.event & 0xFFC000000000) >> 6 |\n+\t\t\t\t(tim[arr_idx]->ev.event & 0xFFFFFFFF);\n+\t\t\tentry[idx].wqe = tim[arr_idx]->ev.u64;\n+\t\t}\n+\t\tret = timvf_add_entry_brst(timr, timeout_tick, &tim[set_timers],\n+\t\t\t\tentry, idx);\n+\t\tset_timers += ret;\n+\t\tif (ret != idx)\n+\t\t\tbreak;\n+\t}\n+\treturn set_timers;\n+}\n+\n int\n timvf_timer_unreg_burst(const struct rte_event_timer_adapter *adptr,\n \t\tstruct rte_event_timer **tim, const uint16_t nb_timers)\n@@ -23,6 +59,35 @@ timvf_timer_unreg_burst(const struct rte_event_timer_adapter *adptr,\n \treturn index;\n }\n \n+int\n+timvf_timer_reg_burst_sp(const struct rte_event_timer_adapter *adptr,\n+\t\tstruct rte_event_timer **tim, const uint16_t nb_timers)\n+{\n+\tint ret;\n+\tuint16_t index;\n+\tstruct tim_mem_entry entry;\n+\tstruct timvf_ring *timr = adptr->data->adapter_priv;\n+\tfor (index = 0; index < nb_timers; index++) {\n+\t\tif (unlikely(tim[index]->timeout_ticks > timr->meta.nb_bkts)) {\n+\t\t\ttim[index]->state = RTE_EVENT_TIMER_ERROR_TOOLATE;\n+\t\t\trte_errno = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tentry.w0 = (tim[index]->ev.event & 0xFFC000000000) >> 6 |\n+\t\t\t(tim[index]->ev.event & 0xFFFFFFFF);\n+\t\tentry.wqe = tim[index]->ev.u64;\n+\t\tret = timvf_add_entry_sp(timr, tim[index]->timeout_ticks,\n+\t\t\t\ttim[index], &entry);\n+\t\tif (unlikely(ret)) {\n+\t\t\trte_errno = -ret;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn index;\n+}\n+\n int\n timvf_timer_reg_burst_mp(const struct rte_event_timer_adapter *adptr,\n \t\tstruct rte_event_timer **tim, const uint16_t nb_timers)\ndiff --git a/drivers/event/octeontx/timvf_worker.h b/drivers/event/octeontx/timvf_worker.h\nindex b63dd763c..320eb6ac1 100644\n--- a/drivers/event/octeontx/timvf_worker.h\n+++ b/drivers/event/octeontx/timvf_worker.h\n@@ -160,6 +160,118 @@ timr_clr_bkt(struct timvf_ring *timr, struct tim_mem_bucket *bkt)\n \treturn (struct tim_mem_entry *)bkt->first_chunk;\n }\n \n+/* Burst mode functions */\n+static inline int __hot\n+timvf_add_entry_brst(struct timvf_ring *timr, const uint16_t rel_bkt,\n+\t\tstruct rte_event_timer **tim, const struct tim_mem_entry *ents,\n+\t\tconst uint16_t nb_timers)\n+{\n+\tint16_t rem;\n+\tint16_t crem = 0;\n+\tuint8_t lock_cnt;\n+\tuint16_t index = 0;\n+\tuint16_t chunk_remainder = 0;\n+\tuint32_t bucket;\n+\tuint32_t tbkt_id;\n+\tconst uint32_t nb_bkts = timr->meta.nb_bkts;\n+\tconst uint64_t start = timr->meta.ring_start_cyc;\n+\tuint64_t pos_reg;\n+\tuint64_t lock_sema;\n+\tstruct tim_mem_bucket *bkt;\n+\tstruct tim_mem_entry *chunk;\n+\n+__retry:\n+\tpos_reg = (rte_rdtsc() - start);\n+\tbucket = rte_reciprocal_divide_u64(pos_reg,\n+\t\t\t&timr->meta.fast_div) + rel_bkt;\n+\ttbkt_id = timr->meta.get_target_bkt(bucket, nb_bkts);\n+\tbkt = &timr->meta.bkt[tbkt_id];\n+\n+\t/* Only one thread beyond this. */\n+\tlock_sema = timr_bkt_inc_lock(bkt);\n+\tlock_cnt = (uint8_t)\n+\t\t((lock_sema >> TIM_BUCKET_W1_S_LOCK) & TIM_BUCKET_W1_M_LOCK);\n+\n+\tif (lock_cnt) {\n+\t\ttimr_bkt_dec_lock(bkt);\n+\t\tgoto __retry;\n+\t}\n+\n+\t/* Bucket related checks. */\n+\tif (unlikely(timr_bkt_get_shbt(lock_sema))) {\n+\t\ttimr_bkt_dec_lock(bkt);\n+\t\tgoto __retry;\n+\t}\n+\n+\tchunk_remainder = timr_bkt_fetch_rem(lock_sema);\n+\trem = chunk_remainder - nb_timers;\n+\tif (rem < 0) {\n+\t\tcrem = nb_chunk_slots - chunk_remainder;\n+\t\tif (chunk_remainder && crem) {\n+\t\t\tchunk = ((struct tim_mem_entry *)bkt->current_chunk) +\n+\t\t\t\tcrem;\n+\t\t\tfor (; index < chunk_remainder; index++) {\n+\t\t\t\t*chunk = *(ents + index);\n+\t\t\t\ttim[index]->impl_opaque[0] = (uint64_t)chunk++;\n+\t\t\t\ttim[index]->impl_opaque[1] = (uint64_t)bkt;\n+\t\t\t\ttim[index]->state = RTE_EVENT_TIMER_ARMED;\n+\t\t\t}\n+\t\t\ttimr_bkt_sub_rem(bkt, chunk_remainder);\n+\t\t\ttimr_bkt_add_nent(bkt, chunk_remainder);\n+\t\t}\n+\t\trem = nb_timers - chunk_remainder;\n+\t\tents = ents + chunk_remainder;\n+\t\tif (bkt->nb_entry || !bkt->first_chunk) {\n+\t\t\tif (unlikely(rte_mempool_get(timr->meta.chunk_pool,\n+\t\t\t\t\t\t\t(void **)&chunk))) {\n+\t\t\t\t/*\n+\t\t\t\t * No more chunks, return number of entries\n+\t\t\t\t * successfully copied.\n+\t\t\t\t */\n+\t\t\t\ttimr_bkt_dec_lock(bkt);\n+\t\t\t\trte_errno = -ENOMEM;\n+\t\t\t\ttim[index]->state = RTE_EVENT_TIMER_ERROR;\n+\t\t\t\treturn crem;\n+\t\t\t}\n+\t\t\tif (bkt->nb_entry) {\n+\t\t\t\t*(uint64_t *)(\n+\t\t\t\t(struct tim_mem_entry *)bkt->current_chunk +\n+\t\t\t\t\tnb_chunk_slots) = (uint64_t) chunk;\n+\t\t\t} else {\n+\t\t\t\tbkt->first_chunk = (uint64_t) chunk;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tchunk = timr_clr_bkt(timr, bkt);\n+\t\t\tbkt->first_chunk = (uint64_t) chunk;\n+\t\t}\n+\t\t*(uint64_t *)(chunk + nb_chunk_slots) = 0;\n+\t\tbkt->current_chunk = (uint64_t) chunk;\n+\n+\t\tfor (; index < nb_timers; index++) {\n+\t\t\t*chunk = *(ents + index);\n+\t\t\ttim[index]->impl_opaque[0] = (uint64_t)chunk++;\n+\t\t\ttim[index]->impl_opaque[1] = (uint64_t)bkt;\n+\t\t\ttim[index]->state = RTE_EVENT_TIMER_ARMED;\n+\t\t}\n+\t\ttimr_bkt_set_rem(bkt, nb_chunk_slots - rem);\n+\t\ttimr_bkt_add_nent(bkt, rem);\n+\t} else {\n+\t\tchunk = (struct tim_mem_entry *)bkt->current_chunk;\n+\t\tchunk += (nb_chunk_slots - chunk_remainder);\n+\t\tfor (; index < nb_timers; index++) {\n+\t\t\t*chunk = *(ents + index);\n+\t\t\ttim[index]->impl_opaque[0] = (uint64_t)chunk++;\n+\t\t\ttim[index]->impl_opaque[1] = (uint64_t)bkt;\n+\t\t\ttim[index]->state = RTE_EVENT_TIMER_ARMED;\n+\t\t}\n+\t\ttimr_bkt_sub_rem(bkt, nb_timers);\n+\t\ttimr_bkt_add_nent(bkt, nb_timers);\n+\t}\n+\n+\ttimr_bkt_dec_lock(bkt);\n+\treturn nb_timers;\n+}\n+\n static inline int __hot\n timvf_rem_entry(struct rte_event_timer *tim)\n {\n@@ -192,6 +304,77 @@ timvf_rem_entry(struct rte_event_timer *tim)\n \treturn 0;\n }\n \n+/* Single producer functions. */\n+static inline int __hot\n+timvf_add_entry_sp(struct timvf_ring *timr, const uint32_t rel_bkt,\n+\t\tstruct rte_event_timer *tim, const struct tim_mem_entry *pent)\n+{\n+\tint16_t rem;\n+\tuint32_t bucket;\n+\tuint32_t tbkt_id;\n+\tconst uint32_t nb_bkts = timr->meta.nb_bkts;\n+\tuint64_t lock_sema;\n+\tuint64_t pos_reg;\n+\tconst uint64_t start = timr->meta.ring_start_cyc;\n+\tstruct tim_mem_bucket *bkt;\n+\tstruct tim_mem_entry *chunk;\n+\n+\tpos_reg = (rte_rdtsc() - start);\n+\tbucket = rte_reciprocal_divide_u64(pos_reg,\n+\t\t\t&timr->meta.fast_div) + rel_bkt;\n+\ttbkt_id = timr->meta.get_target_bkt(bucket, nb_bkts);\n+\tbkt = &timr->meta.bkt[tbkt_id];\n+__retry:\n+\t/*Get Bucket sema*/\n+\tlock_sema = timr_bkt_fetch_sema(bkt);\n+\t/* Bucket related checks. */\n+\tif (unlikely(timr_bkt_get_shbt(lock_sema)))\n+\t\tgoto __retry;\n+\n+\t/* Insert the work. */\n+\trem = timr_bkt_fetch_rem(lock_sema);\n+\n+\tif (!rem) {\n+\t\t/* SP mode will have only one thread. */\n+\t\tif (bkt->nb_entry || !bkt->first_chunk) {\n+\t\t\tif (unlikely(rte_mempool_get(timr->meta.chunk_pool,\n+\t\t\t\t\t\t\t(void **)&chunk))) {\n+\t\t\t\ttimr_bkt_set_rem(bkt, 0);\n+\t\t\t\ttim->impl_opaque[0] =\n+\t\t\t\t\ttim->impl_opaque[1] = 0;\n+\t\t\t\ttim->state = RTE_EVENT_TIMER_ERROR;\n+\t\t\t\treturn -ENOMEM;\n+\t\t\t}\n+\t\t\tif (bkt->nb_entry) {\n+\t\t\t\t*(uint64_t *)((struct tim_mem_entry *)\n+\t\t\t\t\t\tbkt->current_chunk +\n+\t\t\t\t\t\tnb_chunk_slots) =\n+\t\t\t\t\t(uint64_t) chunk;\n+\t\t\t} else {\n+\t\t\t\tbkt->first_chunk = (uint64_t) chunk;\n+\t\t\t}\n+\t\t\t*(uint64_t *)(chunk + nb_chunk_slots) = 0;\n+\t\t} else {\n+\t\t\tchunk = timr_clr_bkt(timr, bkt);\n+\t\t\t*(uint64_t *)(chunk + nb_chunk_slots) = 0;\n+\t\t\tbkt->first_chunk = (uint64_t) chunk;\n+\t\t}\n+\t\tbkt->current_chunk = (uint64_t) chunk;\n+\t\ttimr_bkt_set_rem(bkt, nb_chunk_slots - 1);\n+\t} else {\n+\t\tchunk = (struct tim_mem_entry *)bkt->current_chunk;\n+\t\tchunk += nb_chunk_slots - rem;\n+\t}\n+\t/* Copy work entry. */\n+\t*chunk = *pent;\n+\ttimr_bkt_inc_nent(bkt);\n+\n+\ttim->impl_opaque[0] = (uint64_t)chunk;\n+\ttim->impl_opaque[1] = (uint64_t)bkt;\n+\ttim->state = RTE_EVENT_TIMER_ARMED;\n+\treturn 0;\n+}\n+\n /* Multi producer functions. */\n static inline int __hot\n timvf_add_entry_mp(struct timvf_ring *timr, const uint32_t rel_bkt,\n", "prefixes": [ "dpdk-dev", "06/10" ] }