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GET /api/patches/35203/?format=api
{ "id": 35203, "url": "http://patches.dpdk.org/api/patches/35203/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180216213700.3415-4-pbhagavatula@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180216213700.3415-4-pbhagavatula@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180216213700.3415-4-pbhagavatula@caviumnetworks.com", "date": "2018-02-16T21:36:53", "name": "[dpdk-dev,03/10] event/octeontx: add support to create and free timer adapter", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "38bdc976bfbc884f0a69451aa3c0814c2bab6e98", "submitter": { "id": 768, "url": "http://patches.dpdk.org/api/people/768/?format=api", "name": "Pavan Nikhilesh", "email": "pbhagavatula@caviumnetworks.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180216213700.3415-4-pbhagavatula@caviumnetworks.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/35203/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/35203/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 16A1F1B2A7;\n\tFri, 16 Feb 2018 22:37:45 +0100 (CET)", "from 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)\n\tsmtp.mailfrom=Pavan.Bhagavatula@cavium.com; ", "From": "Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>", "To": "jerin.jacob@caviumnetworks.com, santosh.shukla@caviumnetworks.com,\n\terik.g.carrillo@intel.com", "Cc": "dev@dpdk.org,\n\tPavan Nikhilesh <pbhagavatula@caviumnetworks.com>", "Date": "Sat, 17 Feb 2018 03:06:53 +0530", "Message-Id": "<20180216213700.3415-4-pbhagavatula@caviumnetworks.com>", "X-Mailer": "git-send-email 2.16.1", "In-Reply-To": "<20180216213700.3415-1-pbhagavatula@caviumnetworks.com>", "References": "<20180216213700.3415-1-pbhagavatula@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[111.93.218.67]", "X-ClientProxiedBy": "SG2PR01CA0090.apcprd01.prod.exchangelabs.com\n\t(2603:1096:3:15::16) To DM5PR07MB3467.namprd07.prod.outlook.com\n\t(2603:10b6:4:67::22)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "1167decd-2390-4446-15cf-08d5758581ea", "X-Microsoft-Antispam": "UriScan:; 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"SFV:NSPM;\n\tSFS:(10009020)(6069001)(346002)(366004)(396003)(39860400002)(39380400002)(376002)(189003)(199004)(6486002)(25786009)(2950100002)(386003)(6506007)(53936002)(42882006)(5009440100003)(4326008)(107886003)(6666003)(59450400001)(6512007)(16586007)(106356001)(316002)(105586002)(36756003)(478600001)(2906002)(47776003)(6116002)(76176011)(3846002)(1076002)(97736004)(66066001)(8676002)(51416003)(50466002)(48376002)(81156014)(5660300001)(68736007)(8936002)(52116002)(16526019)(26005)(305945005)(1857600001)(72206003)(81166006)(50226002)(7736002)(42262002);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR07MB3467; H:localhost.localdomain;\n\tFPR:; \n\tSPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Feb 2018 21:37:39.4901\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "1167decd-2390-4446-15cf-08d5758581ea", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR07MB3467", "Subject": "[dpdk-dev] [PATCH 03/10] event/octeontx: add support to create and\n\tfree timer adapter", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When the application requests to create a timer device, Octeontx TIM\ncreate does the following:\n- Get the requested TIMvf ring based on adapter_id.\n- Verify the config parameters supplied.\n- Allocate memory required for\n * Buckets based on min and max timeout supplied.\n * Allocate the chunk pool based on the number of timers.\n- Clear the interrupts.\n\nOn Free:\n- Free the allocated bucket and chunk memory.\n- Free private data used by TIMvf.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>\n---\n drivers/event/octeontx/Makefile | 1 +\n drivers/event/octeontx/meson.build | 3 +-\n drivers/event/octeontx/ssovf_evdev.c | 3 +\n drivers/event/octeontx/timvf_evdev.c | 160 +++++++++++++++++++++++++++++++++++\n drivers/event/octeontx/timvf_evdev.h | 158 ++++++++++++++++++++++++++++++++++\n 5 files changed, 324 insertions(+), 1 deletion(-)\n create mode 100644 drivers/event/octeontx/timvf_evdev.c\n create mode 100644 drivers/event/octeontx/timvf_evdev.h", "diff": "diff --git a/drivers/event/octeontx/Makefile b/drivers/event/octeontx/Makefile\nindex 0e49efd84..f1d10a99e 100644\n--- a/drivers/event/octeontx/Makefile\n+++ b/drivers/event/octeontx/Makefile\n@@ -27,6 +27,7 @@ LIBABIVER := 1\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_worker.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_evdev.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_evdev_selftest.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += timvf_evdev.c\n \n ifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\n CFLAGS_ssovf_worker.o += -fno-prefetch-loop-arrays\ndiff --git a/drivers/event/octeontx/meson.build b/drivers/event/octeontx/meson.build\nindex 358fc9fc9..8941f8a56 100644\n--- a/drivers/event/octeontx/meson.build\n+++ b/drivers/event/octeontx/meson.build\n@@ -3,7 +3,8 @@\n \n sources = files('ssovf_worker.c',\n \t\t'ssovf_evdev.c',\n-\t\t'ssovf_evdev_selftest.c'\n+\t\t'ssovf_evdev_selftest.c',\n+\t\t'timvf_evdev.c',\n )\n \n deps += ['mempool_octeontx', 'bus_vdev', 'pmd_octeontx']\ndiff --git a/drivers/event/octeontx/ssovf_evdev.c b/drivers/event/octeontx/ssovf_evdev.c\nindex a1086077d..54384d465 100644\n--- a/drivers/event/octeontx/ssovf_evdev.c\n+++ b/drivers/event/octeontx/ssovf_evdev.c\n@@ -18,6 +18,7 @@\n #include <rte_bus_vdev.h>\n \n #include \"ssovf_evdev.h\"\n+#include \"timvf_evdev.h\"\n \n int otx_logtype_ssovf;\n \n@@ -610,6 +611,8 @@ static const struct rte_eventdev_ops ssovf_ops = {\n \t.eth_rx_adapter_start = ssovf_eth_rx_adapter_start,\n \t.eth_rx_adapter_stop = ssovf_eth_rx_adapter_stop,\n \n+\t.timer_adapter_caps_get = timvf_timer_adapter_caps_get,\n+\n \t.dev_selftest = test_eventdev_octeontx,\n \n \t.dump = ssovf_dump,\ndiff --git a/drivers/event/octeontx/timvf_evdev.c b/drivers/event/octeontx/timvf_evdev.c\nnew file mode 100644\nindex 000000000..a56ca7e71\n--- /dev/null\n+++ b/drivers/event/octeontx/timvf_evdev.c\n@@ -0,0 +1,160 @@\n+/*\n+ * SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#include \"timvf_evdev.h\"\n+\n+int otx_logtype_timvf;\n+\n+RTE_INIT(otx_timvf_init_log);\n+static void\n+otx_timvf_init_log(void)\n+{\n+\totx_logtype_timvf = rte_log_register(\"pmd.event.octeontx.timer\");\n+\tif (otx_logtype_timvf >= 0)\n+\t\trte_log_set_level(otx_logtype_timvf, RTE_LOG_NOTICE);\n+}\n+\n+static void\n+timvf_ring_info_get(const struct rte_event_timer_adapter *adptr,\n+\t\tstruct rte_event_timer_adapter_info *adptr_info)\n+{\n+\tstruct timvf_ring *timr = adptr->data->adapter_priv;\n+\tadptr_info->max_tmo_ns = timr->max_tout;\n+\tadptr_info->min_resolution_ns = timr->tck_nsec;\n+\trte_memcpy(&adptr_info->conf, &adptr->data->conf,\n+\t\t\tsizeof(struct rte_event_timer_adapter_conf));\n+}\n+\n+static int\n+timvf_ring_create(struct rte_event_timer_adapter *adptr)\n+{\n+\tchar pool_name[25];\n+\tint ret;\n+\tuint64_t nb_timers;\n+\tstruct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;\n+\tstruct timvf_ring *timr;\n+\tstruct octeontx_timvf_info tinfo;\n+\n+\tif (octeontx_timvf_info(&tinfo) < 0)\n+\t\treturn -ENODEV;\n+\n+\tif (adptr->data->id >= tinfo.total_timvfs)\n+\t\treturn -ENODEV;\n+\n+\ttimr = rte_zmalloc(\"octeontx_timvf_priv\",\n+\t\t\tsizeof(struct timvf_ring), 0);\n+\tif (timr == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tadptr->data->adapter_priv = timr;\n+\t/* Check config parameters. */\n+\tif ((rcfg->clk_src != RTE_EVENT_TIMER_ADAPTER_EXT_CLK0) &&\n+\t\t\t(!rcfg->timer_tick_ns ||\n+\t\t\t rcfg->timer_tick_ns < TIM_MIN_INTERVAL)) {\n+\t\ttimvf_log_err(\"Too low timer ticks\");\n+\t\tgoto cfg_err;\n+\t}\n+\n+\tswitch (rcfg->clk_src) {\n+\tcase RTE_EVENT_TIMER_ADAPTER_CPU_CLK:\n+\t\ttimr->clk_src = TIM_CLK_SRC_SCLK;\n+\t\tbreak;\n+\tcase RTE_EVENT_TIMER_ADAPTER_EXT_CLK0:\n+\t\ttimr->clk_src = TIM_CLK_SRC_GPIO;\n+\t\tbreak;\n+\tcase RTE_EVENT_TIMER_ADAPTER_EXT_CLK1:\n+\t\ttimr->clk_src = TIM_CLK_SRC_GTI;\n+\t\tbreak;\n+\tcase RTE_EVENT_TIMER_ADAPTER_EXT_CLK2:\n+\t\ttimr->clk_src = TIM_CLK_SRC_PTP;\n+\t\tbreak;\n+\tdefault:\n+\t\ttimvf_log_err(\"Invalid clk source specified.\");\n+\t\tgoto cfg_err;\n+\t}\n+\n+\ttimr->tim_ring_id = adptr->data->id;\n+\ttimr->tck_nsec = rcfg->timer_tick_ns;\n+\ttimr->max_tout = rcfg->max_tmo_ns;\n+\ttimr->meta.nb_bkts = (timr->max_tout / timr->tck_nsec) + 1;\n+\ttimr->vbar0 = octeontx_timvf_bar(timr->tim_ring_id, 0);\n+\ttimr->bkt_pos = (uint8_t *)timr->vbar0 + TIM_VRING_REL;\n+\tnb_timers = rcfg->nb_timers;\n+\ttimr->meta.get_target_bkt = bkt_mod;\n+\n+\ttimr->nb_chunks = nb_timers / nb_chunk_slots;\n+\n+\ttimr->meta.bkt = rte_zmalloc(\"octeontx_timvf_bucket\",\n+\t\t\t(timr->meta.nb_bkts) * sizeof(struct tim_mem_bucket),\n+\t\t\t0);\n+\tif (timr->meta.bkt == NULL)\n+\t\tgoto mem_err;\n+\n+\tsnprintf(pool_name, 30, \"timvf_meta.chunk_pool%d\", timr->tim_ring_id);\n+\ttimr->meta.chunk_pool = (void *)rte_mempool_create_empty(pool_name,\n+\t\t\ttimr->nb_chunks, TIM_CHUNK_SIZE, 0, 0, rte_socket_id(),\n+\t\t\t0);\n+\n+\tif (!timr->meta.chunk_pool) {\n+\t\trte_free(timr->meta.bkt);\n+\t\ttimvf_log_err(\"Unable to create chunkpool.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tret = rte_mempool_set_ops_byname(timr->meta.chunk_pool,\n+\t\t\tRTE_MBUF_DEFAULT_MEMPOOL_OPS, NULL);\n+\ttimvf_log_dbg(\"Not giving back chunks to fpa\");\n+\n+\tif (ret != 0) {\n+\t\ttimvf_log_err(\"Unable to set chunkpool ops.\");\n+\t\tgoto mem_err;\n+\t}\n+\n+\tret = rte_mempool_populate_default(timr->meta.chunk_pool);\n+\tif (ret < 0) {\n+\t\ttimvf_log_err(\"Unable to set populate chunkpool.\");\n+\t\tgoto mem_err;\n+\t}\n+\ttimvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VRING_BASE);\n+\ttimvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_INT);\n+\ttimvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_INT_W1S);\n+\ttimvf_write64(0x7, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_ENA_W1C);\n+\ttimvf_write64(0x7, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_ENA_W1S);\n+\n+\treturn 0;\n+mem_err:\n+\trte_free(timr);\n+\treturn -ENOMEM;\n+cfg_err:\n+\trte_free(timr);\n+\treturn -EINVAL;\n+}\n+\n+static int\n+timvf_ring_free(struct rte_event_timer_adapter *adptr)\n+{\n+\tstruct timvf_ring *timr = adptr->data->adapter_priv;\n+\trte_mempool_free(timr->meta.chunk_pool);\n+\trte_free(timr->meta.bkt);\n+\trte_free(adptr->data->adapter_priv);\n+\treturn 0;\n+}\n+\n+static struct rte_event_timer_adapter_ops timvf_ops = {\n+\t\t.init\t\t= timvf_ring_create,\n+\t\t.uninit\t\t= timvf_ring_free,\n+\t\t.get_info\t= timvf_ring_info_get,\n+};\n+\n+int\n+timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n+\t\tuint32_t *caps, const struct rte_event_timer_adapter_ops **ops)\n+{\n+\tRTE_SET_USED(dev);\n+\tRTE_SET_USED(flags);\n+\t*caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;\n+\t*ops = &timvf_ops;\n+\treturn -EINVAL;\n+}\ndiff --git a/drivers/event/octeontx/timvf_evdev.h b/drivers/event/octeontx/timvf_evdev.h\nnew file mode 100644\nindex 000000000..fcc938b82\n--- /dev/null\n+++ b/drivers/event/octeontx/timvf_evdev.h\n@@ -0,0 +1,158 @@\n+/*\n+ * SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#ifndef __TIMVF_EVDEV_H__\n+#define __TIMVF_EVDEV_H__\n+\n+#include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_debug.h>\n+#include <rte_eal.h>\n+#include <rte_eventdev.h>\n+#include <rte_event_timer_adapter.h>\n+#include <rte_event_timer_adapter_pmd.h>\n+#include <rte_io.h>\n+#include <rte_lcore.h>\n+#include <rte_log.h>\n+#include <rte_malloc.h>\n+#include <rte_mempool.h>\n+#include <rte_memzone.h>\n+#include <rte_pci.h>\n+#include <rte_prefetch.h>\n+#include <rte_reciprocal.h>\n+\n+#include <octeontx_mbox.h>\n+\n+#define timvf_log(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, otx_logtype_timvf, \\\n+\t\t\t\"[%s] %s() \" fmt \"\\n\", \\\n+\t\t\tRTE_STR(event_timer_octeontx), __func__, ## args)\n+\n+#define timvf_log_info(fmt, ...) timvf_log(INFO, fmt, ##__VA_ARGS__)\n+#define timvf_log_dbg(fmt, ...) timvf_log(DEBUG, fmt, ##__VA_ARGS__)\n+#define timvf_log_err(fmt, ...) timvf_log(ERR, fmt, ##__VA_ARGS__)\n+#define timvf_func_trace timvf_log_dbg\n+\n+#define TIM_COPROC\t\t\t\t(8)\n+#define TIM_GET_DEV_INFO\t\t\t(1)\n+#define TIM_GET_RING_INFO\t\t\t(2)\n+#define TIM_SET_RING_INFO\t\t\t(3)\n+#define TIM_RING_START_CYC_GET\t\t\t(4)\n+\n+#define TIM_MAX_RINGS\t\t\t\t(64)\n+#define TIM_DEV_PER_NODE\t\t\t(1)\n+#define TIM_VF_PER_DEV\t\t\t\t(64)\n+#define TIM_RING_PER_DEV\t\t\t(TIM_VF_PER_DEV)\n+#define TIM_RING_NODE_SHIFT\t\t\t(6)\n+#define TIM_RING_MASK\t\t\t\t((TIM_RING_PER_DEV) - 1)\n+#define TIM_RING_INVALID\t\t\t(-1)\n+\n+#define TIM_MIN_INTERVAL\t\t\t(1E3)\n+#define TIM_MAX_INTERVAL\t\t\t((1ull << 32) - 1)\n+#define TIM_MAX_BUCKETS\t\t\t\t(1ull << 20)\n+#define TIM_CHUNK_SIZE\t\t\t\t(4096)\n+#define TIM_MAX_CHUNKS_PER_BUCKET\t\t(1ull << 32)\n+\n+#define TIMVF_MAX_BURST\t\t\t\t(8)\n+\n+/* TIM VF Control/Status registers (CSRs): */\n+/* VF_BAR0: */\n+#define TIM_VF_NRSPERR_INT\t\t\t(0x0)\n+#define TIM_VF_NRSPERR_INT_W1S\t\t\t(0x8)\n+#define TIM_VF_NRSPERR_ENA_W1C\t\t\t(0x10)\n+#define TIM_VF_NRSPERR_ENA_W1S\t\t\t(0x18)\n+#define TIM_VRING_FR_RN_CYCLES\t\t\t(0x20)\n+#define TIM_VRING_FR_RN_GPIOS\t\t\t(0x28)\n+#define TIM_VRING_FR_RN_GTI\t\t\t(0x30)\n+#define TIM_VRING_FR_RN_PTP\t\t\t(0x38)\n+#define TIM_VRING_CTL0\t\t\t\t(0x40)\n+#define TIM_VRING_CTL1\t\t\t\t(0x50)\n+#define TIM_VRING_CTL2\t\t\t\t(0x60)\n+#define TIM_VRING_BASE\t\t\t\t(0x100)\n+#define TIM_VRING_AURA\t\t\t\t(0x108)\n+#define TIM_VRING_REL\t\t\t\t(0x110)\n+\n+#define timvf_read64 rte_read64_relaxed\n+#define timvf_write64 rte_write64_relaxed\n+\n+#ifndef __hot\n+#define __hot\t__attribute__((hot))\n+#endif\n+\n+extern int otx_logtype_timvf;\n+\n+static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1;\n+\n+enum timvf_clk_src {\n+\tTIM_CLK_SRC_SCLK,\n+\tTIM_CLK_SRC_GPIO,\n+\tTIM_CLK_SRC_GTI,\n+\tTIM_CLK_SRC_PTP,\n+};\n+\n+/* TIM_MEM_BUCKET */\n+struct tim_mem_bucket {\n+\tuint64_t first_chunk;\n+\tunion {\n+\t\tuint64_t w1;\n+\t\tstruct {\n+\t\t\tuint32_t nb_entry;\n+\t\t\tuint8_t sbt:1;\n+\t\t\tuint8_t hbt:1;\n+\t\t\tuint8_t bsk:1;\n+\t\t\tuint8_t rsvd:5;\n+\t\t\tuint8_t lock;\n+\t\t\tint16_t chunk_remainder;\n+\t\t};\n+\t};\n+\tuint64_t current_chunk;\n+\tuint64_t pad;\n+} __rte_packed;\n+\n+struct tim_mem_entry {\n+\tuint64_t w0;\n+\tuint64_t wqe;\n+} __rte_packed;\n+\n+struct timvf_ctrl_reg {\n+\tuint64_t rctrl0;\n+\tuint64_t rctrl1;\n+\tuint64_t rctrl2;\n+\tuint8_t use_pmu;\n+} __rte_packed;\n+\n+typedef uint32_t (*bkt_id)(uint32_t bkt_tcks, uint32_t nb_bkts);\n+\n+struct timvf_meta {\n+\tbkt_id get_target_bkt;\n+\tstruct rte_reciprocal_u64 fast_div;\n+\tuint64_t ring_start_cyc;\n+\tuint32_t nb_bkts;\n+\tstruct tim_mem_bucket *bkt;\n+\tvoid *chunk_pool;\n+\tuint64_t tck_int;\n+} __rte_cache_aligned;\n+\n+struct timvf_ring {\n+\tstruct timvf_meta meta;\n+\tuint64_t tck_nsec;\n+\tvoid *vbar0;\n+\tvoid *bkt_pos;\n+\tuint64_t max_tout;\n+\tuint64_t nb_chunks;\n+\tenum timvf_clk_src clk_src;\n+\tuint16_t tim_ring_id;\n+} __rte_cache_aligned;\n+\n+static __rte_always_inline uint32_t __hot\n+bkt_mod(uint32_t rel_bkt, uint32_t nb_bkts)\n+{\n+\treturn rel_bkt % nb_bkts;\n+}\n+\n+int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n+\t\tuint32_t *caps, const struct rte_event_timer_adapter_ops **ops);\n+\n+#endif /* __TIMVF_EVDEV_H__ */\n", "prefixes": [ "dpdk-dev", "03/10" ] }