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GET /api/patches/35124/?format=api
{ "id": 35124, "url": "http://patches.dpdk.org/api/patches/35124/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/AM4PR07MB3300A7F00A63C7337005857E8EF70@AM4PR07MB3300.eurprd07.prod.outlook.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<AM4PR07MB3300A7F00A63C7337005857E8EF70@AM4PR07MB3300.eurprd07.prod.outlook.com>", "list_archive_url": "https://inbox.dpdk.org/dev/AM4PR07MB3300A7F00A63C7337005857E8EF70@AM4PR07MB3300.eurprd07.prod.outlook.com", "date": "2018-02-12T06:02:25", "name": "[dpdk-dev] dev Digest, Vol 180, Issue 152", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "d77cdfc8215bdba740006e4d3df763aa2e2ff414", "submitter": { "id": 976, "url": "http://patches.dpdk.org/api/people/976/?format=api", "name": "Nitin Katiyar", "email": "nitin.katiyar@ericsson.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/AM4PR07MB3300A7F00A63C7337005857E8EF70@AM4PR07MB3300.eurprd07.prod.outlook.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/35124/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/35124/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8B82A1B315;\n\tMon, 12 Feb 2018 07:02:30 +0100 (CET)", "from sesbmg22.ericsson.net (sesbmg22.ericsson.net [193.180.251.48])\n\tby dpdk.org (Postfix) with ESMTP id C566B1B312\n\tfor <dev@dpdk.org>; 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q=dns/txt; i=@ericsson.com; t=1518415349;\n\th=From:Sender:Reply-To:Subject:Date:Message-ID:To:CC:MIME-Version:Content-Type:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From:\n\tResent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id:\n\tList-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive;\n\tbh=p2smVBUAXqJBtRRZ8PYr+BmRcY7vcR5F9LzLEua9VE8=;\n\tb=CnVjfY89JiJvldNFgtddgnIG40KUTwiDdy57vhP5L1IAuDbnnCyCtRoxaXXSDRhD\n\t8iECeoUAENEtWIUiNREt0PeHvl/s2Lei2IwNuZ9lbsCSiB0g70qcCYFoRQlw8/9e\n\tu4MBbpg56wmUf7eLwKpaZvuBDtKgQYBXyVkglgIP2U8=;", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com;\n\ts=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=CdPB0F42xqOGNcnU56+gN91MsWcTfwFqZ+Hp/izQucg=;\n\tb=Fy+N2j20MaASwOm6Xh3qIkOdJZxx2TeUqvjKmNmP3iUAZW13bgzguJ5nXM2OzzqhuBJs4HHWQY02BNfbHXtLx477DcAmpvyTyfxoMyflcXKGBYnpeH3vaWHWOO/dBDugn6cjQdiQgr58H2hI9kG3dF/zekCbsB0BeHOYw7f4nkc=" ], "X-AuditID": "c1b4fb30-799639c000004778-b7-5a812df5c027", "From": "Nitin Katiyar <nitin.katiyar@ericsson.com>", "To": "\"dev@dpdk.org\" <dev@dpdk.org>", "CC": "Venkatesan Pradeep <venkatesan.pradeep@ericsson.com>", "Thread-Topic": "dev Digest, Vol 180, Issue 152", "Thread-Index": "AQHTnCEGaYVvdz7PW0qN11KcV69YcaOgUB6Q", "Date": "Mon, 12 Feb 2018 06:02:25 +0000", "Message-ID": "<AM4PR07MB3300A7F00A63C7337005857E8EF70@AM4PR07MB3300.eurprd07.prod.outlook.com>", "References": "<mailman.360.1517574292.21795.dev@dpdk.org>", "In-Reply-To": "<mailman.360.1517574292.21795.dev@dpdk.org>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-originating-ip": "[125.16.128.122]", "x-ms-publictraffictype": "Email", "x-microsoft-exchange-diagnostics": "1; AM4PR07MB1601;\n\t7:9IzZhWUMB8JPEIBSSCYflGDqEAGjGJD/7FeX2rraUBwIzt+51YbIkzjOkkkcMNjUmM+5ujk1nBfoCLOMa1JV6barz+eryc0hjvzv2WAVmbI5mhPveO2E4FxaQ/3E0xRi5gQnoE3jSF7zRZLEGqPCyx5SjfmE/SwlbTGvGxEe/zMofNbcAkQVLKwHfQTyRrOuUOGau2xVoF7XbE9oODVvpFM1xJqls8dMtHvNKyCZb0AYI/ld4JprLWPnMJJAWn+X", "x-ms-exchange-antispam-srfa-diagnostics": "SSOS;SSOR;", "x-forefront-antispam-report": "SFV:SKI; SCL:-1; SFV:NSPM;\n\tSFS:(10009020)(366004)(396003)(39380400002)(376002)(39860400002)(346002)(18543002)(13464003)(5403001)(27574002)(10533003)(199004)(189003)(68736007)(14454004)(105586002)(99286004)(316002)(106356001)(33656002)(2351001)(66066001)(74316002)(5660300001)(305945005)(7736002)(6436002)(53546011)(6506007)(186003)(3660700001)(3280700002)(8676002)(2906002)(81166006)(2501003)(5640700003)(53946003)(55236004)(6346003)(478600001)(6116002)(3846002)(5250100002)(7696005)(25786009)(81156014)(1730700003)(4326008)(107886003)(8936002)(102836004)(53936002)(16200700003)(6306002)(55016002)(6916009)(2950100002)(229853002)(76176011)(86362001)(575784001)(9686003)(97736004)(2900100001)(966005)(6246003)(59450400001)(26005)(559001)(579004)(569006);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM4PR07MB1601;\n\tH:AM4PR07MB3300.eurprd07.prod.outlook.com; FPR:; SPF:None;\n\tPTR:InfoNoRecords; A:1; MX:1; LANG:en; ", "x-ms-office365-filtering-correlation-id": "7e1b1d8e-d36b-4489-99ef-08d571de30ed", "x-microsoft-antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(7020095)(4652020)(5600026)(4604075)(3008032)(4534165)(7168020)(4627221)(201703031133081)(201702281549075)(2017052603307)(7153060)(7193020);\n\tSRVR:AM4PR07MB1601; ", "x-ms-traffictypediagnostic": "AM4PR07MB1601:", "x-microsoft-antispam-prvs": "<AM4PR07MB1601F04C91D4D011161999C78EF70@AM4PR07MB1601.eurprd07.prod.outlook.com>", "x-exchange-antispam-report-test": "UriScan:(228905959029699);", "x-exchange-antispam-report-cfa-test": "BCL:0; PCL:0;\n\tRULEID:(6040501)(2401047)(5005006)(8121501046)(3002001)(3231101)(944501161)(10201501046)(93006095)(93001095)(6041288)(20161123558120)(20161123562045)(20161123560045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(6072148)(201708071742011);\n\tSRVR:AM4PR07MB1601; BCL:0; PCL:0; RULEID:; SRVR:AM4PR07MB1601; ", "x-forefront-prvs": "0581B5AB35", "received-spf": "None (protection.outlook.com: ericsson.com does not designate\n\tpermitted sender hosts)", "authentication-results": "spf=none (sender IP is )\n\tsmtp.mailfrom=nitin.katiyar@ericsson.com; ", "x-microsoft-antispam-message-info": "aCF4+NS5Gy/DkHJGi31BU5GcF+ufG8pfZ5ddYDo6ZiPmWLpmM4qd73BbR1893MJV3ArdYNDSFHpBrAsTaJ0SGA==", "spamdiagnosticoutput": "1:99", "spamdiagnosticmetadata": "NSPM", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-MS-Exchange-CrossTenant-Network-Message-Id": "7e1b1d8e-d36b-4489-99ef-08d571de30ed", "X-MS-Exchange-CrossTenant-originalarrivaltime": "12 Feb 2018 06:02:25.8728\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "92e84ceb-fbfd-47ab-be52-080c6b87953f", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM4PR07MB1601", "X-OriginatorOrg": "ericsson.com", "X-Brightmail-Tracker": "H4sIAAAAAAAAA+NgFvrLIsWRmVeSWpSXmKPExsUyM2K7n+5X3cYog8b1whbvPm1ncmD0+LVg\n\tKWsAYxSXTUpqTmZZapG+XQJXxtqWq6wFG+cxVdw/cZ+xgXHJS8YuRg4OCQETifOthV2MXBxC\n\tAocZJe7/aGGDcE4wShx4sIYZxGER+MQk0bHzBlRmEpPE555t7BDOI0aJ5efOsXYxcnKwCRhI\n\tbL84iR3EFhFQlJg+cTIbyA5mAQuJ6Wd0QMLCAtoSy09/ZoQo0ZH4vuA7M4RtJLFo/1Gwk1gE\n\tVCVufgAr4RWIkXjz5S0biC0kYC5xZdsnJhCbE2hi85oVYDajgJjE91NrwGxmAXGJW0/mg9kS\n\tAgISS/acZ4awRSVePv7HCmErSWye+QKqRlbi0vxuRpBXJAS2MEk8fv2ZDSJhLNE1YQ8rRGIC\n\tu8Tln28YIRK+EmeXLGOBSFxklFhwfwo7REJLYsfUPVArsiU2Lj0GZVtLvHk4Faqhn1li1eot\n\tUCtkJO59aWWcwKg/C8npELaOxILdn9ggbG2JZQtfM88CB4egxMmZT1gWMLKsYhQtTi1Oyk03\n\tMtJLLcpMLi7Oz9PLSy3ZxAhMFAe3/DbYwfjyueMhRgEORiUe3lkKjVFCrIllxZW5hxglOJiV\n\tRHg7LzRECfGmJFZWpRblxxeV5qQWH2KU5mBREuc96ckbJSSQnliSmp2aWpBaBJNl4uCUamB0\n\tiTselc11XoUz8Zz5Ps1tHy29oq68zA1b8NdPSbzX3CJg/4d5/OKZ+mfPzEpb3lu4cEPlc6/1\n\tMzb7r7C1WlC42oWN84owW+G0jNLnP9gybUUWtfAHrPtYZZrMYOT8K6KmP2H5bWbedYbFO4QF\n\t7yYvv3iDuWHvJU9Z+Z+CM/hcP1e9PrHkUYkSS3FGoqEWc1FxIgAb7jS7EAMAAA==", "Subject": "Re: [dpdk-dev] dev Digest, Vol 180, Issue 152", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Hi Beilei,\nI was looking at the patches and have few queries regarding support-multi-driver.\n1) With these patches, we have 2 different values for some of the global registers depending upon whether single driver or multi-driver is using all ports of the NIC. Does it impact any functionality/performance if we use DPDK drivers in single driver vs multi-driver support? \n2) Why can't we have same settings for both the cases? That way we don't have to care for extra parameter.\n3) Does this issue need any update for kernel driver also? \n\n\nRegards,\nNitin\n\n-----Original Message-----\nFrom: dev [mailto:dev-bounces@dpdk.org] On Behalf Of dev-request@dpdk.org\nSent: Friday, February 02, 2018 5:55 PM\nTo: dev@dpdk.org\nSubject: dev Digest, Vol 180, Issue 152\n\nSend dev mailing list submissions to\n\tdev@dpdk.org\n\nTo subscribe or unsubscribe via the World Wide Web, visit\n\thttps://dpdk.org/ml/listinfo/dev\nor, via email, send a message with subject or body 'help' to\n\tdev-request@dpdk.org\n\nYou can reach the person managing the list at\n\tdev-owner@dpdk.org\n\nWhen replying, please edit your Subject line so it is more specific than \"Re: Contents of dev digest...\"\n\n\nToday's Topics:\n\n 1. [PATCH v3 2/4] net/i40e: add debug logs when writing\tglobal\n registers (Beilei Xing)\n 2. [PATCH v3 3/4] net/i40e: fix multiple driver support\tissue\n (Beilei Xing)\n 3. [PATCH v3 4/4] net/i40e: fix interrupt conflict when\tusing\n multi-driver (Beilei Xing)\n\n\n----------------------------------------------------------------------\n\nMessage: 1\nDate: Fri, 2 Feb 2018 20:25:08 +0800\nFrom: Beilei Xing <beilei.xing@intel.com>\nTo: dev@dpdk.org,\tjingjing.wu@intel.com\nCc: stable@dpdk.org\nSubject: [dpdk-dev] [PATCH v3 2/4] net/i40e: add debug logs when\n\twriting\tglobal registers\nMessage-ID: <1517574310-93096-3-git-send-email-beilei.xing@intel.com>\n\nAdd debug logs when writing global registers.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\nCc: stable@dpdk.org\n---\n drivers/net/i40e/i40e_ethdev.c | 127 +++++++++++++++++++++++++----------------\n drivers/net/i40e/i40e_ethdev.h | 8 +++\n 2 files changed, 87 insertions(+), 48 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 44821f2..ef23241 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -716,6 +716,15 @@ rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+static inline void\n+i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) \n+{\n+\ti40e_write_rx_ctl(hw, reg_addr, reg_val);\n+\tPMD_DRV_LOG(DEBUG, \"Global register 0x%08x is modified \"\n+\t\t \"with value 0x%08x\",\n+\t\t reg_addr, reg_val);\n+}\n+\n RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv); RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);\n \n@@ -735,9 +744,9 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)\n \t * configuration API is added to avoid configuration conflicts\n \t * between ports of the same device.\n \t */\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);\n \ti40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);\n \n \t/*\n@@ -746,8 +755,8 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)\n \t * configuration API is added to avoid configuration conflicts\n \t * between ports of the same device.\n \t */\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);\n-\tI40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);\n \ti40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);\n }\n \n@@ -2799,8 +2808,9 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,\n \t\t\t \"I40E_GL_SWT_L2TAGCTRL[%d]\", reg_id);\n \t\treturn ret;\n \t}\n-\tPMD_DRV_LOG(DEBUG, \"Debug write 0x%08\"PRIx64\" to \"\n-\t\t \"I40E_GL_SWT_L2TAGCTRL[%d]\", reg_w, reg_id);\n+\tPMD_DRV_LOG(DEBUG,\n+\t\t \"Global register 0x%08x is changed with value 0x%08x\",\n+\t\t I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);\n \n \ti40e_global_cfg_warning(I40E_WARNING_TPID);\n \n@@ -3030,16 +3040,16 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n \t}\n \n \t/* config the water marker both based on the packets and bytes */\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_PHW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,\n \t\t (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_PLW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,\n \t\t (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_GHW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,\n \t\t pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT);\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_GLW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,\n \t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT);\n \ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n@@ -6880,6 +6890,9 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)\n \t\t\t\t\t\t reg, NULL);\n \t\tif (ret != 0)\n \t\t\treturn ret;\n+\t\tPMD_DRV_LOG(DEBUG, \"Global register 0x%08x is changed \"\n+\t\t\t \"with value 0x%08x\",\n+\t\t\t I40E_GL_PRS_FVBM(2), reg);\n \t\ti40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);\n \t} else {\n \t\tret = 0;\n@@ -7124,41 +7137,43 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t\t\tI40E_GLQF_HSYM_SYMH_ENA_MASK : 0;\n \t\tif (hw->mac.type == I40E_MAC_X722) {\n \t\t\tif (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),\n \t\t\t\t reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),\n \t\t\t\t reg);\n \t\t\t} else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),\n \t\t\t\t reg);\n \t\t\t} else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),\n \t\t\t\t reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),\n \t\t\t\t reg);\n \t\t\t} else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(\n+\t\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(\n \t\t\t\t I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),\n \t\t\t\t reg);\n \t\t\t} else {\n-\t\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),\n-\t\t\t\t reg);\n+\t\t\t\ti40e_write_global_rx_ctl(hw,\n+\t\t\t\t\t\t\t I40E_GLQF_HSYM(pctype),\n+\t\t\t\t\t\t\t reg);\n \t\t\t}\n \t\t} else {\n-\t\t\ti40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);\n+\t\t\ti40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(pctype),\n+\t\t\t\t\t\t reg);\n \t\t}\n \t\ti40e_global_cfg_warning(I40E_WARNING_HSYM);\n \t}\n@@ -7184,7 +7199,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t/* Use the default, and keep it as it is */\n \t\tgoto out;\n \n-\ti40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);\n+\ti40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);\n \ti40e_global_cfg_warning(I40E_WARNING_QF_CTL);\n \n out:\n@@ -7799,6 +7814,18 @@ i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) }\n \n static void\n+i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t \n+val) {\n+\tuint32_t reg = i40e_read_rx_ctl(hw, addr);\n+\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] original: 0x%08x\", addr, reg);\n+\tif (reg != val)\n+\t\ti40e_write_global_rx_ctl(hw, addr, val);\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] after: 0x%08x\", addr,\n+\t\t (uint32_t)i40e_read_rx_ctl(hw, addr)); }\n+\n+static void\n i40e_filter_input_set_init(struct i40e_pf *pf) {\n \tstruct i40e_hw *hw = I40E_PF_TO_HW(pf); @@ -7831,24 +7858,28 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),\n \t\t\t\t (uint32_t)((inset_reg >>\n \t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n \t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n \t\t\t\t (uint32_t)((inset_reg >>\n \t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \n \t\tfor (i = 0; i < num; i++) {\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t mask_reg[i]);\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t\t mask_reg[i]);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t mask_reg[i]);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t\t mask_reg[i]);\n \t\t}\n \t\t/*clear unused mask registers of the pctype */\n \t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t 0);\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t\t 0);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t 0);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t\t 0);\n \t\t}\n \t\tI40E_WRITE_FLUSH(hw);\n \n@@ -7920,20 +7951,20 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,\n \n \tinset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);\n \n-\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n-\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n-\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n-\t\t\t (uint32_t)((inset_reg >>\n-\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n+\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n+\t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n+\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n+\t\t\t\t (uint32_t)((inset_reg >>\n+\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n \n \tfor (i = 0; i < num; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t mask_reg[i]);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t mask_reg[i]);\n \t/*clear unused mask registers of the pctype */\n \tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t 0);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t 0);\n \ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n \tI40E_WRITE_FLUSH(hw);\n \n@@ -8007,12 +8038,12 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \n \tfor (i = 0; i < num; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t mask_reg[i]);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t mask_reg[i]);\n \t/*clear unused mask registers of the pctype */\n \tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t 0);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t 0);\n \ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n \tI40E_WRITE_FLUSH(hw);\n \ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index 1d813ef..12b6000 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -103,6 +103,14 @@\n \t(((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \\\n \t((vf)->version_minor == 1))\n \n+static inline void\n+I40E_WRITE_GLB_REG(struct i40e_hw *hw, uint32_t reg, uint32_t value) {\n+\tI40E_WRITE_REG(hw, reg, value);\n+\tPMD_DRV_LOG(DEBUG, \"Global register 0x%08x is modified \"\n+\t\t \"with value 0x%08x\",\n+\t\t reg, value);\n+}\n+\n /* index flex payload per layer */\n enum i40e_flxpld_layer_idx {\n \tI40E_FLXPLD_L2_IDX = 0,\n--\n2.5.5\n\n\n\n------------------------------\n\nMessage: 2\nDate: Fri, 2 Feb 2018 20:25:09 +0800\nFrom: Beilei Xing <beilei.xing@intel.com>\nTo: dev@dpdk.org,\tjingjing.wu@intel.com\nCc: stable@dpdk.org\nSubject: [dpdk-dev] [PATCH v3 3/4] net/i40e: fix multiple driver\n\tsupport\tissue\nMessage-ID: <1517574310-93096-4-git-send-email-beilei.xing@intel.com>\n\nThis patch provides the option to disable writing some global registers\nin PMD, in order to avoid affecting other drivers, when multiple drivers\nrun on the same NIC and control different physical ports. Because there\nare few global resources shared among different physical ports.\n\nFixes: ec246eeb5da1 (\"i40e: use default filter input set on init\")\nFixes: 98f055707685 (\"i40e: configure input fields for RSS or flow director\")\nFixes: f05ec7d77e41 (\"i40e: initialize flow director flexible payload setting\")\nFixes: e536c2e32883 (\"net/i40e: fix parsing QinQ packets type\")\nFixes: 19b16e2f6442 (\"ethdev: add vlan type when setting ether type\")\nCc: stable@dpdk.org\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 215 ++++++++++++++++++++++++++++++++---------\n drivers/net/i40e/i40e_ethdev.h | 2 +\n 2 files changed, 171 insertions(+), 46 deletions(-)\n\ndiff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex ef23241..ae0f31a 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -944,6 +944,67 @@ config_floating_veb(struct rte_eth_dev *dev)\n #define I40E_L2_TAGS_S_TAG_SHIFT 1\n #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)\n \n+#define ETH_I40E_SUPPORT_MULTI_DRIVER\t\"support-multi-driver\"\n+RTE_PMD_REGISTER_PARAM_STRING(net_i40e,\n+\t\t\t ETH_I40E_SUPPORT_MULTI_DRIVER \"=0|1\");\n+\n+static int\n+i40e_parse_multi_drv_handler(__rte_unused const char *key,\n+\t\t\t const char *value,\n+\t\t\t void *opaque)\n+{\n+\tstruct i40e_pf *pf;\n+\tunsigned long support_multi_driver;\n+\tchar *end;\n+\n+\tpf = (struct i40e_pf *)opaque;\n+\n+\terrno = 0;\n+\tsupport_multi_driver = strtoul(value, &end, 10);\n+\tif (errno != 0 || end == value || *end != 0) {\n+\t\tPMD_DRV_LOG(WARNING, \"Wrong global configuration\");\n+\t\treturn -(EINVAL);\n+\t}\n+\n+\tif (support_multi_driver == 1 || support_multi_driver == 0)\n+\t\tpf->support_multi_driver = (bool)support_multi_driver;\n+\telse\n+\t\tPMD_DRV_LOG(WARNING, \"%s must be 1 or 0,\",\n+\t\t\t \"enable global configuration by default.\"\n+\t\t\t ETH_I40E_SUPPORT_MULTI_DRIVER);\n+\treturn 0;\n+}\n+\n+static int\n+i40e_support_multi_driver(struct rte_eth_dev *dev)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct rte_pci_device *pci_dev = dev->pci_dev;\n+\tstatic const char *valid_keys[] = {\n+\t\tETH_I40E_SUPPORT_MULTI_DRIVER, NULL};\n+\tstruct rte_kvargs *kvlist;\n+\n+\t/* Enable global configuration by default */\n+\tpf->support_multi_driver = false;\n+\n+\tif (!pci_dev->device.devargs)\n+\t\treturn 0;\n+\n+\tkvlist = rte_kvargs_parse(pci_dev->device.devargs->args, valid_keys);\n+\tif (!kvlist)\n+\t\treturn -EINVAL;\n+\n+\tif (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)\n+\t\tPMD_DRV_LOG(WARNING, \"More than one argument \\\"%s\\\" and only \"\n+\t\t\t \"the first invalid or last valid one is used !\",\n+\t\t\t ETH_I40E_SUPPORT_MULTI_DRIVER);\n+\n+\trte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,\n+\t\t\t i40e_parse_multi_drv_handler, pf);\n+\trte_kvargs_free(kvlist);\n+\treturn 0;\n+}\n+\n static int\n eth_i40e_dev_init(struct rte_eth_dev *dev)\n {\n@@ -993,6 +1054,9 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \thw->bus.func = pci_dev->addr.function;\n \thw->adapter_stopped = 0;\n \n+\t/* Check if need to support multi-driver */\n+\ti40e_support_multi_driver(dev);\n+\n \t/* Make sure all is clean before doing PF reset */\n \ti40e_clear_hw(hw);\n \n@@ -1019,7 +1083,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \t * software. It should be removed once issues are fixed\n \t * in NVM.\n \t */\n-\ti40e_GLQF_reg_init(hw);\n+\tif (!pf->support_multi_driver)\n+\t\ti40e_GLQF_reg_init(hw);\n \n \t/* Initialize the input set for filters (hash and fd) to default value */\n \ti40e_filter_input_set_init(pf);\n@@ -1115,11 +1180,14 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \ti40e_set_fc(hw, &aq_fail, TRUE);\n \n \t/* Set the global registers with default ether type value */\n-\tret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);\n-\tif (ret != I40E_SUCCESS) {\n-\t\tPMD_INIT_LOG(ERR, \"Failed to set the default outer \"\n-\t\t\t \"VLAN ether type\");\n-\t\tgoto err_setup_pf_switch;\n+\tif (!pf->support_multi_driver) {\n+\t\tret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,\n+\t\t\t\t\t ETHER_TYPE_VLAN);\n+\t\tif (ret != I40E_SUCCESS) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to set the default outer \"\n+\t\t\t\t \"VLAN ether type\");\n+\t\t\tgoto err_setup_pf_switch;\n+\t\t}\n \t}\n \n \t/* PF setup, which includes VSI setup */\n@@ -2754,11 +2822,17 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,\n \t\t uint16_t tpid)\n {\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tuint64_t reg_r = 0, reg_w = 0;\n \tuint16_t reg_id = 0;\n \tint ret = 0;\n \tint qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Setting TPID is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tswitch (vlan_type) {\n \tcase ETH_VLAN_TYPE_OUTER:\n \t\tif (qinq)\n@@ -3039,20 +3113,25 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n \t\tI40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);\n \t}\n \n-\t/* config the water marker both based on the packets and bytes */\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,\n-\t\t (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,\n-\t\t (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,\n-\t\t pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT);\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,\n-\t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT);\n-\ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n+\tif (!pf->support_multi_driver) {\n+\t\t/* config water marker both based on the packets and bytes */\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,\n+\t\t\t\t(pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,\n+\t\t\t\t(pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,\n+\t\t\t\t pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT);\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,\n+\t\t\t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t \"Water marker configuration is not supported.\");\n+\t}\n \n \tI40E_WRITE_FLUSH(hw);\n \n@@ -6870,9 +6949,15 @@ i40e_tunnel_filter_param_check(struct i40e_pf *pf,\n static int\n i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)\n {\n+\tstruct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;\n \tuint32_t val, reg;\n \tint ret = -EINVAL;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"GRE key length configuration is unsupported\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tval = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));\n \tPMD_DRV_LOG(DEBUG, \"Read original GL_PRS_FVBM with 0x%08x\\n\", val);\n \n@@ -7114,12 +7199,18 @@ static int\n i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t\t\t struct rte_eth_hash_global_conf *g_cfg)\n {\n+\tstruct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;\n \tint ret;\n \tuint16_t i;\n \tuint32_t reg;\n \tuint32_t mask0 = g_cfg->valid_bit_mask[0];\n \tenum i40e_filter_pctype pctype;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Hash global configuration is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \t/* Check the input parameters */\n \tret = i40e_hash_global_config_check(g_cfg);\n \tif (ret < 0)\n@@ -7850,6 +7941,12 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\t\t\t\t\t I40E_INSET_MASK_NUM_REG);\n \t\tif (num < 0)\n \t\t\treturn;\n+\n+\t\tif (pf->support_multi_driver && num > 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Input set setting is not supported.\");\n+\t\t\treturn;\n+\t\t}\n+\n \t\tinset_reg = i40e_translate_input_set_reg(hw->mac.type,\n \t\t\t\t\tinput_set);\n \n@@ -7858,39 +7955,49 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),\n \t\t\t\t (uint32_t)((inset_reg >>\n \t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n-\t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n-\t\t\t\t (uint32_t)((inset_reg >>\n-\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\n-\t\tfor (i = 0; i < num; i++) {\n+\t\tif (!pf->support_multi_driver) {\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t I40E_GLQF_HASH_INSET(0, pctype),\n+\t\t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n \t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t I40E_GLQF_HASH_INSET(1, pctype),\n+\t\t\t\t\t (uint32_t)((inset_reg >>\n+\t\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n+\n+\t\t\tfor (i = 0; i < num; i++) {\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n \t\t\t\t\t\t mask_reg[i]);\n-\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n \t\t\t\t\t\t mask_reg[i]);\n-\t\t}\n-\t\t/*clear unused mask registers of the pctype */\n-\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {\n-\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t}\n+\t\t\t/*clear unused mask registers of the pctype */\n+\t\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n \t\t\t\t\t\t 0);\n-\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t\t\t 0);\n+\t\t\t\t\t\t 0);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t \"Input set setting is not supported.\");\n \t\t}\n \t\tI40E_WRITE_FLUSH(hw);\n \n \t\t/* store the default input set */\n-\t\tpf->hash_input_set[pctype] = input_set;\n+\t\tif (!pf->support_multi_driver)\n+\t\t\tpf->hash_input_set[pctype] = input_set;\n \t\tpf->fdir.input_set[pctype] = input_set;\n \t}\n \n-\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n-\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n-\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n+\tif (!pf->support_multi_driver) {\n+\t\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n+\t}\n }\n \n int\n@@ -7903,6 +8010,11 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,\n \tuint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};\n \tint ret, i, num;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Hash input set setting is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tif (!conf) {\n \t\tPMD_DRV_LOG(ERR, \"Invalid pointer\");\n \t\treturn -EFAULT;\n@@ -8029,6 +8141,11 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \tif (num < 0)\n \t\treturn -EINVAL;\n \n+\tif (pf->support_multi_driver && num > 0) {\n+\t\tPMD_DRV_LOG(ERR, \"FDIR bit mask is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tinset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);\n \n \ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),\n@@ -8037,14 +8154,20 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \t\t\t (uint32_t)((inset_reg >>\n \t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \n-\tfor (i = 0; i < num; i++)\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t mask_reg[i]);\n-\t/*clear unused mask registers of the pctype */\n-\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t 0);\n-\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n+\tif (!pf->support_multi_driver) {\n+\t\tfor (i = 0; i < num; i++)\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t mask_reg[i]);\n+\t\t/*clear unused mask registers of the pctype */\n+\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t 0);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"FDIR bit mask is not supported.\");\n+\t}\n \tI40E_WRITE_FLUSH(hw);\n \n \tpf->fdir.input_set[pctype] = input_set;\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 12b6000..82d5501 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -485,6 +485,8 @@ struct i40e_pf {\n \tbool floating_veb; /* The flag to use the floating VEB */\n \t/* The floating enable flag for the specific VF */\n \tbool floating_veb_list[I40E_MAX_VF];\n+\n+\tbool support_multi_driver; /* 1 - support multiple driver */\n };\n \n enum pending_msg {\n-- \n2.5.5\n\n\n\n------------------------------\n\nMessage: 3\nDate: Fri, 2 Feb 2018 20:25:10 +0800\nFrom: Beilei Xing <beilei.xing@intel.com>\nTo: dev@dpdk.org,\tjingjing.wu@intel.com\nCc: stable@dpdk.org\nSubject: [dpdk-dev] [PATCH v3 4/4] net/i40e: fix interrupt conflict\n\twhen\tusing multi-driver\nMessage-ID: <1517574310-93096-5-git-send-email-beilei.xing@intel.com>\n\nThere's interrupt conflict when using DPDK and Linux i40e\non different ports of the same Ethernet controller, this\npatch fixes it by switching from IntN to Int0 if multiple\ndrivers are used.\n\nFixes: be6c228d4da3 (\"i40e: support Rx interrupt\")\nCc: stable@dpdk.org\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 93 +++++++++++++++++++++++++--------------\n drivers/net/i40e/i40e_ethdev.h | 10 +++--\n drivers/net/i40e/i40e_ethdev_vf.c | 4 +-\n 3 files changed, 68 insertions(+), 39 deletions(-)\n\ndiff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex ae0f31a..cae22e7 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -760,6 +760,23 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)\n \ti40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);\n }\n \n+static inline void i40e_config_automask(struct i40e_pf *pf)\n+{\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tuint32_t val;\n+\n+\t/* INTENA flag is not auto-cleared for interrupt */\n+\tval = I40E_READ_REG(hw, I40E_GLINT_CTL);\n+\tval |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |\n+\t\tI40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;\n+\n+\t/* If support multi-driver, PF will use INT0. */\n+\tif (!pf->support_multi_driver)\n+\t\tval |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;\n+\n+\tI40E_WRITE_REG(hw, I40E_GLINT_CTL, val);\n+}\n+\n #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808\n \n /*\n@@ -1077,6 +1094,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \t\treturn ret;\n \t}\n \n+\ti40e_config_automask(pf);\n+\n \t/*\n \t * To work around the NVM issue, initialize registers\n \t * for flexible payload and packet type of QinQ by\n@@ -1463,6 +1482,7 @@ __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,\n \tint i;\n \tuint32_t val;\n \tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n+\tstruct i40e_pf *pf = I40E_VSI_TO_PF(vsi);\n \n \t/* Bind all RX queues to allocated MSIX interrupt */\n \tfor (i = 0; i < nb_queue; i++) {\n@@ -1481,7 +1501,8 @@ __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,\n \t/* Write first RX queue to Link list register as the head element */\n \tif (vsi->type != I40E_VSI_SRIOV) {\n \t\tuint16_t interval =\n-\t\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);\n+\t\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL,\n+\t\t\t\t\t pf->support_multi_driver);\n \n \t\tif (msix_vect == I40E_MISC_VEC_ID) {\n \t\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,\n@@ -1539,7 +1560,6 @@ i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)\n \tuint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);\n \tuint16_t queue_idx = 0;\n \tint record = 0;\n-\tuint32_t val;\n \tint i;\n \n \tfor (i = 0; i < vsi->nb_qps; i++) {\n@@ -1547,13 +1567,6 @@ i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)\n \t\tI40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);\n \t}\n \n-\t/* INTENA flag is not auto-cleared for interrupt */\n-\tval = I40E_READ_REG(hw, I40E_GLINT_CTL);\n-\tval |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |\n-\t\tI40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |\n-\t\tI40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;\n-\tI40E_WRITE_REG(hw, I40E_GLINT_CTL, val);\n-\n \t/* VF bind interrupt */\n \tif (vsi->type == I40E_VSI_SRIOV) {\n \t\t__vsi_queues_bind_intr(vsi, msix_vect,\n@@ -1606,27 +1619,22 @@ i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)\n \tstruct rte_eth_dev *dev = vsi->adapter->eth_dev;\n \tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n-\tuint16_t interval = i40e_calc_itr_interval(\\\n-\t\tRTE_LIBRTE_I40E_ITR_INTERVAL);\n+\tstruct i40e_pf *pf = I40E_VSI_TO_PF(vsi);\n \tuint16_t msix_intr, i;\n \n-\tif (rte_intr_allow_others(intr_handle))\n+\tif (rte_intr_allow_others(intr_handle) || !pf->support_multi_driver)\n \t\tfor (i = 0; i < vsi->nb_msix; i++) {\n \t\t\tmsix_intr = vsi->msix_intr + i;\n \t\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),\n-\t\t\t\tI40E_PFINT_DYN_CTLN_INTENA_MASK |\n-\t\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n-\t\t\t\t(0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n-\t\t\t\t(interval <<\n-\t\t\t\t I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));\n+\t\t\t\t I40E_PFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\t\t I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t\t I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);\n \t\t}\n \telse\n \t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,\n \t\t\t I40E_PFINT_DYN_CTL0_INTENA_MASK |\n \t\t\t I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |\n-\t\t\t (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |\n-\t\t\t (interval <<\n-\t\t\t\tI40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));\n+\t\t\t I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);\n \n \tI40E_WRITE_FLUSH(hw);\n }\n@@ -1637,16 +1645,18 @@ i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)\n \tstruct rte_eth_dev *dev = vsi->adapter->eth_dev;\n \tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n+\tstruct i40e_pf *pf = I40E_VSI_TO_PF(vsi);\n \tuint16_t msix_intr, i;\n \n-\tif (rte_intr_allow_others(intr_handle))\n+\tif (rte_intr_allow_others(intr_handle) || !pf->support_multi_driver)\n \t\tfor (i = 0; i < vsi->nb_msix; i++) {\n \t\t\tmsix_intr = vsi->msix_intr + i;\n \t\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),\n-\t\t\t\t 0);\n+\t\t\t\t I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);\n \t\t}\n \telse\n-\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);\n+\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,\n+\t\t\t I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);\n \n \tI40E_WRITE_FLUSH(hw);\n }\n@@ -4618,16 +4628,28 @@ i40e_vsi_setup(struct i40e_pf *pf,\n \n \t/* VF has MSIX interrupt in VF range, don't allocate here */\n \tif (type == I40E_VSI_MAIN) {\n-\t\tret = i40e_res_pool_alloc(&pf->msix_pool,\n-\t\t\t\t\t RTE_MIN(vsi->nb_qps,\n-\t\t\t\t\t\t RTE_MAX_RXTX_INTR_VEC_ID));\n-\t\tif (ret < 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"VSI MAIN %d get heap failed %d\",\n-\t\t\t\t vsi->seid, ret);\n-\t\t\tgoto fail_queue_alloc;\n+\t\tif (pf->support_multi_driver) {\n+\t\t\t/* If support multi-driver, need to use INT0 instead of\n+\t\t\t * allocating from msix pool. The Msix pool is init from\n+\t\t\t * INT1, so it's OK just set msix_intr to 0 and nb_msix\n+\t\t\t * to 1 without calling i40e_res_pool_alloc.\n+\t\t\t */\n+\t\t\tvsi->msix_intr = 0;\n+\t\t\tvsi->nb_msix = 1;\n+\t\t} else {\n+\t\t\tret = i40e_res_pool_alloc(&pf->msix_pool,\n+\t\t\t\t\t\t RTE_MIN(vsi->nb_qps,\n+\t\t\t\t\t\t RTE_MAX_RXTX_INTR_VEC_ID));\n+\t\t\tif (ret < 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\t \"VSI MAIN %d get heap failed %d\",\n+\t\t\t\t\t vsi->seid, ret);\n+\t\t\t\tgoto fail_queue_alloc;\n+\t\t\t}\n+\t\t\tvsi->msix_intr = ret;\n+\t\t\tvsi->nb_msix = RTE_MIN(vsi->nb_qps,\n+\t\t\t\t\t RTE_MAX_RXTX_INTR_VEC_ID);\n \t\t}\n-\t\tvsi->msix_intr = ret;\n-\t\tvsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);\n \t} else if (type != I40E_VSI_SRIOV) {\n \t\tret = i40e_res_pool_alloc(&pf->msix_pool, 1);\n \t\tif (ret < 0) {\n@@ -5540,7 +5562,8 @@ void\n i40e_pf_disable_irq0(struct i40e_hw *hw)\n {\n \t/* Disable all interrupt types */\n-\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);\n+\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,\n+\t\t I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);\n \tI40E_WRITE_FLUSH(hw);\n }\n \n@@ -9861,10 +9884,12 @@ i40e_dev_get_dcb_info(struct rte_eth_dev *dev,\n static int\n i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n {\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint16_t interval =\n-\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);\n+\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL,\n+\t\t\t\t pf->support_multi_driver);\n \tuint16_t msix_intr;\n \n \tmsix_intr = intr_handle->intr_vec[queue_id];\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 82d5501..77a4466 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -720,10 +720,14 @@ i40e_align_floor(int n)\n }\n \n static inline uint16_t\n-i40e_calc_itr_interval(int16_t interval)\n+i40e_calc_itr_interval(int16_t interval, bool is_multi_drv)\n {\n-\tif (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)\n-\t\tinterval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;\n+\tif (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) {\n+\t\tif (is_multi_drv)\n+\t\t\tinterval = I40E_QUEUE_ITR_INTERVAL_MAX;\n+\t\telse\n+\t\t\tinterval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;\n+\t}\n \n \t/* Convert to hardware count, as writing each 1 represents 2 us */\n \treturn interval / 2;\ndiff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c\nindex 1686914..618c717 100644\n--- a/drivers/net/i40e/i40e_ethdev_vf.c\n+++ b/drivers/net/i40e/i40e_ethdev_vf.c\n@@ -1246,7 +1246,7 @@ i40evf_init_vf(struct rte_eth_dev *dev)\n \tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n \tstruct ether_addr *p_mac_addr;\n \tuint16_t interval =\n-\t\ti40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);\n+\t\ti40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX, 0);\n \n \tvf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tvf->dev_data = dev->data;\n@@ -1986,7 +1986,7 @@ i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n \tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint16_t interval =\n-\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);\n+\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 0);\n \tuint16_t msix_intr;\n \n \tmsix_intr = intr_handle->intr_vec[queue_id];\n", "prefixes": [ "dpdk-dev" ] }