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GET /api/patches/34932/?format=api
{ "id": 34932, "url": "http://patches.dpdk.org/api/patches/34932/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1517791895-3061-5-git-send-email-xiangxia.m.yue@gmail.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1517791895-3061-5-git-send-email-xiangxia.m.yue@gmail.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1517791895-3061-5-git-send-email-xiangxia.m.yue@gmail.com", "date": "2018-02-05T00:51:34", "name": "[dpdk-dev,v3,4/5] net/ixgbevf: save IXGBE_VTEIMS to intr->mask for performance.", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "dda39344536cd6312dd6dc08a547f79d24261b5d", "submitter": { "id": 834, "url": "http://patches.dpdk.org/api/people/834/?format=api", "name": "Tonghao Zhang", "email": "xiangxia.m.yue@gmail.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1517791895-3061-5-git-send-email-xiangxia.m.yue@gmail.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/34932/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/34932/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6D77E1B208;\n\tMon, 5 Feb 2018 01:51:59 +0100 (CET)", "from mail-pg0-f65.google.com (mail-pg0-f65.google.com\n\t[74.125.83.65]) by dpdk.org (Postfix) with ESMTP id E252F1B2A6\n\tfor <dev@dpdk.org>; Mon, 5 Feb 2018 01:51:57 +0100 (CET)", "by mail-pg0-f65.google.com with SMTP id h2so2985462pgq.5\n\tfor <dev@dpdk.org>; Sun, 04 Feb 2018 16:51:57 -0800 (PST)", "from local.opencloud.tech.localdomain ([23.102.225.250])\n\tby smtp.gmail.com with ESMTPSA id\n\tb84sm9432835pfj.11.2018.02.04.16.51.54\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 04 Feb 2018 16:51:56 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=cpit4M2iB64PRIwtIiqqCWbSBMOu8jJHc3wjlqSDH38=;\n\tb=hUnKQHW+lbRJjNuno95QcUypiKD2cVOoz3c1/s4kplTf3H/T/sAXI2TlerdUe0kb3T\n\tt8XIQ+rM8EWpz3Xee44RA5Pyj1jQiYaQ4KJ+mbOFLTnNXvbbStC26vbWts6131/tbDox\n\tIhG/IVTwMSQwsddhWFMKdfEED6K+L7NfcDs6uFnr0igZSIJnV1fknf0K3I5ZNxXqGpS1\n\tu3L7JJHR+TOCijCVmlKEYiwE7xk01nSQc9kEI9CTZPntnPQDIKII+SvCpUeXHpXwiXNY\n\t5PeNqXR79k+SyeQ/ZyRtA2L31DJbH+g0r8bHnhIzMi1UlNmRQ20n91TRFORNXyJKGQOW\n\tq+yw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=cpit4M2iB64PRIwtIiqqCWbSBMOu8jJHc3wjlqSDH38=;\n\tb=Cq9aCB/rRs+tdQkzRyMr2MGqRreBKjNFY81hknr9ErhyJZzSGsj4t8xxQfFiK6k2Qe\n\tO2Avt6DgSlX+cOXBFzU/tiDl237ykNZ6TonOShp58SIy9rHb27QHx2M4vgoQjeRiO+HE\n\tE4dRzX4AUw+J9HPPTj6e0dYOnxStXYgT2mRCum+7uaq/alS7nlW58IITFoaz1dRUvYYO\n\tFZQjlaWuqcXFYEP0QmtF0mjB2YK9H7naBaUMwUo7fA1ClqhuEMZFV/ZCRUeRdjon/LYY\n\tZQP0ZRZWubMSjwewDJXL0ZMsyQ7boqtMWk4iQX4ZQUzU73hiwjwqEJSZmg8UjfZP31V4\n\ttLCw==", "X-Gm-Message-State": "AKwxytciC3xbZJz5dkJVJmhxdewU+f6b5u8mFBKjhMPrhA8pqiCbkNqg\n\tCY7t9hY2X9FSxK2cr02uLro=", "X-Google-Smtp-Source": "AH8x224dbIYTcZs6n5vesRyN1chuxegUSjG0Nt1REYcc5TkxDpgIVMZ3tFVAiYLrCQe6VJEGaG7BSA==", "X-Received": "by 10.101.68.138 with SMTP id l10mr27330257pgq.150.1517791917106;\n\tSun, 04 Feb 2018 16:51:57 -0800 (PST)", "From": "xiangxia.m.yue@gmail.com", "To": "beilei.xing@intel.com, wei.dai@intel.com, helin.zhang@intel.com,\n\twenzhuo.lu@intel.com", "Cc": "dev@dpdk.org,\n\tTonghao Zhang <xiangxia.m.yue@gmail.com>", "Date": "Sun, 4 Feb 2018 16:51:34 -0800", "Message-Id": "<1517791895-3061-5-git-send-email-xiangxia.m.yue@gmail.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1517791895-3061-1-git-send-email-xiangxia.m.yue@gmail.com>", "References": "<1517791895-3061-1-git-send-email-xiangxia.m.yue@gmail.com>", "Subject": "[dpdk-dev] [PATCH v3 4/5] net/ixgbevf: save IXGBE_VTEIMS to\n\tintr->mask for performance.", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tonghao Zhang <xiangxia.m.yue@gmail.com>\n\nIf dpdk APPs call the rte_eth_dev_rx_intr_enable or\nrte_eth_dev_rx_intr_disable frequently, and ixgbe vf will read\nthe IXGBE_VTEIMS register everytime. The patch saves the IXGBE_VTEIMS\nto mask to avoid read frequently.\n\nSigned-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>\nAcked-by: Beilei Xing <beilei.xing@intel.com>\nAcked-by: Wei Dai <wei.dai@intel.com>\n---\n drivers/net/ixgbe/ixgbe_ethdev.c | 55 +++++++++++++++++++++++++---------------\n 1 file changed, 35 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c\nindex 0ea8fe8..7928144 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.c\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.c\n@@ -238,8 +238,8 @@ static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,\n static void ixgbevf_dev_stop(struct rte_eth_dev *dev);\n static void ixgbevf_dev_close(struct rte_eth_dev *dev);\n static int ixgbevf_dev_reset(struct rte_eth_dev *dev);\n-static void ixgbevf_intr_disable(struct ixgbe_hw *hw);\n-static void ixgbevf_intr_enable(struct ixgbe_hw *hw);\n+static void ixgbevf_intr_disable(struct rte_eth_dev *dev);\n+static void ixgbevf_intr_enable(struct rte_eth_dev *dev);\n static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,\n \t\tstruct rte_eth_stats *stats);\n static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);\n@@ -1633,7 +1633,7 @@ static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)\n \tixgbevf_dev_stats_reset(eth_dev);\n \n \t/* Disable the interrupts for VF */\n-\tixgbevf_intr_disable(hw);\n+\tixgbevf_intr_disable(eth_dev);\n \n \thw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */\n \tdiag = hw->mac.ops.reset_hw(hw);\n@@ -1702,7 +1702,7 @@ static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)\n \trte_intr_callback_register(intr_handle,\n \t\t\t\t ixgbevf_dev_interrupt_handler, eth_dev);\n \trte_intr_enable(intr_handle);\n-\tixgbevf_intr_enable(hw);\n+\tixgbevf_intr_enable(eth_dev);\n \n \tPMD_INIT_LOG(DEBUG, \"port %d vendorID=0x%x deviceID=0x%x mac.type=%s\",\n \t\t eth_dev->data->port_id, pci_dev->id.vendor_id,\n@@ -1735,7 +1735,7 @@ static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)\n \teth_dev->tx_pkt_burst = NULL;\n \n \t/* Disable the interrupts for VF */\n-\tixgbevf_intr_disable(hw);\n+\tixgbevf_intr_disable(eth_dev);\n \n \trte_free(eth_dev->data->mac_addrs);\n \teth_dev->data->mac_addrs = NULL;\n@@ -4921,19 +4921,32 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\n * Virtual Function operations\n */\n static void\n-ixgbevf_intr_disable(struct ixgbe_hw *hw)\n+ixgbevf_intr_disable(struct rte_eth_dev *dev)\n {\n+\tstruct ixgbe_interrupt *intr =\n+\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n+\tstruct ixgbe_hw *hw =\n+\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n \tPMD_INIT_FUNC_TRACE();\n \n \t/* Clear interrupt mask to stop from interrupts being generated */\n \tIXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);\n \n \tIXGBE_WRITE_FLUSH(hw);\n+\n+\t/* Clear mask value. */\n+\tintr->mask = 0;\n }\n \n static void\n-ixgbevf_intr_enable(struct ixgbe_hw *hw)\n+ixgbevf_intr_enable(struct rte_eth_dev *dev)\n {\n+\tstruct ixgbe_interrupt *intr =\n+\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n+\tstruct ixgbe_hw *hw =\n+\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n \tPMD_INIT_FUNC_TRACE();\n \n \t/* VF enable interrupt autoclean */\n@@ -4942,6 +4955,9 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\n \tIXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);\n \n \tIXGBE_WRITE_FLUSH(hw);\n+\n+\t/* Save IXGBE_VTEIMS value to mask. */\n+\tintr->mask = IXGBE_VF_IRQ_ENABLE_MASK;\n }\n \n static int\n@@ -5067,7 +5083,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\n \trte_intr_enable(intr_handle);\n \n \t/* Re-enable interrupt for VF */\n-\tixgbevf_intr_enable(hw);\n+\tixgbevf_intr_enable(dev);\n \n \treturn 0;\n }\n@@ -5081,7 +5097,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\n \n \tPMD_INIT_FUNC_TRACE();\n \n-\tixgbevf_intr_disable(hw);\n+\tixgbevf_intr_disable(dev);\n \n \thw->adapter_stopped = 1;\n \tixgbe_stop_adapter(hw);\n@@ -5579,17 +5595,17 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)\n {\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n-\tuint32_t mask;\n+\tstruct ixgbe_interrupt *intr =\n+\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n \tstruct ixgbe_hw *hw =\n \t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint32_t vec = IXGBE_MISC_VEC_ID;\n \n-\tmask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);\n \tif (rte_intr_allow_others(intr_handle))\n \t\tvec = IXGBE_RX_VEC_START;\n-\tmask |= (1 << vec);\n+\tintr->mask |= (1 << vec);\n \tRTE_SET_USED(queue_id);\n-\tIXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);\n+\tIXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);\n \n \trte_intr_enable(intr_handle);\n \n@@ -5599,19 +5615,19 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)\n static int\n ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n {\n-\tuint32_t mask;\n+\tstruct ixgbe_interrupt *intr =\n+\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n \tstruct ixgbe_hw *hw =\n \t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tuint32_t vec = IXGBE_MISC_VEC_ID;\n \n-\tmask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);\n \tif (rte_intr_allow_others(intr_handle))\n \t\tvec = IXGBE_RX_VEC_START;\n-\tmask &= ~(1 << vec);\n+\tintr->mask &= ~(1 << vec);\n \tRTE_SET_USED(queue_id);\n-\tIXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);\n+\tIXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);\n \n \treturn 0;\n }\n@@ -8172,7 +8188,7 @@ static void ixgbevf_mbx_process(struct rte_eth_dev *dev)\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct ixgbe_interrupt *intr =\n \t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n-\tixgbevf_intr_disable(hw);\n+\tixgbevf_intr_disable(dev);\n \n \t/* read-on-clear nic registers here */\n \teicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);\n@@ -8189,7 +8205,6 @@ static void ixgbevf_mbx_process(struct rte_eth_dev *dev)\n static int\n ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)\n {\n-\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct ixgbe_interrupt *intr =\n \t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n \n@@ -8198,7 +8213,7 @@ static void ixgbevf_mbx_process(struct rte_eth_dev *dev)\n \t\tintr->flags &= ~IXGBE_FLAG_MAILBOX;\n \t}\n \n-\tixgbevf_intr_enable(hw);\n+\tixgbevf_intr_enable(dev);\n \n \treturn 0;\n }\n", "prefixes": [ "dpdk-dev", "v3", "4/5" ] }