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GET /api/patches/34917/?format=api
{ "id": 34917, "url": "http://patches.dpdk.org/api/patches/34917/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/883b5307bbd3f437af51a5205bf5ae5ded44c971.1517685185.git.rahul.lakkireddy@chelsio.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<883b5307bbd3f437af51a5205bf5ae5ded44c971.1517685185.git.rahul.lakkireddy@chelsio.com>", "list_archive_url": "https://inbox.dpdk.org/dev/883b5307bbd3f437af51a5205bf5ae5ded44c971.1517685185.git.rahul.lakkireddy@chelsio.com", "date": "2018-02-04T06:06:12", "name": "[dpdk-dev,7/7] cxgbe: rework and use 32-bit port capability", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "08b395977087e053fa5882dbef9de722c93a98f7", "submitter": { "id": 241, "url": "http://patches.dpdk.org/api/people/241/?format=api", "name": "Rahul Lakkireddy", "email": "rahul.lakkireddy@chelsio.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/883b5307bbd3f437af51a5205bf5ae5ded44c971.1517685185.git.rahul.lakkireddy@chelsio.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/34917/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/34917/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A82301B1A5;\n\tSun, 4 Feb 2018 07:06:55 +0100 (CET)", "from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8])\n\tby dpdk.org (Postfix) with ESMTP id E980F2BF5\n\tfor <dev@dpdk.org>; Sun, 4 Feb 2018 07:06:53 +0100 (CET)", "from localhost (scalar.blr.asicdesigners.com [10.193.185.94])\n\tby stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id w1466o1x030195; \n\tSat, 3 Feb 2018 22:06:51 -0800" ], "From": "Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>", "To": "dev@dpdk.org", "Cc": "kumaras@chelsio.com, surendra@chelsio.com, nirranjan@chelsio.com,\n\tindranil@chelsio.com", "Date": "Sun, 4 Feb 2018 11:36:12 +0530", "Message-Id": "<883b5307bbd3f437af51a5205bf5ae5ded44c971.1517685185.git.rahul.lakkireddy@chelsio.com>", "X-Mailer": "git-send-email 2.5.3", "In-Reply-To": [ "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>", "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>" ], "References": [ "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>", "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>" ], "Subject": "[dpdk-dev] [PATCH 7/7] cxgbe: rework and use 32-bit port capability", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The new code uses the new 32-bit Port Capabilities exclusively and\nonly translates to/from the old 16-bit Port Capabilities at the last\npoint possible when talking to older Firmware.\n\nFor the old versus new Firmware issue, we use the new FW_PARAMS_CMD[PFVF,\nCAPS32] command to tell the Firmware that we want Asynchronous Port Status\nupdates to use the new 32-bit version of the Port Information message. If\nwe get an error, we know we're dealing with older Firmware, and if not,\nwe'll start getting th new 32-bit Port Capability message formats.\n\nAlso, refactor t4_handle_fw_rpl() to handle new 32-bit Port Capability\nreplies from firmware in t4_handle_get_port_info().\n\nOriginal work by Surendra Mobiya <surendra@chelsio.com>\n\nSigned-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>\nSigned-off-by: Kumar Sanghvi <kumaras@chelsio.com>\n---\n doc/guides/nics/cxgbe.rst | 10 +-\n drivers/net/cxgbe/base/common.h | 8 +\n drivers/net/cxgbe/base/t4_hw.c | 356 +++++++++++++++++++++++---------\n drivers/net/cxgbe/base/t4fw_interface.h | 47 ++++-\n 4 files changed, 323 insertions(+), 98 deletions(-)", "diff": "diff --git a/doc/guides/nics/cxgbe.rst b/doc/guides/nics/cxgbe.rst\nindex 6126167c5..c4afe8678 100644\n--- a/doc/guides/nics/cxgbe.rst\n+++ b/doc/guides/nics/cxgbe.rst\n@@ -82,7 +82,7 @@ Supported Chelsio T6 NICs\n Prerequisites\n -------------\n \n-- Requires firmware version **1.16.43.0** and higher. Visit\n+- Requires firmware version **1.17.14.0** and higher. Visit\n `Chelsio Download Center <http://service.chelsio.com>`_ to get latest firmware\n bundled with the latest Chelsio Unified Wire package.\n \n@@ -210,7 +210,7 @@ Unified Wire package for Linux operating system are as follows:\n \n .. code-block:: console\n \n- firmware-version: 1.16.43.0, TP 0.1.4.9\n+ firmware-version: 1.17.14.0, TP 0.1.4.9\n \n Running testpmd\n ~~~~~~~~~~~~~~~\n@@ -268,7 +268,7 @@ devices managed by librte_pmd_cxgbe in Linux operating system.\n EAL: PCI memory mapped at 0x7fd7c0200000\n EAL: PCI memory mapped at 0x7fd77cdfd000\n EAL: PCI memory mapped at 0x7fd7c10b7000\n- PMD: rte_cxgbe_pmd: fw: 1.16.43.0, TP: 0.1.4.9\n+ PMD: rte_cxgbe_pmd: fw: 1.17.14.0, TP: 0.1.4.9\n PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter\n Interactive-mode selected\n Configuring Port 0 (socket 0)\n@@ -352,7 +352,7 @@ Unified Wire package for FreeBSD operating system are as follows:\n \n .. code-block:: console\n \n- dev.t5nex.0.firmware_version: 1.16.43.0\n+ dev.t5nex.0.firmware_version: 1.17.14.0\n \n Running testpmd\n ~~~~~~~~~~~~~~~\n@@ -470,7 +470,7 @@ devices managed by librte_pmd_cxgbe in FreeBSD operating system.\n EAL: PCI memory mapped at 0x8007ec000\n EAL: PCI memory mapped at 0x842800000\n EAL: PCI memory mapped at 0x80086c000\n- PMD: rte_cxgbe_pmd: fw: 1.16.43.0, TP: 0.1.4.9\n+ PMD: rte_cxgbe_pmd: fw: 1.17.14.0, TP: 0.1.4.9\n PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter\n Interactive-mode selected\n Configuring Port 0 (socket 0)\ndiff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h\nindex 98886288c..365e9e692 100644\n--- a/drivers/net/cxgbe/base/common.h\n+++ b/drivers/net/cxgbe/base/common.h\n@@ -239,6 +239,7 @@ struct adapter_params {\n \tstruct arch_specific_params arch; /* chip specific params */\n \n \tbool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */\n+\tu8 fw_caps_support;\t\t /* 32-bit Port Capabilities */\n };\n \n /* Firmware Port Capabilities types.\n@@ -246,6 +247,12 @@ struct adapter_params {\n typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */\n typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */\n \n+enum fw_caps {\n+\tFW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */\n+\tFW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */\n+\tFW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */\n+};\n+\n struct link_config {\n \tfw_port_cap32_t pcaps; /* link capabilities */\n \tfw_port_cap32_t acaps; /* advertised capabilities */\n@@ -265,6 +272,7 @@ struct link_config {\n \tunsigned char autoneg; /* autonegotiating? */\n \n \tunsigned char link_ok; /* link up? */\n+\tunsigned char link_down_rc; /* link down reason */\n };\n \n #include \"adapter.h\"\ndiff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c\nindex 46b296a9d..c66e2a6f7 100644\n--- a/drivers/net/cxgbe/base/t4_hw.c\n+++ b/drivers/net/cxgbe/base/t4_hw.c\n@@ -2791,6 +2791,43 @@ void t4_dump_version_info(struct adapter *adapter)\n \n #define ADVERT_MASK (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) | \\\n \t\t FW_PORT_CAP32_ANEG)\n+/**\n+ * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits\n+ * @caps16: a 16-bit Port Capabilities value\n+ *\n+ * Returns the equivalent 32-bit Port Capabilities value.\n+ */\n+static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)\n+{\n+\tfw_port_cap32_t caps32 = 0;\n+\n+#define CAP16_TO_CAP32(__cap) \\\n+\tdo { \\\n+\t\tif (caps16 & FW_PORT_CAP_##__cap) \\\n+\t\t\tcaps32 |= FW_PORT_CAP32_##__cap; \\\n+\t} while (0)\n+\n+\tCAP16_TO_CAP32(SPEED_100M);\n+\tCAP16_TO_CAP32(SPEED_1G);\n+\tCAP16_TO_CAP32(SPEED_25G);\n+\tCAP16_TO_CAP32(SPEED_10G);\n+\tCAP16_TO_CAP32(SPEED_40G);\n+\tCAP16_TO_CAP32(SPEED_100G);\n+\tCAP16_TO_CAP32(FC_RX);\n+\tCAP16_TO_CAP32(FC_TX);\n+\tCAP16_TO_CAP32(ANEG);\n+\tCAP16_TO_CAP32(MDIX);\n+\tCAP16_TO_CAP32(MDIAUTO);\n+\tCAP16_TO_CAP32(FEC_RS);\n+\tCAP16_TO_CAP32(FEC_BASER_RS);\n+\tCAP16_TO_CAP32(802_3_PAUSE);\n+\tCAP16_TO_CAP32(802_3_ASM_DIR);\n+\n+#undef CAP16_TO_CAP32\n+\n+\treturn caps32;\n+}\n+\n /**\n * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits\n * @caps32: a 32-bit Port Capabilities value\n@@ -2900,6 +2937,7 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,\n \t\t struct link_config *lc)\n {\n \tunsigned int fw_mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);\n+\tunsigned int fw_caps = adap->params.fw_caps_support;\n \tfw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;\n \tstruct fw_port_cmd cmd;\n \n@@ -2941,9 +2979,15 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,\n \t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_EXEC |\n \t\t\t\t V_FW_PORT_CMD_PORTID(port));\n \tcmd.action_to_len16 =\n-\t\tcpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |\n+\t\tcpu_to_be32(V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16 ?\n+\t\t\t\t\t\t FW_PORT_ACTION_L1_CFG :\n+\t\t\t\t\t\t FW_PORT_ACTION_L1_CFG32) |\n \t\t\t FW_LEN16(cmd));\n-\tcmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));\n+\n+\tif (fw_caps == FW_CAPS16)\n+\t\tcmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));\n+\telse\n+\t\tcmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);\n \n \treturn t4_wr_mbox(adap, mbox, &cmd, sizeof(cmd), NULL);\n }\n@@ -4278,6 +4322,31 @@ int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,\n \treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n }\n \n+/**\n+ * t4_link_down_rc_str - return a string for a Link Down Reason Code\n+ * @link_down_rc: Link Down Reason Code\n+ *\n+ * Returns a string representation of the Link Down Reason Code.\n+ */\n+static const char *t4_link_down_rc_str(unsigned char link_down_rc)\n+{\n+\tstatic const char * const reason[] = {\n+\t\t\"Link Down\",\n+\t\t\"Remote Fault\",\n+\t\t\"Auto-negotiation Failure\",\n+\t\t\"Reserved\",\n+\t\t\"Insufficient Airflow\",\n+\t\t\"Unable To Determine Reason\",\n+\t\t\"No RX Signal Detected\",\n+\t\t\"Reserved\",\n+\t};\n+\n+\tif (link_down_rc >= ARRAY_SIZE(reason))\n+\t\treturn \"Bad Reason Code\";\n+\n+\treturn reason[link_down_rc];\n+}\n+\n /* Return the highest speed set in the port capabilities, in Mb/s. */\n static unsigned int fwcap_to_speed(fw_port_cap32_t caps)\n {\n@@ -4300,6 +4369,122 @@ static unsigned int fwcap_to_speed(fw_port_cap32_t caps)\n \treturn 0;\n }\n \n+/**\n+ * t4_handle_get_port_info - process a FW reply message\n+ * @pi: the port info\n+ * @rpl: start of the FW message\n+ *\n+ * Processes a GET_PORT_INFO FW reply message.\n+ */\n+static void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)\n+{\n+\tconst struct fw_port_cmd *cmd = (const void *)rpl;\n+\tint action = G_FW_PORT_CMD_ACTION(be32_to_cpu(cmd->action_to_len16));\n+\tfw_port_cap32_t pcaps, acaps, linkattr;\n+\tstruct link_config *lc = &pi->link_cfg;\n+\tstruct adapter *adapter = pi->adapter;\n+\tenum fw_port_module_type mod_type;\n+\tenum fw_port_type port_type;\n+\tunsigned int speed, fc, fec;\n+\tint link_ok, linkdnrc;\n+\n+\t/* Extract the various fields from the Port Information message.\n+\t */\n+\tswitch (action) {\n+\tcase FW_PORT_ACTION_GET_PORT_INFO: {\n+\t\tu32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);\n+\n+\t\tlink_ok = (lstatus & F_FW_PORT_CMD_LSTATUS) != 0;\n+\t\tlinkdnrc = G_FW_PORT_CMD_LINKDNRC(lstatus);\n+\t\tport_type = G_FW_PORT_CMD_PTYPE(lstatus);\n+\t\tmod_type = G_FW_PORT_CMD_MODTYPE(lstatus);\n+\t\tpcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));\n+\t\tacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));\n+\n+\t\t/* Unfortunately the format of the Link Status in the old\n+\t\t * 16-bit Port Information message isn't the same as the\n+\t\t * 16-bit Port Capabilities bitfield used everywhere else ...\n+\t\t */\n+\t\tlinkattr = 0;\n+\t\tif (lstatus & F_FW_PORT_CMD_RXPAUSE)\n+\t\t\tlinkattr |= FW_PORT_CAP32_FC_RX;\n+\t\tif (lstatus & F_FW_PORT_CMD_TXPAUSE)\n+\t\t\tlinkattr |= FW_PORT_CAP32_FC_TX;\n+\t\tif (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))\n+\t\t\tlinkattr |= FW_PORT_CAP32_SPEED_100M;\n+\t\tif (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))\n+\t\t\tlinkattr |= FW_PORT_CAP32_SPEED_1G;\n+\t\tif (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))\n+\t\t\tlinkattr |= FW_PORT_CAP32_SPEED_10G;\n+\t\tif (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))\n+\t\t\tlinkattr |= FW_PORT_CAP32_SPEED_25G;\n+\t\tif (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))\n+\t\t\tlinkattr |= FW_PORT_CAP32_SPEED_40G;\n+\t\tif (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))\n+\t\t\tlinkattr |= FW_PORT_CAP32_SPEED_100G;\n+\n+\t\tbreak;\n+\t\t}\n+\n+\tcase FW_PORT_ACTION_GET_PORT_INFO32: {\n+\t\tu32 lstatus32 =\n+\t\t\tbe32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);\n+\n+\t\tlink_ok = (lstatus32 & F_FW_PORT_CMD_LSTATUS32) != 0;\n+\t\tlinkdnrc = G_FW_PORT_CMD_LINKDNRC32(lstatus32);\n+\t\tport_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);\n+\t\tmod_type = G_FW_PORT_CMD_MODTYPE32(lstatus32);\n+\t\tpcaps = be32_to_cpu(cmd->u.info32.pcaps32);\n+\t\tacaps = be32_to_cpu(cmd->u.info32.acaps32);\n+\t\tlinkattr = be32_to_cpu(cmd->u.info32.linkattr32);\n+\t\tbreak;\n+\t\t}\n+\n+\tdefault:\n+\t\tdev_warn(adapter, \"Handle Port Information: Bad Command/Action %#x\\n\",\n+\t\t\t be32_to_cpu(cmd->action_to_len16));\n+\t\treturn;\n+\t}\n+\n+\tfec = fwcap_to_cc_fec(acaps);\n+\n+\tfc = fwcap_to_cc_pause(linkattr);\n+\tspeed = fwcap_to_speed(linkattr);\n+\n+\tif (mod_type != pi->mod_type) {\n+\t\tlc->auto_fec = fec;\n+\t\tpi->port_type = port_type;\n+\t\tpi->mod_type = mod_type;\n+\t\tt4_os_portmod_changed(adapter, pi->port_id);\n+\t}\n+\tif (link_ok != lc->link_ok || speed != lc->speed ||\n+\t fc != lc->fc || fec != lc->fec) { /* something changed */\n+\t\tif (!link_ok && lc->link_ok) {\n+\t\t\tlc->link_down_rc = linkdnrc;\n+\t\t\tdev_warn(adap, \"Port %d link down, reason: %s\\n\",\n+\t\t\t\t pi->tx_chan, t4_link_down_rc_str(linkdnrc));\n+\t\t}\n+\t\tlc->link_ok = link_ok;\n+\t\tlc->speed = speed;\n+\t\tlc->fc = fc;\n+\t\tlc->fec = fec;\n+\t\tlc->pcaps = pcaps;\n+\t\tlc->acaps = acaps & ADVERT_MASK;\n+\n+\t\tif (lc->acaps & FW_PORT_CAP32_ANEG) {\n+\t\t\tlc->autoneg = AUTONEG_ENABLE;\n+\t\t} else {\n+\t\t\t/* When Autoneg is disabled, user needs to set\n+\t\t\t * single speed.\n+\t\t\t * Similar to cxgb4_ethtool.c: set_link_ksettings\n+\t\t\t */\n+\t\t\tlc->acaps = 0;\n+\t\t\tlc->requested_speed = fwcap_to_speed(acaps);\n+\t\t\tlc->autoneg = AUTONEG_DISABLE;\n+\t\t}\n+\t}\n+}\n+\n /**\n * t4_handle_fw_rpl - process a FW reply message\n * @adap: the adapter\n@@ -4321,83 +4506,21 @@ int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)\n \tunsigned int action =\n \t\tG_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));\n \n-\tif (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {\n+\tif (opcode == FW_PORT_CMD &&\n+\t (action == FW_PORT_ACTION_GET_PORT_INFO ||\n+\t action == FW_PORT_ACTION_GET_PORT_INFO32)) {\n \t\t/* link/module state change message */\n-\t\tunsigned int speed = 0, fc = 0, i;\n \t\tint chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));\n \t\tstruct port_info *pi = NULL;\n-\t\tstruct link_config *lc;\n-\t\tu32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);\n-\t\tint link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;\n-\t\tu32 mod = G_FW_PORT_CMD_MODTYPE(stat);\n-\t\tunsigned int fec;\n-\n-\t\tfc = fwcap_to_cc_pause(stat);\n-\t\tfec = fwcap_to_cc_fec(stat);\n-\n-\t\tif (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))\n-\t\t\tspeed = ETH_SPEED_NUM_100M;\n-\t\telse if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))\n-\t\t\tspeed = ETH_SPEED_NUM_1G;\n-\t\telse if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))\n-\t\t\tspeed = ETH_SPEED_NUM_10G;\n-\t\telse if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))\n-\t\t\tspeed = ETH_SPEED_NUM_25G;\n-\t\telse if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))\n-\t\t\tspeed = ETH_SPEED_NUM_40G;\n-\t\telse if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))\n-\t\t\tspeed = ETH_SPEED_NUM_100G;\n+\t\tint i;\n \n \t\tfor_each_port(adap, i) {\n \t\t\tpi = adap2pinfo(adap, i);\n \t\t\tif (pi->tx_chan == chan)\n \t\t\t\tbreak;\n \t\t}\n-\t\tlc = &pi->link_cfg;\n \n-\t\tif (mod != pi->mod_type) {\n-\t\t\tlc->auto_fec = fec;\n-\t\t\tpi->mod_type = mod;\n-\t\t\tt4_os_portmod_changed(adap, i);\n-\t\t}\n-\t\tif (link_ok != lc->link_ok || speed != lc->speed ||\n-\t\t fc != lc->fc || fec != lc->fec) { /* something changed */\n-\t\t\tif (!link_ok && lc->link_ok) {\n-\t\t\t\tstatic const char * const reason[] = {\n-\t\t\t\t\t\"Link Down\",\n-\t\t\t\t\t\"Remote Fault\",\n-\t\t\t\t\t\"Auto-negotiation Failure\",\n-\t\t\t\t\t\"Reserved\",\n-\t\t\t\t\t\"Insufficient Airflow\",\n-\t\t\t\t\t\"Unable To Determine Reason\",\n-\t\t\t\t\t\"No RX Signal Detected\",\n-\t\t\t\t\t\"Reserved\",\n-\t\t\t\t};\n-\t\t\t\tunsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);\n-\n-\t\t\t\tdev_warn(adap, \"Port %d link down, reason: %s\\n\",\n-\t\t\t\t\t chan, reason[rc]);\n-\t\t\t}\n-\t\t\tlc->link_ok = link_ok;\n-\t\t\tlc->speed = speed;\n-\t\t\tlc->fc = fc;\n-\t\t\tlc->fec = fec;\n-\t\t\tlc->pcaps = be16_to_cpu(p->u.info.pcap);\n-\t\t\tlc->acaps = be16_to_cpu(p->u.info.acap) & ADVERT_MASK;\n-\t\t\tif (lc->acaps & FW_PORT_CAP32_ANEG) {\n-\t\t\t\tlc->autoneg = AUTONEG_ENABLE;\n-\t\t\t} else {\n-\t\t\t\t/* When Autoneg is disabled, user needs to set\n-\t\t\t\t * single speed.\n-\t\t\t\t */\n-\t\t\t\tlc->acaps = 0;\n-\t\t\t\tlc->requested_speed =\n-\t\t\t\t\tbe16_to_cpu(p->u.info.acap);\n-\t\t\t\tlc->requested_speed =\n-\t\t\t\t\tfwcap_to_speed(lc->requested_speed);\n-\t\t\t\tlc->autoneg = AUTONEG_DISABLE;\n-\t\t\t}\n-\t\t}\n+\t\tt4_handle_get_port_info(pi, rpl);\n \t} else {\n \t\tdev_warn(adap, \"Unknown firmware reply %d\\n\", opcode);\n \t\treturn -EINVAL;\n@@ -4426,8 +4549,8 @@ void t4_reset_link_config(struct adapter *adap, int idx)\n * Initializes the SW state maintained for each link, including the link's\n * capabilities and default speed/flow-control/autonegotiation settings.\n */\n-static void init_link_config(struct link_config *lc, unsigned int pcaps,\n-\t\t\t unsigned int acaps)\n+static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,\n+\t\t\t fw_port_cap32_t acaps)\n {\n \tlc->pcaps = pcaps;\n \tlc->requested_speed = 0;\n@@ -4969,46 +5092,95 @@ int t4_init_rss_mode(struct adapter *adap, int mbox)\n \n int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)\n {\n-\tu8 addr[6];\n+\tunsigned int fw_caps = adap->params.fw_caps_support;\n+\tfw_port_cap32_t pcaps, acaps;\n+\tenum fw_port_type port_type;\n+\tstruct fw_port_cmd cmd;\n \tint ret, i, j = 0;\n-\tstruct fw_port_cmd c;\n+\tint mdio_addr;\n+\tu32 action;\n+\tu8 addr[6];\n \n-\tmemset(&c, 0, sizeof(c));\n+\tmemset(&cmd, 0, sizeof(cmd));\n \n \tfor_each_port(adap, i) {\n+\t\tstruct port_info *pi = adap2pinfo(adap, i);\n \t\tunsigned int rss_size = 0;\n-\t\tstruct port_info *p = adap2pinfo(adap, i);\n \n \t\twhile ((adap->params.portvec & (1 << j)) == 0)\n \t\t\tj++;\n \n-\t\tc.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |\n-\t\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_READ |\n-\t\t\t\t\t V_FW_PORT_CMD_PORTID(j));\n-\t\tc.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(\n-\t\t\t\t\t\tFW_PORT_ACTION_GET_PORT_INFO) |\n-\t\t\t\t\t\tFW_LEN16(c));\n-\t\tret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);\n+\t\t/* If we haven't yet determined whether we're talking to\n+\t\t * Firmware which knows the new 32-bit Port Capabilities, it's\n+\t\t * time to find out now. This will also tell new Firmware to\n+\t\t * send us Port Status Updates using the new 32-bit Port\n+\t\t * Capabilities version of the Port Information message.\n+\t\t */\n+\t\tif (fw_caps == FW_CAPS_UNKNOWN) {\n+\t\t\tu32 param, val, caps;\n+\n+\t\t\tcaps = FW_PARAMS_PARAM_PFVF_PORT_CAPS32;\n+\t\t\tparam = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) |\n+\t\t\t\t V_FW_PARAMS_PARAM_X(caps));\n+\t\t\tval = 1;\n+\t\t\tret = t4_set_params(adap, mbox, pf, vf, 1, ¶m,\n+\t\t\t\t\t &val);\n+\t\t\tfw_caps = ret == 0 ? FW_CAPS32 : FW_CAPS16;\n+\t\t\tadap->params.fw_caps_support = fw_caps;\n+\t\t}\n+\n+\t\tmemset(&cmd, 0, sizeof(cmd));\n+\t\tcmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |\n+\t\t\t\t\t F_FW_CMD_REQUEST |\n+\t\t\t\t\t F_FW_CMD_READ |\n+\t\t\t\t\t V_FW_PORT_CMD_PORTID(j));\n+\t\taction = fw_caps == FW_CAPS16 ? FW_PORT_ACTION_GET_PORT_INFO :\n+\t\t\t\t\t\tFW_PORT_ACTION_GET_PORT_INFO32;\n+\t\tcmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |\n+\t\t\t\t\t\t FW_LEN16(cmd));\n+\t\tret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);\n \t\tif (ret)\n \t\t\treturn ret;\n \n+\t\t/* Extract the various fields from the Port Information message.\n+\t\t */\n+\t\tif (fw_caps == FW_CAPS16) {\n+\t\t\tu32 lstatus =\n+\t\t\t\tbe32_to_cpu(cmd.u.info.lstatus_to_modtype);\n+\n+\t\t\tport_type = G_FW_PORT_CMD_PTYPE(lstatus);\n+\t\t\tmdio_addr = (lstatus & F_FW_PORT_CMD_MDIOCAP) ?\n+\t\t\t\t (int)G_FW_PORT_CMD_MDIOADDR(lstatus) : -1;\n+\t\t\tpcaps = be16_to_cpu(cmd.u.info.pcap);\n+\t\t\tacaps = be16_to_cpu(cmd.u.info.acap);\n+\t\t\tpcaps = fwcaps16_to_caps32(pcaps);\n+\t\t\tacaps = fwcaps16_to_caps32(acaps);\n+\t\t} else {\n+\t\t\tu32 lstatus32 =\n+\t\t\t\tbe32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);\n+\n+\t\t\tport_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);\n+\t\t\tmdio_addr = (lstatus32 & F_FW_PORT_CMD_MDIOCAP32) ?\n+\t\t\t\t (int)G_FW_PORT_CMD_MDIOADDR32(lstatus32) :\n+\t\t\t\t -1;\n+\t\t\tpcaps = be32_to_cpu(cmd.u.info32.pcaps32);\n+\t\t\tacaps = be32_to_cpu(cmd.u.info32.acaps32);\n+\t\t}\n+\n \t\tret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);\n \t\tif (ret < 0)\n \t\t\treturn ret;\n \n-\t\tp->viid = ret;\n-\t\tp->tx_chan = j;\n-\t\tp->rss_size = rss_size;\n+\t\tpi->viid = ret;\n+\t\tpi->tx_chan = j;\n+\t\tpi->rss_size = rss_size;\n \t\tt4_os_set_hw_addr(adap, i, addr);\n \n-\t\tret = be32_to_cpu(c.u.info.lstatus_to_modtype);\n-\t\tp->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?\n-\t\t\t\tG_FW_PORT_CMD_MDIOADDR(ret) : -1;\n-\t\tp->port_type = G_FW_PORT_CMD_PTYPE(ret);\n-\t\tp->mod_type = FW_PORT_MOD_TYPE_NA;\n+\t\tpi->port_type = port_type;\n+\t\tpi->mdio_addr = mdio_addr;\n+\t\tpi->mod_type = FW_PORT_MOD_TYPE_NA;\n \n-\t\tinit_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),\n-\t\t\t\t be16_to_cpu(c.u.info.acap));\n+\t\tinit_link_config(&pi->link_cfg, pcaps, acaps);\n \t\tj++;\n \t}\n \treturn 0;\ndiff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h\nindex 0e139377f..d71c5a4af 100644\n--- a/drivers/net/cxgbe/base/t4fw_interface.h\n+++ b/drivers/net/cxgbe/base/t4fw_interface.h\n@@ -491,7 +491,8 @@ enum fw_params_param_dev {\n * physical and virtual function parameters\n */\n enum fw_params_param_pfvf {\n-\tFW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31\n+\tFW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,\n+\tFW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A\n };\n \n /*\n@@ -1226,6 +1227,8 @@ enum fw_port_mdi32 {\n enum fw_port_action {\n \tFW_PORT_ACTION_L1_CFG\t\t= 0x0001,\n \tFW_PORT_ACTION_GET_PORT_INFO\t= 0x0003,\n+\tFW_PORT_ACTION_L1_CFG32 = 0x0009,\n+\tFW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,\n };\n \n struct fw_port_cmd {\n@@ -1314,6 +1317,18 @@ struct fw_port_cmd {\n \t\t\t\t__be64 r12;\n \t\t\t} control;\n \t\t} dcb;\n+\t\tstruct fw_port_l1cfg32 {\n+\t\t\t__be32 rcap32;\n+\t\t\t__be32 r;\n+\t\t} l1cfg32;\n+\t\tstruct fw_port_info32 {\n+\t\t\t__be32 lstatus32_to_cbllen32;\n+\t\t\t__be32 auxlinfo32_mtu32;\n+\t\t\t__be32 linkattr32;\n+\t\t\t__be32 pcaps32;\n+\t\t\t__be32 acaps32;\n+\t\t\t__be32 lpacaps32;\n+\t\t} info32;\n \t} u;\n };\n \n@@ -1387,6 +1402,36 @@ struct fw_port_cmd {\n #define G_FW_PORT_CMD_MODTYPE(x)\t\\\n \t(((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)\n \n+#define S_FW_PORT_CMD_LSTATUS32 31\n+#define M_FW_PORT_CMD_LSTATUS32 0x1\n+#define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)\n+#define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)\n+\n+#define S_FW_PORT_CMD_LINKDNRC32 28\n+#define M_FW_PORT_CMD_LINKDNRC32 0x7\n+#define G_FW_PORT_CMD_LINKDNRC32(x) \\\n+\t(((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)\n+\n+#define S_FW_PORT_CMD_MDIOCAP32 26\n+#define M_FW_PORT_CMD_MDIOCAP32 0x1\n+#define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)\n+#define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)\n+\n+#define S_FW_PORT_CMD_MDIOADDR32 21\n+#define M_FW_PORT_CMD_MDIOADDR32 0x1f\n+#define G_FW_PORT_CMD_MDIOADDR32(x) \\\n+\t(((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)\n+\n+#define S_FW_PORT_CMD_PORTTYPE32 13\n+#define M_FW_PORT_CMD_PORTTYPE32 0xff\n+#define G_FW_PORT_CMD_PORTTYPE32(x) \\\n+\t(((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)\n+\n+#define S_FW_PORT_CMD_MODTYPE32 8\n+#define M_FW_PORT_CMD_MODTYPE32 0x1f\n+#define G_FW_PORT_CMD_MODTYPE32(x) \\\n+\t(((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)\n+\n /*\n * These are configured into the VPD and hence tools that generate\n * VPD may use this enumeration.\n", "prefixes": [ "dpdk-dev", "7/7" ] }