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GET /api/patches/34916/?format=api
{ "id": 34916, "url": "http://patches.dpdk.org/api/patches/34916/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/be1b026e8329a17f55ebf27fdcecc5abb7bba965.1517685185.git.rahul.lakkireddy@chelsio.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<be1b026e8329a17f55ebf27fdcecc5abb7bba965.1517685185.git.rahul.lakkireddy@chelsio.com>", "list_archive_url": "https://inbox.dpdk.org/dev/be1b026e8329a17f55ebf27fdcecc5abb7bba965.1517685185.git.rahul.lakkireddy@chelsio.com", "date": "2018-02-04T06:06:11", "name": "[dpdk-dev,6/7] cxgbe: update link configuration for 32-bit port capability", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ce1fd38acfa0cd66027f63bef6cba2aa1f6a832d", "submitter": { "id": 241, "url": "http://patches.dpdk.org/api/people/241/?format=api", "name": "Rahul Lakkireddy", "email": "rahul.lakkireddy@chelsio.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/be1b026e8329a17f55ebf27fdcecc5abb7bba965.1517685185.git.rahul.lakkireddy@chelsio.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/34916/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/34916/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0EFA81B1AB;\n\tSun, 4 Feb 2018 07:06:54 +0100 (CET)", "from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8])\n\tby dpdk.org (Postfix) with ESMTP id B896C1B026\n\tfor <dev@dpdk.org>; Sun, 4 Feb 2018 07:06:51 +0100 (CET)", "from localhost (scalar.blr.asicdesigners.com [10.193.185.94])\n\tby stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id w1466lss030192; \n\tSat, 3 Feb 2018 22:06:48 -0800" ], "From": "Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>", "To": "dev@dpdk.org", "Cc": "kumaras@chelsio.com, surendra@chelsio.com, nirranjan@chelsio.com,\n\tindranil@chelsio.com", "Date": "Sun, 4 Feb 2018 11:36:11 +0530", "Message-Id": "<be1b026e8329a17f55ebf27fdcecc5abb7bba965.1517685185.git.rahul.lakkireddy@chelsio.com>", "X-Mailer": "git-send-email 2.5.3", "In-Reply-To": [ "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>", "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>" ], "References": [ "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>", "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>" ], "Subject": "[dpdk-dev] [PATCH 6/7] cxgbe: update link configuration for 32-bit\n\tport capability", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update link configuration API to prepare for 32-bit port capability\nsupport. Continue using 16-bit port capability for older firmware.\n\nOriginal work by Surendra Mobiya <surendra@chelsio.com>\n\nSigned-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>\nSigned-off-by: Kumar Sanghvi <kumaras@chelsio.com>\n---\n drivers/net/cxgbe/base/common.h | 40 +++++---\n drivers/net/cxgbe/base/t4_hw.c | 168 +++++++++++++++++++++++---------\n drivers/net/cxgbe/base/t4fw_interface.h | 36 ++++++-\n drivers/net/cxgbe/cxgbe_ethdev.c | 2 +-\n drivers/net/cxgbe/cxgbe_main.c | 28 +++---\n 5 files changed, 200 insertions(+), 74 deletions(-)", "diff": "diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h\nindex 0bd78c1b0..98886288c 100644\n--- a/drivers/net/cxgbe/base/common.h\n+++ b/drivers/net/cxgbe/base/common.h\n@@ -62,13 +62,13 @@ enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };\n \n enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };\n \n-enum {\n+enum cc_pause {\n \tPAUSE_RX = 1 << 0,\n \tPAUSE_TX = 1 << 1,\n \tPAUSE_AUTONEG = 1 << 2\n };\n \n-enum {\n+enum cc_fec {\n \tFEC_AUTO = 1 << 0, /* IEEE 802.3 \"automatic\" */\n \tFEC_RS = 1 << 1, /* Reed-Solomon */\n \tFEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */\n@@ -241,20 +241,30 @@ struct adapter_params {\n \tbool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */\n };\n \n+/* Firmware Port Capabilities types.\n+ */\n+typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */\n+typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */\n+\n struct link_config {\n-\tunsigned short supported; /* link capabilities */\n-\tunsigned short advertising; /* advertised capabilities */\n-\tunsigned int requested_speed; /* speed user has requested */\n-\tunsigned int speed; /* actual link speed */\n-\tunsigned char requested_fc; /* flow control user has requested */\n-\tunsigned char fc; /* actual link flow control */\n-\tunsigned char auto_fec; /* Forward Error Correction (FEC)\n-\t\t\t\t\t * \"automatic\" (IEEE 802.3)\n-\t\t\t\t\t */\n-\tunsigned char requested_fec; /* FEC requested */\n-\tunsigned char fec; /* FEC actual */\n-\tunsigned char autoneg; /* autonegotiating? */\n-\tunsigned char link_ok; /* link up? */\n+\tfw_port_cap32_t pcaps; /* link capabilities */\n+\tfw_port_cap32_t acaps; /* advertised capabilities */\n+\n+\tu32 requested_speed; /* speed (Mb/s) user has requested */\n+\tu32 speed; /* actual link speed (Mb/s) */\n+\n+\tenum cc_pause requested_fc; /* flow control user has requested */\n+\tenum cc_pause fc; /* actual link flow control */\n+\n+\tenum cc_fec auto_fec; /* Forward Error Correction\n+\t\t\t\t\t * \"automatic\" (IEEE 802.3)\n+\t\t\t\t\t */\n+\tenum cc_fec requested_fec; /* Forward Error Correction requested */\n+\tenum cc_fec fec; /* Forward Error Correction actual */\n+\n+\tunsigned char autoneg; /* autonegotiating? */\n+\n+\tunsigned char link_ok; /* link up? */\n };\n \n #include \"adapter.h\"\ndiff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c\nindex e8545ceb0..46b296a9d 100644\n--- a/drivers/net/cxgbe/base/t4_hw.c\n+++ b/drivers/net/cxgbe/base/t4_hw.c\n@@ -2789,66 +2789,105 @@ void t4_dump_version_info(struct adapter *adapter)\n \t\t\t G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));\n }\n \n-#define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \\\n-\t\t FW_PORT_CAP_ANEG)\n+#define ADVERT_MASK (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) | \\\n+\t\t FW_PORT_CAP32_ANEG)\n+/**\n+ * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits\n+ * @caps32: a 32-bit Port Capabilities value\n+ *\n+ * Returns the equivalent 16-bit Port Capabilities value. Note that\n+ * not all 32-bit Port Capabilities can be represented in the 16-bit\n+ * Port Capabilities and some fields/values may not make it.\n+ */\n+static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)\n+{\n+\tfw_port_cap16_t caps16 = 0;\n+\n+#define CAP32_TO_CAP16(__cap) \\\n+\tdo { \\\n+\t\tif (caps32 & FW_PORT_CAP32_##__cap) \\\n+\t\t\tcaps16 |= FW_PORT_CAP_##__cap; \\\n+\t} while (0)\n+\n+\tCAP32_TO_CAP16(SPEED_100M);\n+\tCAP32_TO_CAP16(SPEED_1G);\n+\tCAP32_TO_CAP16(SPEED_10G);\n+\tCAP32_TO_CAP16(SPEED_25G);\n+\tCAP32_TO_CAP16(SPEED_40G);\n+\tCAP32_TO_CAP16(SPEED_100G);\n+\tCAP32_TO_CAP16(FC_RX);\n+\tCAP32_TO_CAP16(FC_TX);\n+\tCAP32_TO_CAP16(802_3_PAUSE);\n+\tCAP32_TO_CAP16(802_3_ASM_DIR);\n+\tCAP32_TO_CAP16(ANEG);\n+\tCAP32_TO_CAP16(MDIX);\n+\tCAP32_TO_CAP16(MDIAUTO);\n+\tCAP32_TO_CAP16(FEC_RS);\n+\tCAP32_TO_CAP16(FEC_BASER_RS);\n+\n+#undef CAP32_TO_CAP16\n+\n+\treturn caps16;\n+}\n \n /* Translate Firmware Pause specification to Common Code */\n-static inline unsigned int fwcap_to_cc_pause(unsigned int fw_pause)\n+static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)\n {\n-\tunsigned int cc_pause = 0;\n+\tenum cc_pause cc_pause = 0;\n \n-\tif (fw_pause & F_FW_PORT_CMD_RXPAUSE)\n+\tif (fw_pause & FW_PORT_CAP32_FC_RX)\n \t\tcc_pause |= PAUSE_RX;\n-\tif (fw_pause & F_FW_PORT_CMD_TXPAUSE)\n+\tif (fw_pause & FW_PORT_CAP32_FC_TX)\n \t\tcc_pause |= PAUSE_TX;\n \n \treturn cc_pause;\n }\n \n /* Translate Common Code Pause Frame specification into Firmware */\n-static inline unsigned int cc_to_fwcap_pause(unsigned int cc_pause)\n+static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)\n {\n-\tunsigned int fw_pause = 0;\n+\tfw_port_cap32_t fw_pause = 0;\n \n \tif (cc_pause & PAUSE_RX)\n-\t\tfw_pause |= F_FW_PORT_CMD_RXPAUSE;\n+\t\tfw_pause |= FW_PORT_CAP32_FC_RX;\n \tif (cc_pause & PAUSE_TX)\n-\t\tfw_pause |= F_FW_PORT_CMD_TXPAUSE;\n+\t\tfw_pause |= FW_PORT_CAP32_FC_TX;\n \n \treturn fw_pause;\n }\n \n /* Translate Firmware Forward Error Correction specification to Common Code */\n-static inline unsigned int fwcap_to_cc_fec(unsigned int fw_fec)\n+static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)\n {\n-\tunsigned int cc_fec = 0;\n+\tenum cc_fec cc_fec = 0;\n \n-\tif (fw_fec & FW_PORT_CAP_FEC_RS)\n+\tif (fw_fec & FW_PORT_CAP32_FEC_RS)\n \t\tcc_fec |= FEC_RS;\n-\tif (fw_fec & FW_PORT_CAP_FEC_BASER_RS)\n+\tif (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)\n \t\tcc_fec |= FEC_BASER_RS;\n \n \treturn cc_fec;\n }\n \n /* Translate Common Code Forward Error Correction specification to Firmware */\n-static inline unsigned int cc_to_fwcap_fec(unsigned int cc_fec)\n+static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)\n {\n-\tunsigned int fw_fec = 0;\n+\tfw_port_cap32_t fw_fec = 0;\n \n \tif (cc_fec & FEC_RS)\n-\t\tfw_fec |= FW_PORT_CAP_FEC_RS;\n+\t\tfw_fec |= FW_PORT_CAP32_FEC_RS;\n \tif (cc_fec & FEC_BASER_RS)\n-\t\tfw_fec |= FW_PORT_CAP_FEC_BASER_RS;\n+\t\tfw_fec |= FW_PORT_CAP32_FEC_BASER_RS;\n \n \treturn fw_fec;\n }\n \n /**\n * t4_link_l1cfg - apply link configuration to MAC/PHY\n- * @phy: the PHY to setup\n- * @mac: the MAC to setup\n- * @lc: the requested link configuration\n+ * @adapter: the adapter\n+ * @mbox: the Firmware Mailbox to use\n+ * @port: the Port ID\n+ * @lc: the Port's Link Configuration\n *\n * Set up a port's MAC and PHY according to a desired link configuration.\n * - If the PHY can auto-negotiate first decide what to advertise, then\n@@ -2860,9 +2899,9 @@ static inline unsigned int cc_to_fwcap_fec(unsigned int cc_fec)\n int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,\n \t\t struct link_config *lc)\n {\n-\tstruct fw_port_cmd c;\n-\tunsigned int fw_mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);\n-\tunsigned int fw_fc, cc_fec, fw_fec;\n+\tunsigned int fw_mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);\n+\tfw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;\n+\tstruct fw_port_cmd cmd;\n \n \tlc->link_ok = 0;\n \n@@ -2881,30 +2920,32 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,\n \t\tcc_fec = lc->requested_fec;\n \tfw_fec = cc_to_fwcap_fec(cc_fec);\n \n-\tmemset(&c, 0, sizeof(c));\n-\tc.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |\n-\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_EXEC |\n-\t\t\t\t V_FW_PORT_CMD_PORTID(port));\n-\tc.action_to_len16 =\n-\t\tcpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |\n-\t\t\t FW_LEN16(c));\n-\n-\tif (!(lc->supported & FW_PORT_CAP_ANEG)) {\n-\t\tc.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |\n-\t\t\t\t\t fw_fc | fw_fec);\n+\t/* Figure out what our Requested Port Capabilities are going to be.\n+\t */\n+\tif (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {\n+\t\trcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;\n \t\tlc->fc = lc->requested_fc & ~PAUSE_AUTONEG;\n \t\tlc->fec = cc_fec;\n \t} else if (lc->autoneg == AUTONEG_DISABLE) {\n-\t\tc.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fw_fc |\n-\t\t\t\t\t fw_fec | fw_mdi);\n+\t\trcap = lc->requested_speed | fw_fc | fw_fec | fw_mdi;\n \t\tlc->fc = lc->requested_fc & ~PAUSE_AUTONEG;\n \t\tlc->fec = cc_fec;\n \t} else {\n-\t\tc.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fw_fc | fw_fec |\n-\t\t\t\t\t fw_mdi);\n+\t\trcap = lc->acaps | fw_fc | fw_fec | fw_mdi;\n \t}\n \n-\treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n+\t/* And send that on to the Firmware ...\n+\t */\n+\tmemset(&cmd, 0, sizeof(cmd));\n+\tcmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |\n+\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_EXEC |\n+\t\t\t\t V_FW_PORT_CMD_PORTID(port));\n+\tcmd.action_to_len16 =\n+\t\tcpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |\n+\t\t\t FW_LEN16(cmd));\n+\tcmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));\n+\n+\treturn t4_wr_mbox(adap, mbox, &cmd, sizeof(cmd), NULL);\n }\n \n /**\n@@ -4237,6 +4278,28 @@ int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,\n \treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n }\n \n+/* Return the highest speed set in the port capabilities, in Mb/s. */\n+static unsigned int fwcap_to_speed(fw_port_cap32_t caps)\n+{\n+#define TEST_SPEED_RETURN(__caps_speed, __speed) \\\n+\tdo { \\\n+\t\tif (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \\\n+\t\t\treturn __speed; \\\n+\t} while (0)\n+\n+\tTEST_SPEED_RETURN(100G, 100000);\n+\tTEST_SPEED_RETURN(50G, 50000);\n+\tTEST_SPEED_RETURN(40G, 40000);\n+\tTEST_SPEED_RETURN(25G, 25000);\n+\tTEST_SPEED_RETURN(10G, 10000);\n+\tTEST_SPEED_RETURN(1G, 1000);\n+\tTEST_SPEED_RETURN(100M, 100);\n+\n+#undef TEST_SPEED_RETURN\n+\n+\treturn 0;\n+}\n+\n /**\n * t4_handle_fw_rpl - process a FW reply message\n * @adap: the adapter\n@@ -4319,7 +4382,21 @@ int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)\n \t\t\tlc->speed = speed;\n \t\t\tlc->fc = fc;\n \t\t\tlc->fec = fec;\n-\t\t\tlc->supported = be16_to_cpu(p->u.info.pcap);\n+\t\t\tlc->pcaps = be16_to_cpu(p->u.info.pcap);\n+\t\t\tlc->acaps = be16_to_cpu(p->u.info.acap) & ADVERT_MASK;\n+\t\t\tif (lc->acaps & FW_PORT_CAP32_ANEG) {\n+\t\t\t\tlc->autoneg = AUTONEG_ENABLE;\n+\t\t\t} else {\n+\t\t\t\t/* When Autoneg is disabled, user needs to set\n+\t\t\t\t * single speed.\n+\t\t\t\t */\n+\t\t\t\tlc->acaps = 0;\n+\t\t\t\tlc->requested_speed =\n+\t\t\t\t\tbe16_to_cpu(p->u.info.acap);\n+\t\t\t\tlc->requested_speed =\n+\t\t\t\t\tfwcap_to_speed(lc->requested_speed);\n+\t\t\t\tlc->autoneg = AUTONEG_DISABLE;\n+\t\t\t}\n \t\t}\n \t} else {\n \t\tdev_warn(adap, \"Unknown firmware reply %d\\n\", opcode);\n@@ -4352,7 +4429,7 @@ void t4_reset_link_config(struct adapter *adap, int idx)\n static void init_link_config(struct link_config *lc, unsigned int pcaps,\n \t\t\t unsigned int acaps)\n {\n-\tlc->supported = pcaps;\n+\tlc->pcaps = pcaps;\n \tlc->requested_speed = 0;\n \tlc->speed = 0;\n \tlc->requested_fc = 0;\n@@ -4366,11 +4443,12 @@ static void init_link_config(struct link_config *lc, unsigned int pcaps,\n \tlc->requested_fec = FEC_AUTO;\n \tlc->fec = lc->auto_fec;\n \n-\tif (lc->supported & FW_PORT_CAP_ANEG) {\n-\t\tlc->advertising = lc->supported & ADVERT_MASK;\n+\tif (lc->pcaps & FW_PORT_CAP32_ANEG) {\n+\t\tlc->acaps = lc->pcaps & ADVERT_MASK;\n \t\tlc->autoneg = AUTONEG_ENABLE;\n+\t\tlc->requested_fc |= PAUSE_AUTONEG;\n \t} else {\n-\t\tlc->advertising = 0;\n+\t\tlc->acaps = 0;\n \t\tlc->autoneg = AUTONEG_DISABLE;\n \t}\n }\ndiff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h\nindex 883a1c7f5..0e139377f 100644\n--- a/drivers/net/cxgbe/base/t4fw_interface.h\n+++ b/drivers/net/cxgbe/base/t4fw_interface.h\n@@ -1154,7 +1154,7 @@ struct fw_vi_stats_cmd {\n \t} u;\n };\n \n-/* port capabilities bitmap */\n+/* old 16-bit port capabilities bitmap */\n enum fw_port_cap {\n \tFW_PORT_CAP_SPEED_100M\t\t= 0x0001,\n \tFW_PORT_CAP_SPEED_1G\t\t= 0x0002,\n@@ -1189,6 +1189,40 @@ enum fw_port_mdi {\n #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)\n #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)\n \n+/* new 32-bit port capabilities bitmap (fw_port_cap32_t) */\n+#define FW_PORT_CAP32_SPEED_100M 0x00000001UL\n+#define FW_PORT_CAP32_SPEED_1G 0x00000002UL\n+#define FW_PORT_CAP32_SPEED_10G 0x00000004UL\n+#define FW_PORT_CAP32_SPEED_25G 0x00000008UL\n+#define FW_PORT_CAP32_SPEED_40G 0x00000010UL\n+#define FW_PORT_CAP32_SPEED_50G 0x00000020UL\n+#define FW_PORT_CAP32_SPEED_100G 0x00000040UL\n+#define FW_PORT_CAP32_FC_RX 0x00010000UL\n+#define FW_PORT_CAP32_FC_TX 0x00020000UL\n+#define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL\n+#define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL\n+#define FW_PORT_CAP32_ANEG 0x00100000UL\n+#define FW_PORT_CAP32_MDIX 0x00200000UL\n+#define FW_PORT_CAP32_MDIAUTO 0x00400000UL\n+#define FW_PORT_CAP32_FEC_RS 0x00800000UL\n+#define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL\n+\n+#define S_FW_PORT_CAP32_SPEED 0\n+#define M_FW_PORT_CAP32_SPEED 0xfff\n+#define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)\n+#define G_FW_PORT_CAP32_SPEED(x) \\\n+\t(((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)\n+\n+enum fw_port_mdi32 {\n+\tFW_PORT_CAP32_MDI_AUTO,\n+};\n+\n+#define S_FW_PORT_CAP32_MDI 21\n+#define M_FW_PORT_CAP32_MDI 3\n+#define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)\n+#define G_FW_PORT_CAP32_MDI(x) \\\n+\t(((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)\n+\n enum fw_port_action {\n \tFW_PORT_ACTION_L1_CFG\t\t= 0x0001,\n \tFW_PORT_ACTION_GET_PORT_INFO\t= 0x0003,\ndiff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c\nindex 1343041ef..b0d82fc93 100644\n--- a/drivers/net/cxgbe/cxgbe_ethdev.c\n+++ b/drivers/net/cxgbe/cxgbe_ethdev.c\n@@ -752,7 +752,7 @@ static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \tstruct adapter *adapter = pi->adapter;\n \tstruct link_config *lc = &pi->link_cfg;\n \n-\tif (lc->supported & FW_PORT_CAP_ANEG) {\n+\tif (lc->pcaps & FW_PORT_CAP32_ANEG) {\n \t\tif (fc_conf->autoneg)\n \t\t\tlc->requested_fc |= PAUSE_AUTONEG;\n \t\telse\ndiff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c\nindex 930c3dfdf..eb8213921 100644\n--- a/drivers/net/cxgbe/cxgbe_main.c\n+++ b/drivers/net/cxgbe/cxgbe_main.c\n@@ -199,15 +199,16 @@ int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,\n \n static inline bool is_x_1g_port(const struct link_config *lc)\n {\n-\treturn (lc->supported & FW_PORT_CAP_SPEED_1G) != 0;\n+\treturn (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;\n }\n \n static inline bool is_x_10g_port(const struct link_config *lc)\n {\n \tunsigned int speeds, high_speeds;\n \n-\tspeeds = V_FW_PORT_CAP_SPEED(G_FW_PORT_CAP_SPEED(lc->supported));\n-\thigh_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);\n+\tspeeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));\n+\thigh_speeds = speeds &\n+\t\t ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);\n \n \treturn high_speeds != 0;\n }\n@@ -387,17 +388,19 @@ static void print_port_info(struct adapter *adap)\n \t\tconst struct port_info *pi = &adap->port[i];\n \t\tchar *bufp = buf;\n \n-\t\tif (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)\n+\t\tif (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)\n \t\t\tbufp += sprintf(bufp, \"100M/\");\n-\t\tif (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)\n+\t\tif (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)\n \t\t\tbufp += sprintf(bufp, \"1G/\");\n-\t\tif (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)\n+\t\tif (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)\n \t\t\tbufp += sprintf(bufp, \"10G/\");\n-\t\tif (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)\n+\t\tif (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)\n \t\t\tbufp += sprintf(bufp, \"25G/\");\n-\t\tif (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)\n+\t\tif (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)\n \t\t\tbufp += sprintf(bufp, \"40G/\");\n-\t\tif (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)\n+\t\tif (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)\n+\t\t\tbufp += sprintf(bufp, \"50G/\");\n+\t\tif (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)\n \t\t\tbufp += sprintf(bufp, \"100G/\");\n \t\tif (bufp != buf)\n \t\t\t--bufp;\n@@ -1096,7 +1099,7 @@ static void fw_caps_to_speed_caps(enum fw_port_type port_type,\n \n #define FW_CAPS_TO_SPEED(__fw_name) \\\n \tdo { \\\n-\t\tif (fw_caps & FW_PORT_CAP_ ## __fw_name) \\\n+\t\tif (fw_caps & FW_PORT_CAP32_ ## __fw_name) \\\n \t\t\tSET_SPEED(__fw_name); \\\n \t} while (0)\n \n@@ -1151,6 +1154,7 @@ static void fw_caps_to_speed_caps(enum fw_port_type port_type,\n \tcase FW_PORT_TYPE_CR4_QSFP:\n \t\tFW_CAPS_TO_SPEED(SPEED_25G);\n \t\tFW_CAPS_TO_SPEED(SPEED_40G);\n+\t\tFW_CAPS_TO_SPEED(SPEED_50G);\n \t\tFW_CAPS_TO_SPEED(SPEED_100G);\n \t\tbreak;\n \n@@ -1173,10 +1177,10 @@ void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)\n {\n \t*speed_caps = 0;\n \n-\tfw_caps_to_speed_caps(pi->port_type, pi->link_cfg.supported,\n+\tfw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,\n \t\t\t speed_caps);\n \n-\tif (!(pi->link_cfg.supported & FW_PORT_CAP_ANEG))\n+\tif (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))\n \t\t*speed_caps |= ETH_LINK_SPEED_FIXED;\n }\n \n", "prefixes": [ "dpdk-dev", "6/7" ] }