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GET /api/patches/34913/?format=api
{ "id": 34913, "url": "http://patches.dpdk.org/api/patches/34913/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/713e92d0143827f8af409763815cde15b9d40305.1517685185.git.rahul.lakkireddy@chelsio.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<713e92d0143827f8af409763815cde15b9d40305.1517685185.git.rahul.lakkireddy@chelsio.com>", "list_archive_url": "https://inbox.dpdk.org/dev/713e92d0143827f8af409763815cde15b9d40305.1517685185.git.rahul.lakkireddy@chelsio.com", "date": "2018-02-04T06:06:08", "name": "[dpdk-dev,3/7] cxgbe: add support to update RSS hash configuration and key", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "63eee0a633e427e11d6c164cb40ef78595868a0e", "submitter": { "id": 241, "url": "http://patches.dpdk.org/api/people/241/?format=api", "name": "Rahul Lakkireddy", "email": "rahul.lakkireddy@chelsio.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/713e92d0143827f8af409763815cde15b9d40305.1517685185.git.rahul.lakkireddy@chelsio.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/34913/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/34913/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 81525A49A;\n\tSun, 4 Feb 2018 07:06:49 +0100 (CET)", "from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8])\n\tby dpdk.org (Postfix) with ESMTP id 37938A495\n\tfor <dev@dpdk.org>; Sun, 4 Feb 2018 07:06:48 +0100 (CET)", "from localhost (scalar.blr.asicdesigners.com [10.193.185.94])\n\tby stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id w1466dVJ030183; \n\tSat, 3 Feb 2018 22:06:40 -0800" ], "From": "Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>", "To": "dev@dpdk.org", "Cc": "kumaras@chelsio.com, surendra@chelsio.com, nirranjan@chelsio.com,\n\tindranil@chelsio.com", "Date": "Sun, 4 Feb 2018 11:36:08 +0530", "Message-Id": "<713e92d0143827f8af409763815cde15b9d40305.1517685185.git.rahul.lakkireddy@chelsio.com>", "X-Mailer": "git-send-email 2.5.3", "In-Reply-To": [ "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>", "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>" ], "References": [ "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>", "<cover.1517685185.git.rahul.lakkireddy@chelsio.com>" ], "Subject": "[dpdk-dev] [PATCH 3/7] cxgbe: add support to update RSS hash\n\tconfiguration and key", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kumar Sanghvi <kumaras@chelsio.com>\n\nAdd firmware API for updating RSS hash configuration and key. Move\nRSS hash configuration from cxgb4_write_rss() to a separate function\ncxgbe_write_rss_conf().\n\nAlso, rename cxgb4_write_rss() to cxgbe_write_rss() for consistency.\n\nOriginal work by Surendra Mobiya <surendra@chelsio.com>\n\nSigned-off-by: Kumar Sanghvi <kumaras@chelsio.com>\nSigned-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>\n---\n doc/guides/nics/cxgbe.rst | 2 +\n doc/guides/nics/features/cxgbe.ini | 1 +\n doc/guides/rel_notes/release_18_02.rst | 3 ++\n drivers/net/cxgbe/base/adapter.h | 4 +-\n drivers/net/cxgbe/base/common.h | 3 ++\n drivers/net/cxgbe/base/t4_hw.c | 73 +++++++++++++++++++++++++++\n drivers/net/cxgbe/base/t4_regs.h | 25 +++++++++\n drivers/net/cxgbe/base/t4fw_interface.h | 89 +++++++++++++++++++++++++++++++++\n drivers/net/cxgbe/cxgbe.h | 2 +\n drivers/net/cxgbe/cxgbe_ethdev.c | 32 ++++++++++++\n drivers/net/cxgbe/cxgbe_main.c | 79 ++++++++++++++++++++++-------\n 11 files changed, 295 insertions(+), 18 deletions(-)", "diff": "diff --git a/doc/guides/nics/cxgbe.rst b/doc/guides/nics/cxgbe.rst\nindex 8651a7be6..6126167c5 100644\n--- a/doc/guides/nics/cxgbe.rst\n+++ b/doc/guides/nics/cxgbe.rst\n@@ -45,6 +45,8 @@ CXGBE PMD has support for:\n \n - Multiple queues for TX and RX\n - Receiver Side Steering (RSS)\n+ Receiver Side Steering (RSS) on IPv4, IPv6, IPv4-TCP/UDP, IPv6-TCP/UDP.\n+ For 4-tuple, enabling 'RSS on TCP' and 'RSS on TCP + UDP' is supported.\n - VLAN filtering\n - Checksum offload\n - Promiscuous mode\ndiff --git a/doc/guides/nics/features/cxgbe.ini b/doc/guides/nics/features/cxgbe.ini\nindex 1b9d81ffb..6cf5c13f5 100644\n--- a/doc/guides/nics/features/cxgbe.ini\n+++ b/doc/guides/nics/features/cxgbe.ini\n@@ -14,6 +14,7 @@ TSO = Y\n Promiscuous mode = Y\n Allmulticast mode = Y\n RSS hash = Y\n+RSS key update = Y\n Flow control = Y\n CRC offload = Y\n VLAN offload = Y\ndiff --git a/doc/guides/rel_notes/release_18_02.rst b/doc/guides/rel_notes/release_18_02.rst\nindex 689080bed..51a50cf93 100644\n--- a/doc/guides/rel_notes/release_18_02.rst\n+++ b/doc/guides/rel_notes/release_18_02.rst\n@@ -204,6 +204,9 @@ New Features\n is unaffected by these changes, and can continue to be used for this\n and subsequent releases until such time as it's deprecation is announced.\n \n+* **Added RSS hash and key update to CXGBE PMD.**\n+\n+ Support to update RSS hash and key has been added to CXGBE PMD.\n \n API Changes\n -----------\ndiff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h\nindex 0c1a1be25..4db2951e7 100644\n--- a/drivers/net/cxgbe/base/adapter.h\n+++ b/drivers/net/cxgbe/base/adapter.h\n@@ -77,6 +77,7 @@ struct port_info {\n \tu16 *rss; /* rss table */\n \tu8 rss_mode; /* rss mode */\n \tu16 rss_size; /* size of VI's RSS table slice */\n+\tu64 rss_hf;\t\t\t/* RSS Hash Function */\n };\n \n /* Enable or disable autonegotiation. If this is set to enable,\n@@ -736,6 +737,7 @@ int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,\n \t\t\t unsigned int cnt);\n int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,\n \t unsigned int budget, unsigned int *work_done);\n-int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);\n+int cxgbe_write_rss(const struct port_info *pi, const u16 *queues);\n+int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags);\n \n #endif /* __T4_ADAPTER_H__ */\ndiff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h\nindex 1eda57d09..5301f7474 100644\n--- a/drivers/net/cxgbe/base/common.h\n+++ b/drivers/net/cxgbe/base/common.h\n@@ -410,6 +410,9 @@ int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,\n \t\t\tint start, int n, const u16 *rspq, unsigned int nrspq);\n int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,\n \t\t unsigned int flags, unsigned int defq);\n+void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,\n+\t\t unsigned int start_index, unsigned int rw);\n+void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);\n \n enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };\n int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,\ndiff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c\nindex 56f38c838..9eb83fd5e 100644\n--- a/drivers/net/cxgbe/base/t4_hw.c\n+++ b/drivers/net/cxgbe/base/t4_hw.c\n@@ -2166,6 +2166,79 @@ int t4_seeprom_wp(struct adapter *adapter, int enable)\n \treturn t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);\n }\n \n+/**\n+ * t4_fw_tp_pio_rw - Access TP PIO through LDST\n+ * @adap: the adapter\n+ * @vals: where the indirect register values are stored/written\n+ * @nregs: how many indirect registers to read/write\n+ * @start_idx: index of first indirect register to read/write\n+ * @rw: Read (1) or Write (0)\n+ *\n+ * Access TP PIO registers through LDST\n+ */\n+void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,\n+\t\t unsigned int start_index, unsigned int rw)\n+{\n+\tint cmd = FW_LDST_ADDRSPC_TP_PIO;\n+\tstruct fw_ldst_cmd c;\n+\tunsigned int i;\n+\tint ret;\n+\n+\tfor (i = 0 ; i < nregs; i++) {\n+\t\tmemset(&c, 0, sizeof(c));\n+\t\tc.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |\n+\t\t\t\t\t\tF_FW_CMD_REQUEST |\n+\t\t\t\t\t\t(rw ? F_FW_CMD_READ :\n+\t\t\t\t\t\t F_FW_CMD_WRITE) |\n+\t\t\t\t\t\tV_FW_LDST_CMD_ADDRSPACE(cmd));\n+\t\tc.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));\n+\n+\t\tc.u.addrval.addr = cpu_to_be32(start_index + i);\n+\t\tc.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);\n+\t\tret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);\n+\t\tif (ret == 0) {\n+\t\t\tif (rw)\n+\t\t\t\tvals[i] = be32_to_cpu(c.u.addrval.val);\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * t4_write_rss_key - program one of the RSS keys\n+ * @adap: the adapter\n+ * @key: 10-entry array holding the 320-bit RSS key\n+ * @idx: which RSS key to write\n+ *\n+ * Writes one of the RSS keys with the given 320-bit value. If @idx is\n+ * 0..15 the corresponding entry in the RSS key table is written,\n+ * otherwise the global RSS key is written.\n+ */\n+void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)\n+{\n+\tu32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);\n+\tu8 rss_key_addr_cnt = 16;\n+\n+\t/* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),\n+\t * allows access to key addresses 16-63 by using KeyWrAddrX\n+\t * as index[5:4](upper 2) into key table\n+\t */\n+\tif ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&\n+\t (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))\n+\t\trss_key_addr_cnt = 32;\n+\n+\tt4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);\n+\n+\tif (idx >= 0 && idx < rss_key_addr_cnt) {\n+\t\tif (rss_key_addr_cnt > 16)\n+\t\t\tt4_write_reg(adap, A_TP_RSS_CONFIG_VRT,\n+\t\t\t\t V_KEYWRADDRX(idx >> 4) |\n+\t\t\t\t V_T6_VFWRADDR(idx) | F_KEYWREN);\n+\t\telse\n+\t\t\tt4_write_reg(adap, A_TP_RSS_CONFIG_VRT,\n+\t\t\t\t V_KEYWRADDR(idx) | F_KEYWREN);\n+\t}\n+}\n+\n /**\n * t4_config_rss_range - configure a portion of the RSS mapping table\n * @adapter: the adapter\ndiff --git a/drivers/net/cxgbe/base/t4_regs.h b/drivers/net/cxgbe/base/t4_regs.h\nindex 1100e16fe..0f0bca910 100644\n--- a/drivers/net/cxgbe/base/t4_regs.h\n+++ b/drivers/net/cxgbe/base/t4_regs.h\n@@ -503,9 +503,34 @@\n #define V_MTUVALUE(x) ((x) << S_MTUVALUE)\n #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)\n \n+#define A_TP_RSS_CONFIG_VRT 0x7e00\n+\n+#define S_KEYMODE 6\n+#define M_KEYMODE 0x3U\n+#define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)\n+\n+#define S_KEYWRADDR 0\n+#define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)\n+\n+#define S_KEYWREN 4\n+#define V_KEYWREN(x) ((x) << S_KEYWREN)\n+#define F_KEYWREN V_KEYWREN(1U)\n+\n+#define S_KEYWRADDRX 30\n+#define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX)\n+\n+#define S_KEYEXTEND 26\n+#define V_KEYEXTEND(x) ((x) << S_KEYEXTEND)\n+#define F_KEYEXTEND V_KEYEXTEND(1U)\n+\n+#define S_T6_VFWRADDR 8\n+#define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR)\n+\n #define A_TP_PIO_ADDR 0x7e40\n #define A_TP_PIO_DATA 0x7e44\n \n+#define A_TP_RSS_SECRET_KEY0 0x40\n+\n #define A_TP_VLAN_PRI_MAP 0x140\n \n #define S_FRAGMENTATION 9\ndiff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h\nindex 6ca4f3188..883a1c7f5 100644\n--- a/drivers/net/cxgbe/base/t4fw_interface.h\n+++ b/drivers/net/cxgbe/base/t4fw_interface.h\n@@ -171,6 +171,7 @@ struct fw_eth_tx_pkts_wr {\n #define FW_CMD_HELLO_RETRIES\t3\n \n enum fw_cmd_opcodes {\n+\tFW_LDST_CMD\t\t = 0x01,\n \tFW_RESET_CMD = 0x03,\n \tFW_HELLO_CMD = 0x04,\n \tFW_BYE_CMD = 0x05,\n@@ -238,6 +239,94 @@ struct fw_cmd_hdr {\n \n #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)\n \n+/* address spaces\n+ */\n+enum fw_ldst_addrspc {\n+\tFW_LDST_ADDRSPC_TP_PIO = 0x0010,\n+};\n+\n+struct fw_ldst_cmd {\n+\t__be32 op_to_addrspace;\n+\t__be32 cycles_to_len16;\n+\tunion fw_ldst {\n+\t\tstruct fw_ldst_addrval {\n+\t\t\t__be32 addr;\n+\t\t\t__be32 val;\n+\t\t} addrval;\n+\t\tstruct fw_ldst_idctxt {\n+\t\t\t__be32 physid;\n+\t\t\t__be32 msg_ctxtflush;\n+\t\t\t__be32 ctxt_data7;\n+\t\t\t__be32 ctxt_data6;\n+\t\t\t__be32 ctxt_data5;\n+\t\t\t__be32 ctxt_data4;\n+\t\t\t__be32 ctxt_data3;\n+\t\t\t__be32 ctxt_data2;\n+\t\t\t__be32 ctxt_data1;\n+\t\t\t__be32 ctxt_data0;\n+\t\t} idctxt;\n+\t\tstruct fw_ldst_mdio {\n+\t\t\t__be16 paddr_mmd;\n+\t\t\t__be16 raddr;\n+\t\t\t__be16 vctl;\n+\t\t\t__be16 rval;\n+\t\t} mdio;\n+\t\tstruct fw_ldst_mps {\n+\t\t\t__be16 fid_ctl;\n+\t\t\t__be16 rplcpf_pkd;\n+\t\t\t__be32 rplc127_96;\n+\t\t\t__be32 rplc95_64;\n+\t\t\t__be32 rplc63_32;\n+\t\t\t__be32 rplc31_0;\n+\t\t\t__be32 atrb;\n+\t\t\t__be16 vlan[16];\n+\t\t} mps;\n+\t\tstruct fw_ldst_func {\n+\t\t\t__u8 access_ctl;\n+\t\t\t__u8 mod_index;\n+\t\t\t__be16 ctl_id;\n+\t\t\t__be32 offset;\n+\t\t\t__be64 data0;\n+\t\t\t__be64 data1;\n+\t\t} func;\n+\t\tstruct fw_ldst_pcie {\n+\t\t\t__u8 ctrl_to_fn;\n+\t\t\t__u8 bnum;\n+\t\t\t__u8 r;\n+\t\t\t__u8 ext_r;\n+\t\t\t__u8 select_naccess;\n+\t\t\t__u8 pcie_fn;\n+\t\t\t__be16 nset_pkd;\n+\t\t\t__be32 data[12];\n+\t\t} pcie;\n+\t\tstruct fw_ldst_i2c_deprecated {\n+\t\t\t__u8 pid_pkd;\n+\t\t\t__u8 base;\n+\t\t\t__u8 boffset;\n+\t\t\t__u8 data;\n+\t\t\t__be32 r9;\n+\t\t} i2c_deprecated;\n+\t\tstruct fw_ldst_i2c {\n+\t\t\t__u8 pid;\n+\t\t\t__u8 did;\n+\t\t\t__u8 boffset;\n+\t\t\t__u8 blen;\n+\t\t\t__be32 r9;\n+\t\t\t__u8 data[48];\n+\t\t} i2c;\n+\t\tstruct fw_ldst_le {\n+\t\t\t__be32 index;\n+\t\t\t__be32 r9;\n+\t\t\t__u8 val[33];\n+\t\t\t__u8 r11[7];\n+\t\t} le;\n+\t} u;\n+};\n+\n+#define S_FW_LDST_CMD_ADDRSPACE 0\n+#define M_FW_LDST_CMD_ADDRSPACE 0xff\n+#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)\n+\n struct fw_reset_cmd {\n \t__be32 op_to_write;\n \t__be32 retval_len16;\ndiff --git a/drivers/net/cxgbe/cxgbe.h b/drivers/net/cxgbe/cxgbe.h\nindex f98915455..489e09dda 100644\n--- a/drivers/net/cxgbe/cxgbe.h\n+++ b/drivers/net/cxgbe/cxgbe.h\n@@ -46,6 +46,8 @@\n #define CXGBE_MIN_RX_BUFSIZE ETHER_MIN_MTU /* min buf size */\n #define CXGBE_MAX_RX_PKTLEN (9000 + ETHER_HDR_LEN + ETHER_CRC_LEN) /* max pkt */\n \n+#define CXGBE_DEFAULT_RSS_KEY_LEN 40 /* 320-bits */\n+\n int cxgbe_probe(struct adapter *adapter);\n void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps);\n int cxgbe_up(struct adapter *adap);\ndiff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c\nindex 5a25125fe..7b902763b 100644\n--- a/drivers/net/cxgbe/cxgbe_ethdev.c\n+++ b/drivers/net/cxgbe/cxgbe_ethdev.c\n@@ -171,6 +171,7 @@ static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,\n \t\t\t\t DEV_TX_OFFLOAD_TCP_TSO;\n \n \tdevice_info->reta_size = pi->rss_size;\n+\tdevice_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;\n \n \tdevice_info->rx_desc_lim = cxgbe_desc_lim;\n \tdevice_info->tx_desc_lim = cxgbe_desc_lim;\n@@ -788,6 +789,36 @@ cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)\n \treturn NULL;\n }\n \n+/* Update RSS hash configuration\n+ */\n+static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_eth_rss_conf *rss_conf)\n+{\n+\tstruct port_info *pi = (struct port_info *)(dev->data->dev_private);\n+\tstruct adapter *adapter = pi->adapter;\n+\tint err;\n+\n+\terr = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);\n+\tif (err)\n+\t\treturn err;\n+\n+\tpi->rss_hf = rss_conf->rss_hf;\n+\n+\tif (rss_conf->rss_key) {\n+\t\tu32 key[10], mod_key[10];\n+\t\tint i, j;\n+\n+\t\tmemcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);\n+\n+\t\tfor (i = 9, j = 0; i >= 0; i--, j++)\n+\t\t\tmod_key[j] = cpu_to_be32(key[i]);\n+\n+\t\tt4_write_rss_key(adapter, mod_key, -1);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)\n {\n \tRTE_SET_USED(dev);\n@@ -986,6 +1017,7 @@ static const struct eth_dev_ops cxgbe_eth_dev_ops = {\n \t.get_eeprom\t\t= cxgbe_get_eeprom,\n \t.set_eeprom\t\t= cxgbe_set_eeprom,\n \t.get_reg\t\t= cxgbe_get_regs,\n+\t.rss_hash_update\t= cxgbe_dev_rss_hash_update,\n };\n \n /*\ndiff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c\nindex c502fadf7..930c3dfdf 100644\n--- a/drivers/net/cxgbe/cxgbe_main.c\n+++ b/drivers/net/cxgbe/cxgbe_main.c\n@@ -360,6 +360,8 @@ static int init_rss(struct adapter *adap)\n \t\tpi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);\n \t\tif (!pi->rss)\n \t\t\treturn -ENOMEM;\n+\n+\t\tpi->rss_hf = ETH_RSS_TCP | ETH_RSS_UDP;\n \t}\n \treturn 0;\n }\n@@ -930,14 +932,67 @@ int link_start(struct port_info *pi)\n }\n \n /**\n- * cxgb4_write_rss - write the RSS table for a given port\n+ * cxgbe_write_rss_conf - flash the RSS configuration for a given port\n+ * @pi: the port\n+ * @rss_hf: Hash configuration to apply\n+ */\n+int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)\n+{\n+\tstruct adapter *adapter = pi->adapter;\n+\tconst struct sge_eth_rxq *rxq;\n+\tu64 flags = 0;\n+\tu16 rss;\n+\tint err;\n+\n+\t/* Should never be called before setting up sge eth rx queues */\n+\tif (!(adapter->flags & FULL_INIT_DONE)) {\n+\t\tdev_err(adap, \"%s No RXQs available on port %d\\n\",\n+\t\t\t__func__, pi->port_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rss_hf & ETH_RSS_IPV4)\n+\t\tflags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;\n+\n+\tif (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)\n+\t\tflags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;\n+\n+\tif (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)\n+\t\tflags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |\n+\t\t\t F_FW_RSS_VI_CONFIG_CMD_UDPEN;\n+\n+\tif (rss_hf & ETH_RSS_IPV6)\n+\t\tflags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;\n+\n+\tif (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)\n+\t\tflags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;\n+\n+\tif (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)\n+\t\tflags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |\n+\t\t\t F_FW_RSS_VI_CONFIG_CMD_UDPEN;\n+\n+\trxq = &adapter->sge.ethrxq[pi->first_qset];\n+\trss = rxq[0].rspq.abs_id;\n+\n+\t/* If Tunnel All Lookup isn't specified in the global RSS\n+\t * Configuration, then we need to specify a default Ingress\n+\t * Queue for any ingress packets which aren't hashed. We'll\n+\t * use our first ingress queue ...\n+\t */\n+\terr = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,\n+\t\t\t flags, rss);\n+\treturn err;\n+}\n+\n+/**\n+ * cxgbe_write_rss - write the RSS table for a given port\n * @pi: the port\n * @queues: array of queue indices for RSS\n *\n * Sets up the portion of the HW RSS table for the port's VI to distribute\n * packets to the Rx queues in @queues.\n */\n-int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)\n+int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)\n {\n \tu16 *rss;\n \tint i, err;\n@@ -958,20 +1013,6 @@ int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)\n \n \terr = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,\n \t\t\t\t pi->rss_size, rss, pi->rss_size);\n-\t/*\n-\t * If Tunnel All Lookup isn't specified in the global RSS\n-\t * Configuration, then we need to specify a default Ingress\n-\t * Queue for any ingress packets which aren't hashed. We'll\n-\t * use our first ingress queue ...\n-\t */\n-\tif (!err)\n-\t\terr = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,\n-\t\t\t\t F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |\n-\t\t\t\t F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |\n-\t\t\t\t F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |\n-\t\t\t\t F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN |\n-\t\t\t\t F_FW_RSS_VI_CONFIG_CMD_UDPEN,\n-\t\t\t\t rss[0]);\n \trte_free(rss);\n \treturn err;\n }\n@@ -1001,7 +1042,11 @@ int setup_rss(struct port_info *pi)\n \t\t\tfor (j = 0; j < pi->rss_size; j++)\n \t\t\t\tpi->rss[j] = j % pi->n_rx_qsets;\n \n-\t\t\terr = cxgb4_write_rss(pi, pi->rss);\n+\t\t\terr = cxgbe_write_rss(pi, pi->rss);\n+\t\t\tif (err)\n+\t\t\t\treturn err;\n+\n+\t\t\terr = cxgbe_write_rss_conf(pi, pi->rss_hf);\n \t\t\tif (err)\n \t\t\t\treturn err;\n \t\t\tpi->flags |= PORT_RSS_DONE;\n", "prefixes": [ "dpdk-dev", "3/7" ] }