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GET /api/patches/34886/?format=api
{ "id": 34886, "url": "http://patches.dpdk.org/api/patches/34886/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1517574310-93096-4-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1517574310-93096-4-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1517574310-93096-4-git-send-email-beilei.xing@intel.com", "date": "2018-02-02T12:25:09", "name": "[dpdk-dev,v3,3/4] net/i40e: fix multiple driver support issue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a3aaf27f0a20bbc4c37d866251360ce8942f2625", "submitter": { "id": 410, "url": "http://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1517574310-93096-4-git-send-email-beilei.xing@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/34886/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/34886/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A599D1B026;\n\tFri, 2 Feb 2018 13:24:54 +0100 (CET)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n\tby dpdk.org (Postfix) with ESMTP id 9EE60325F;\n\tFri, 2 Feb 2018 13:24:50 +0100 (CET)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t02 Feb 2018 04:24:49 -0800", "from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52])\n\tby orsmga004.jf.intel.com with ESMTP; 02 Feb 2018 04:24:48 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.46,448,1511856000\"; d=\"scan'208\";a=\"171140885\"", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "dev@dpdk.org,\n\tjingjing.wu@intel.com", "Cc": "stable@dpdk.org", "Date": "Fri, 2 Feb 2018 20:25:09 +0800", "Message-Id": "<1517574310-93096-4-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1517574310-93096-1-git-send-email-beilei.xing@intel.com>", "References": "<1517486402-81403-1-git-send-email-beilei.xing@intel.com>\n\t<1517574310-93096-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 3/4] net/i40e: fix multiple driver support\n\tissue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch provides the option to disable writing some global registers\nin PMD, in order to avoid affecting other drivers, when multiple drivers\nrun on the same NIC and control different physical ports. Because there\nare few global resources shared among different physical ports.\n\nFixes: ec246eeb5da1 (\"i40e: use default filter input set on init\")\nFixes: 98f055707685 (\"i40e: configure input fields for RSS or flow director\")\nFixes: f05ec7d77e41 (\"i40e: initialize flow director flexible payload setting\")\nFixes: e536c2e32883 (\"net/i40e: fix parsing QinQ packets type\")\nFixes: 19b16e2f6442 (\"ethdev: add vlan type when setting ether type\")\nCc: stable@dpdk.org\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 215 ++++++++++++++++++++++++++++++++---------\n drivers/net/i40e/i40e_ethdev.h | 2 +\n 2 files changed, 171 insertions(+), 46 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex ef23241..ae0f31a 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -944,6 +944,67 @@ config_floating_veb(struct rte_eth_dev *dev)\n #define I40E_L2_TAGS_S_TAG_SHIFT 1\n #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)\n \n+#define ETH_I40E_SUPPORT_MULTI_DRIVER\t\"support-multi-driver\"\n+RTE_PMD_REGISTER_PARAM_STRING(net_i40e,\n+\t\t\t ETH_I40E_SUPPORT_MULTI_DRIVER \"=0|1\");\n+\n+static int\n+i40e_parse_multi_drv_handler(__rte_unused const char *key,\n+\t\t\t const char *value,\n+\t\t\t void *opaque)\n+{\n+\tstruct i40e_pf *pf;\n+\tunsigned long support_multi_driver;\n+\tchar *end;\n+\n+\tpf = (struct i40e_pf *)opaque;\n+\n+\terrno = 0;\n+\tsupport_multi_driver = strtoul(value, &end, 10);\n+\tif (errno != 0 || end == value || *end != 0) {\n+\t\tPMD_DRV_LOG(WARNING, \"Wrong global configuration\");\n+\t\treturn -(EINVAL);\n+\t}\n+\n+\tif (support_multi_driver == 1 || support_multi_driver == 0)\n+\t\tpf->support_multi_driver = (bool)support_multi_driver;\n+\telse\n+\t\tPMD_DRV_LOG(WARNING, \"%s must be 1 or 0,\",\n+\t\t\t \"enable global configuration by default.\"\n+\t\t\t ETH_I40E_SUPPORT_MULTI_DRIVER);\n+\treturn 0;\n+}\n+\n+static int\n+i40e_support_multi_driver(struct rte_eth_dev *dev)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct rte_pci_device *pci_dev = dev->pci_dev;\n+\tstatic const char *valid_keys[] = {\n+\t\tETH_I40E_SUPPORT_MULTI_DRIVER, NULL};\n+\tstruct rte_kvargs *kvlist;\n+\n+\t/* Enable global configuration by default */\n+\tpf->support_multi_driver = false;\n+\n+\tif (!pci_dev->device.devargs)\n+\t\treturn 0;\n+\n+\tkvlist = rte_kvargs_parse(pci_dev->device.devargs->args, valid_keys);\n+\tif (!kvlist)\n+\t\treturn -EINVAL;\n+\n+\tif (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)\n+\t\tPMD_DRV_LOG(WARNING, \"More than one argument \\\"%s\\\" and only \"\n+\t\t\t \"the first invalid or last valid one is used !\",\n+\t\t\t ETH_I40E_SUPPORT_MULTI_DRIVER);\n+\n+\trte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,\n+\t\t\t i40e_parse_multi_drv_handler, pf);\n+\trte_kvargs_free(kvlist);\n+\treturn 0;\n+}\n+\n static int\n eth_i40e_dev_init(struct rte_eth_dev *dev)\n {\n@@ -993,6 +1054,9 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \thw->bus.func = pci_dev->addr.function;\n \thw->adapter_stopped = 0;\n \n+\t/* Check if need to support multi-driver */\n+\ti40e_support_multi_driver(dev);\n+\n \t/* Make sure all is clean before doing PF reset */\n \ti40e_clear_hw(hw);\n \n@@ -1019,7 +1083,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \t * software. It should be removed once issues are fixed\n \t * in NVM.\n \t */\n-\ti40e_GLQF_reg_init(hw);\n+\tif (!pf->support_multi_driver)\n+\t\ti40e_GLQF_reg_init(hw);\n \n \t/* Initialize the input set for filters (hash and fd) to default value */\n \ti40e_filter_input_set_init(pf);\n@@ -1115,11 +1180,14 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \ti40e_set_fc(hw, &aq_fail, TRUE);\n \n \t/* Set the global registers with default ether type value */\n-\tret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);\n-\tif (ret != I40E_SUCCESS) {\n-\t\tPMD_INIT_LOG(ERR, \"Failed to set the default outer \"\n-\t\t\t \"VLAN ether type\");\n-\t\tgoto err_setup_pf_switch;\n+\tif (!pf->support_multi_driver) {\n+\t\tret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,\n+\t\t\t\t\t ETHER_TYPE_VLAN);\n+\t\tif (ret != I40E_SUCCESS) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to set the default outer \"\n+\t\t\t\t \"VLAN ether type\");\n+\t\t\tgoto err_setup_pf_switch;\n+\t\t}\n \t}\n \n \t/* PF setup, which includes VSI setup */\n@@ -2754,11 +2822,17 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,\n \t\t uint16_t tpid)\n {\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tuint64_t reg_r = 0, reg_w = 0;\n \tuint16_t reg_id = 0;\n \tint ret = 0;\n \tint qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Setting TPID is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tswitch (vlan_type) {\n \tcase ETH_VLAN_TYPE_OUTER:\n \t\tif (qinq)\n@@ -3039,20 +3113,25 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n \t\tI40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);\n \t}\n \n-\t/* config the water marker both based on the packets and bytes */\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,\n-\t\t (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,\n-\t\t (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,\n-\t\t pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT);\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,\n-\t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT);\n-\ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n+\tif (!pf->support_multi_driver) {\n+\t\t/* config water marker both based on the packets and bytes */\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,\n+\t\t\t\t(pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,\n+\t\t\t\t(pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,\n+\t\t\t\t pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT);\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,\n+\t\t\t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t \"Water marker configuration is not supported.\");\n+\t}\n \n \tI40E_WRITE_FLUSH(hw);\n \n@@ -6870,9 +6949,15 @@ i40e_tunnel_filter_param_check(struct i40e_pf *pf,\n static int\n i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)\n {\n+\tstruct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;\n \tuint32_t val, reg;\n \tint ret = -EINVAL;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"GRE key length configuration is unsupported\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tval = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));\n \tPMD_DRV_LOG(DEBUG, \"Read original GL_PRS_FVBM with 0x%08x\\n\", val);\n \n@@ -7114,12 +7199,18 @@ static int\n i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t\t\t struct rte_eth_hash_global_conf *g_cfg)\n {\n+\tstruct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;\n \tint ret;\n \tuint16_t i;\n \tuint32_t reg;\n \tuint32_t mask0 = g_cfg->valid_bit_mask[0];\n \tenum i40e_filter_pctype pctype;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Hash global configuration is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \t/* Check the input parameters */\n \tret = i40e_hash_global_config_check(g_cfg);\n \tif (ret < 0)\n@@ -7850,6 +7941,12 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\t\t\t\t\t I40E_INSET_MASK_NUM_REG);\n \t\tif (num < 0)\n \t\t\treturn;\n+\n+\t\tif (pf->support_multi_driver && num > 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Input set setting is not supported.\");\n+\t\t\treturn;\n+\t\t}\n+\n \t\tinset_reg = i40e_translate_input_set_reg(hw->mac.type,\n \t\t\t\t\tinput_set);\n \n@@ -7858,39 +7955,49 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),\n \t\t\t\t (uint32_t)((inset_reg >>\n \t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n-\t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n-\t\t\t\t (uint32_t)((inset_reg >>\n-\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\n-\t\tfor (i = 0; i < num; i++) {\n+\t\tif (!pf->support_multi_driver) {\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t I40E_GLQF_HASH_INSET(0, pctype),\n+\t\t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n \t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t I40E_GLQF_HASH_INSET(1, pctype),\n+\t\t\t\t\t (uint32_t)((inset_reg >>\n+\t\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n+\n+\t\t\tfor (i = 0; i < num; i++) {\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n \t\t\t\t\t\t mask_reg[i]);\n-\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n \t\t\t\t\t\t mask_reg[i]);\n-\t\t}\n-\t\t/*clear unused mask registers of the pctype */\n-\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {\n-\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t}\n+\t\t\t/*clear unused mask registers of the pctype */\n+\t\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n \t\t\t\t\t\t 0);\n-\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t\t\t 0);\n+\t\t\t\t\t\t 0);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t \"Input set setting is not supported.\");\n \t\t}\n \t\tI40E_WRITE_FLUSH(hw);\n \n \t\t/* store the default input set */\n-\t\tpf->hash_input_set[pctype] = input_set;\n+\t\tif (!pf->support_multi_driver)\n+\t\t\tpf->hash_input_set[pctype] = input_set;\n \t\tpf->fdir.input_set[pctype] = input_set;\n \t}\n \n-\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n-\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n-\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n+\tif (!pf->support_multi_driver) {\n+\t\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n+\t}\n }\n \n int\n@@ -7903,6 +8010,11 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,\n \tuint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};\n \tint ret, i, num;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Hash input set setting is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tif (!conf) {\n \t\tPMD_DRV_LOG(ERR, \"Invalid pointer\");\n \t\treturn -EFAULT;\n@@ -8029,6 +8141,11 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \tif (num < 0)\n \t\treturn -EINVAL;\n \n+\tif (pf->support_multi_driver && num > 0) {\n+\t\tPMD_DRV_LOG(ERR, \"FDIR bit mask is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tinset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);\n \n \ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),\n@@ -8037,14 +8154,20 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \t\t\t (uint32_t)((inset_reg >>\n \t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \n-\tfor (i = 0; i < num; i++)\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t mask_reg[i]);\n-\t/*clear unused mask registers of the pctype */\n-\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t 0);\n-\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n+\tif (!pf->support_multi_driver) {\n+\t\tfor (i = 0; i < num; i++)\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t mask_reg[i]);\n+\t\t/*clear unused mask registers of the pctype */\n+\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t 0);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"FDIR bit mask is not supported.\");\n+\t}\n \tI40E_WRITE_FLUSH(hw);\n \n \tpf->fdir.input_set[pctype] = input_set;\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 12b6000..82d5501 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -485,6 +485,8 @@ struct i40e_pf {\n \tbool floating_veb; /* The flag to use the floating VEB */\n \t/* The floating enable flag for the specific VF */\n \tbool floating_veb_list[I40E_MAX_VF];\n+\n+\tbool support_multi_driver; /* 1 - support multiple driver */\n };\n \n enum pending_msg {\n", "prefixes": [ "dpdk-dev", "v3", "3/4" ] }