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GET /api/patches/34883/?format=api
{ "id": 34883, "url": "http://patches.dpdk.org/api/patches/34883/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1517573152-92442-5-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1517573152-92442-5-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1517573152-92442-5-git-send-email-beilei.xing@intel.com", "date": "2018-02-02T12:05:52", "name": "[dpdk-dev,v4,4/4] net/i40e: fix interrupt conflict when using multi-driver", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ca6bcff29265054ee6d6f78fbc361d78461a62a1", "submitter": { "id": 410, "url": "http://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 24, "url": "http://patches.dpdk.org/api/users/24/?format=api", "username": "helin_zhang", "first_name": "Helin", "last_name": "Zhang", "email": "helin.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1517573152-92442-5-git-send-email-beilei.xing@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/34883/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/34883/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E3A371B16F;\n\tFri, 2 Feb 2018 13:05:21 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id 729DBA499\n\tfor <dev@dpdk.org>; Fri, 2 Feb 2018 13:05:18 +0100 (CET)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t02 Feb 2018 04:05:17 -0800", "from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52])\n\tby orsmga005.jf.intel.com with ESMTP; 02 Feb 2018 04:05:17 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.46,448,1511856000\"; d=\"scan'208\";a=\"198139826\"", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "dev@dpdk.org,\n\tjingjing.wu@intel.com", "Date": "Fri, 2 Feb 2018 20:05:52 +0800", "Message-Id": "<1517573152-92442-5-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1517573152-92442-1-git-send-email-beilei.xing@intel.com>", "References": "<1517485772-80595-1-git-send-email-beilei.xing@intel.com>\n\t<1517573152-92442-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 4/4] net/i40e: fix interrupt conflict when\n\tusing multi-driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "There's interrupt conflict when using DPDK and Linux i40e\non different ports of the same Ethernet controller, this\npatch fixes it by switching from IntN to Int0 if multiple\ndrivers are used.\n\nFixes: be6c228d4da3 (\"i40e: support Rx interrupt\")\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 89 +++++++++++++++++++++++++--------------\n drivers/net/i40e/i40e_ethdev.h | 14 +++---\n drivers/net/i40e/i40e_ethdev_vf.c | 4 +-\n 3 files changed, 68 insertions(+), 39 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex bede5c5..149b98a 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -692,6 +692,23 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)\n \ti40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);\n }\n \n+static inline void i40e_config_automask(struct i40e_pf *pf)\n+{\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tuint32_t val;\n+\n+\t/* INTENA flag is not auto-cleared for interrupt */\n+\tval = I40E_READ_REG(hw, I40E_GLINT_CTL);\n+\tval |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |\n+\t\tI40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;\n+\n+\t/* If support multi-driver, PF will use INT0. */\n+\tif (!pf->support_multi_driver)\n+\t\tval |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;\n+\n+\tI40E_WRITE_REG(hw, I40E_GLINT_CTL, val);\n+}\n+\n #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808\n \n /*\n@@ -1173,6 +1190,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \t\treturn ret;\n \t}\n \n+\ti40e_config_automask(pf);\n+\n \ti40e_set_default_pctype_table(dev);\n \n \t/*\n@@ -1705,6 +1724,7 @@ __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,\n \tint i;\n \tuint32_t val;\n \tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n+\tstruct i40e_pf *pf = I40E_VSI_TO_PF(vsi);\n \n \t/* Bind all RX queues to allocated MSIX interrupt */\n \tfor (i = 0; i < nb_queue; i++) {\n@@ -1723,7 +1743,8 @@ __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,\n \t/* Write first RX queue to Link list register as the head element */\n \tif (vsi->type != I40E_VSI_SRIOV) {\n \t\tuint16_t interval =\n-\t\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);\n+\t\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,\n+\t\t\t\t\t pf->support_multi_driver);\n \n \t\tif (msix_vect == I40E_MISC_VEC_ID) {\n \t\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,\n@@ -1782,7 +1803,6 @@ i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)\n \tuint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);\n \tuint16_t queue_idx = 0;\n \tint record = 0;\n-\tuint32_t val;\n \tint i;\n \n \tfor (i = 0; i < vsi->nb_qps; i++) {\n@@ -1790,13 +1810,6 @@ i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)\n \t\tI40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);\n \t}\n \n-\t/* INTENA flag is not auto-cleared for interrupt */\n-\tval = I40E_READ_REG(hw, I40E_GLINT_CTL);\n-\tval |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |\n-\t\tI40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |\n-\t\tI40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;\n-\tI40E_WRITE_REG(hw, I40E_GLINT_CTL, val);\n-\n \t/* VF bind interrupt */\n \tif (vsi->type == I40E_VSI_SRIOV) {\n \t\t__vsi_queues_bind_intr(vsi, msix_vect,\n@@ -1853,27 +1866,22 @@ i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n-\tuint16_t interval = i40e_calc_itr_interval(\\\n-\t\tRTE_LIBRTE_I40E_ITR_INTERVAL, 1);\n+\tstruct i40e_pf *pf = I40E_VSI_TO_PF(vsi);\n \tuint16_t msix_intr, i;\n \n-\tif (rte_intr_allow_others(intr_handle))\n+\tif (rte_intr_allow_others(intr_handle) || !pf->support_multi_driver)\n \t\tfor (i = 0; i < vsi->nb_msix; i++) {\n \t\t\tmsix_intr = vsi->msix_intr + i;\n \t\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),\n \t\t\t\tI40E_PFINT_DYN_CTLN_INTENA_MASK |\n \t\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n-\t\t\t\t(0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n-\t\t\t\t(interval <<\n-\t\t\t\t I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));\n+\t\t\t\tI40E_PFINT_DYN_CTLN_ITR_INDX_MASK);\n \t\t}\n \telse\n \t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,\n \t\t\t I40E_PFINT_DYN_CTL0_INTENA_MASK |\n \t\t\t I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |\n-\t\t\t (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |\n-\t\t\t (interval <<\n-\t\t\t\tI40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));\n+\t\t\t I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);\n \n \tI40E_WRITE_FLUSH(hw);\n }\n@@ -1885,16 +1893,18 @@ i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n+\tstruct i40e_pf *pf = I40E_VSI_TO_PF(vsi);\n \tuint16_t msix_intr, i;\n \n-\tif (rte_intr_allow_others(intr_handle))\n+\tif (rte_intr_allow_others(intr_handle) || !pf->support_multi_driver)\n \t\tfor (i = 0; i < vsi->nb_msix; i++) {\n \t\t\tmsix_intr = vsi->msix_intr + i;\n \t\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),\n-\t\t\t\t 0);\n+\t\t\t\t I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);\n \t\t}\n \telse\n-\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);\n+\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,\n+\t\t\t I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);\n \n \tI40E_WRITE_FLUSH(hw);\n }\n@@ -5175,16 +5185,28 @@ i40e_vsi_setup(struct i40e_pf *pf,\n \n \t/* VF has MSIX interrupt in VF range, don't allocate here */\n \tif (type == I40E_VSI_MAIN) {\n-\t\tret = i40e_res_pool_alloc(&pf->msix_pool,\n-\t\t\t\t\t RTE_MIN(vsi->nb_qps,\n-\t\t\t\t\t\t RTE_MAX_RXTX_INTR_VEC_ID));\n-\t\tif (ret < 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"VSI MAIN %d get heap failed %d\",\n-\t\t\t\t vsi->seid, ret);\n-\t\t\tgoto fail_queue_alloc;\n+\t\tif (pf->support_multi_driver) {\n+\t\t\t/* If support multi-driver, need to use INT0 instead of\n+\t\t\t * allocating from msix pool. The Msix pool is init from\n+\t\t\t * INT1, so it's OK just set msix_intr to 0 and nb_msix\n+\t\t\t * to 1 without calling i40e_res_pool_alloc.\n+\t\t\t */\n+\t\t\tvsi->msix_intr = 0;\n+\t\t\tvsi->nb_msix = 1;\n+\t\t} else {\n+\t\t\tret = i40e_res_pool_alloc(&pf->msix_pool,\n+\t\t\t\t\t\t RTE_MIN(vsi->nb_qps,\n+\t\t\t\t\t\t RTE_MAX_RXTX_INTR_VEC_ID));\n+\t\t\tif (ret < 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\t \"VSI MAIN %d get heap failed %d\",\n+\t\t\t\t\t vsi->seid, ret);\n+\t\t\t\tgoto fail_queue_alloc;\n+\t\t\t}\n+\t\t\tvsi->msix_intr = ret;\n+\t\t\tvsi->nb_msix = RTE_MIN(vsi->nb_qps,\n+\t\t\t\t\t RTE_MAX_RXTX_INTR_VEC_ID);\n \t\t}\n-\t\tvsi->msix_intr = ret;\n-\t\tvsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);\n \t} else if (type != I40E_VSI_SRIOV) {\n \t\tret = i40e_res_pool_alloc(&pf->msix_pool, 1);\n \t\tif (ret < 0) {\n@@ -6101,7 +6123,8 @@ void\n i40e_pf_disable_irq0(struct i40e_hw *hw)\n {\n \t/* Disable all interrupt types */\n-\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);\n+\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,\n+\t\t I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);\n \tI40E_WRITE_FLUSH(hw);\n }\n \n@@ -11089,11 +11112,13 @@ i40e_dev_get_dcb_info(struct rte_eth_dev *dev,\n static int\n i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n {\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint16_t interval =\n-\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);\n+\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,\n+\t\t\t\t pf->support_multi_driver);\n \tuint16_t msix_intr;\n \n \tmsix_intr = intr_handle->intr_vec[queue_id];\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex deefb11..99efb67 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -1292,13 +1292,17 @@ i40e_align_floor(int n)\n }\n \n static inline uint16_t\n-i40e_calc_itr_interval(int16_t interval, bool is_pf)\n+i40e_calc_itr_interval(int16_t interval, bool is_pf, bool is_multi_drv)\n {\n \tif (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) {\n-\t\tif (is_pf)\n-\t\t\tinterval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;\n-\t\telse\n-\t\t\tinterval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;\n+\t\tif (is_multi_drv) {\n+\t\t\tinterval = I40E_QUEUE_ITR_INTERVAL_MAX;\n+\t\t} else {\n+\t\t\tif (is_pf)\n+\t\t\t\tinterval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;\n+\t\t\telse\n+\t\t\t\tinterval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;\n+\t\t}\n \t}\n \n \t/* Convert to hardware count, as writing each 1 represents 2 us */\ndiff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c\nindex 57f7613..3c75243 100644\n--- a/drivers/net/i40e/i40e_ethdev_vf.c\n+++ b/drivers/net/i40e/i40e_ethdev_vf.c\n@@ -1138,7 +1138,7 @@ i40evf_init_vf(struct rte_eth_dev *dev)\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n \tuint16_t interval =\n-\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 0);\n+\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 0, 0);\n \n \tvf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tvf->dev_data = dev->data;\n@@ -1841,7 +1841,7 @@ i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint16_t interval =\n-\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 0);\n+\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 0, 0);\n \tuint16_t msix_intr;\n \n \tmsix_intr = intr_handle->intr_vec[queue_id];\n", "prefixes": [ "dpdk-dev", "v4", "4/4" ] }