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GET /api/patches/34882/?format=api
{ "id": 34882, "url": "http://patches.dpdk.org/api/patches/34882/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1517573152-92442-4-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1517573152-92442-4-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1517573152-92442-4-git-send-email-beilei.xing@intel.com", "date": "2018-02-02T12:05:51", "name": "[dpdk-dev,v4,3/4] net/i40e: fix multiple driver support issue", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "10a4f73e5a522130446d530a1ceb6727133ae5d8", "submitter": { "id": 410, "url": "http://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 24, "url": "http://patches.dpdk.org/api/users/24/?format=api", "username": "helin_zhang", "first_name": "Helin", "last_name": "Zhang", "email": "helin.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1517573152-92442-4-git-send-email-beilei.xing@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/34882/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/34882/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E77801B16C;\n\tFri, 2 Feb 2018 13:05:20 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id AFE7BA499\n\tfor <dev@dpdk.org>; Fri, 2 Feb 2018 13:05:17 +0100 (CET)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t02 Feb 2018 04:05:17 -0800", "from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52])\n\tby orsmga005.jf.intel.com with ESMTP; 02 Feb 2018 04:05:16 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.46,448,1511856000\"; d=\"scan'208\";a=\"198139819\"", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "dev@dpdk.org,\n\tjingjing.wu@intel.com", "Date": "Fri, 2 Feb 2018 20:05:51 +0800", "Message-Id": "<1517573152-92442-4-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1517573152-92442-1-git-send-email-beilei.xing@intel.com>", "References": "<1517485772-80595-1-git-send-email-beilei.xing@intel.com>\n\t<1517573152-92442-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 3/4] net/i40e: fix multiple driver support\n\tissue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch provides the option to disable writing some global registers\nin PMD, in order to avoid affecting other drivers, when multiple drivers\nrun on the same NIC and control different physical ports. Because there\nare few global resources shared among different physical ports.\n\nFixes: ec246eeb5da1 (\"i40e: use default filter input set on init\")\nFixes: 98f055707685 (\"i40e: configure input fields for RSS or flow director\")\nFixes: f05ec7d77e41 (\"i40e: initialize flow director flexible payload setting\")\nFixes: e536c2e32883 (\"net/i40e: fix parsing QinQ packets type\")\nFixes: 19b16e2f6442 (\"ethdev: add vlan type when setting ether type\")\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 262 ++++++++++++++++++++++++++++++++---------\n drivers/net/i40e/i40e_ethdev.h | 1 +\n drivers/net/i40e/i40e_fdir.c | 39 +++---\n drivers/net/i40e/i40e_flow.c | 8 ++\n 4 files changed, 240 insertions(+), 70 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex aad00aa..bede5c5 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -1039,6 +1039,64 @@ i40e_init_queue_region_conf(struct rte_eth_dev *dev)\n \tmemset(info, 0, sizeof(struct i40e_queue_regions));\n }\n \n+#define ETH_I40E_SUPPORT_MULTI_DRIVER\t\"support-multi-driver\"\n+\n+static int\n+i40e_parse_multi_drv_handler(__rte_unused const char *key,\n+\t\t\t const char *value,\n+\t\t\t void *opaque)\n+{\n+\tstruct i40e_pf *pf;\n+\tunsigned long support_multi_driver;\n+\tchar *end;\n+\n+\tpf = (struct i40e_pf *)opaque;\n+\n+\terrno = 0;\n+\tsupport_multi_driver = strtoul(value, &end, 10);\n+\tif (errno != 0 || end == value || *end != 0) {\n+\t\tPMD_DRV_LOG(WARNING, \"Wrong global configuration\");\n+\t\treturn -(EINVAL);\n+\t}\n+\n+\tif (support_multi_driver == 1 || support_multi_driver == 0)\n+\t\tpf->support_multi_driver = (bool)support_multi_driver;\n+\telse\n+\t\tPMD_DRV_LOG(WARNING, \"%s must be 1 or 0,\",\n+\t\t\t \"enable global configuration by default.\"\n+\t\t\t ETH_I40E_SUPPORT_MULTI_DRIVER);\n+\treturn 0;\n+}\n+\n+static int\n+i40e_support_multi_driver(struct rte_eth_dev *dev)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstatic const char *const valid_keys[] = {\n+\t\tETH_I40E_SUPPORT_MULTI_DRIVER, NULL};\n+\tstruct rte_kvargs *kvlist;\n+\n+\t/* Enable global configuration by default */\n+\tpf->support_multi_driver = false;\n+\n+\tif (!dev->device->devargs)\n+\t\treturn 0;\n+\n+\tkvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);\n+\tif (!kvlist)\n+\t\treturn -EINVAL;\n+\n+\tif (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)\n+\t\tPMD_DRV_LOG(WARNING, \"More than one argument \\\"%s\\\" and only \"\n+\t\t\t \"the first invalid or last valid one is used !\",\n+\t\t\t ETH_I40E_SUPPORT_MULTI_DRIVER);\n+\n+\trte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,\n+\t\t\t i40e_parse_multi_drv_handler, pf);\n+\trte_kvargs_free(kvlist);\n+\treturn 0;\n+}\n+\n static int\n eth_i40e_dev_init(struct rte_eth_dev *dev)\n {\n@@ -1092,6 +1150,9 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \thw->bus.func = pci_dev->addr.function;\n \thw->adapter_stopped = 0;\n \n+\t/* Check if need to support multi-driver */\n+\ti40e_support_multi_driver(dev);\n+\n \t/* Make sure all is clean before doing PF reset */\n \ti40e_clear_hw(hw);\n \n@@ -1119,7 +1180,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \t * for packet type of QinQ by software.\n \t * It should be removed once issues are fixed in NVM.\n \t */\n-\ti40e_GLQF_reg_init(hw);\n+\tif (!pf->support_multi_driver)\n+\t\ti40e_GLQF_reg_init(hw);\n \n \t/* Initialize the input set for filters (hash and fd) to default value */\n \ti40e_filter_input_set_init(pf);\n@@ -1139,13 +1201,17 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \t\t (hw->nvm.version & 0xf), hw->nvm.eetrack);\n \n \t/* initialise the L3_MAP register */\n-\tret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),\n-\t\t\t\t 0x00000028,\tNULL);\n-\tif (ret)\n-\t\tPMD_INIT_LOG(ERR, \"Failed to write L3 MAP register %d\", ret);\n-\tPMD_INIT_LOG(DEBUG, \"Global register 0x%08x is changed with value 0x28\",\n-\t\t I40E_GLQF_L3_MAP(40));\n-\ti40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);\n+\tif (!pf->support_multi_driver) {\n+\t\tret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),\n+\t\t\t\t\t\t 0x00000028,\tNULL);\n+\t\tif (ret)\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to write L3 MAP register %d\",\n+\t\t\t\t ret);\n+\t\tPMD_INIT_LOG(DEBUG,\n+\t\t\t \"Global register 0x%08x is changed with 0x28\",\n+\t\t\t I40E_GLQF_L3_MAP(40));\n+\t\ti40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);\n+\t}\n \n \t/* Need the special FW version to support floating VEB */\n \tconfig_floating_veb(dev);\n@@ -1221,11 +1287,15 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \ti40e_set_fc(hw, &aq_fail, TRUE);\n \n \t/* Set the global registers with default ether type value */\n-\tret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);\n-\tif (ret != I40E_SUCCESS) {\n-\t\tPMD_INIT_LOG(ERR,\n-\t\t\t\"Failed to set the default outer VLAN ether type\");\n-\t\tgoto err_setup_pf_switch;\n+\tif (!pf->support_multi_driver) {\n+\t\tret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,\n+\t\t\t\t\t ETHER_TYPE_VLAN);\n+\t\tif (ret != I40E_SUCCESS) {\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t \"Failed to set the default outer \"\n+\t\t\t\t \"VLAN ether type\");\n+\t\t\tgoto err_setup_pf_switch;\n+\t\t}\n \t}\n \n \t/* PF setup, which includes VSI setup */\n@@ -1291,7 +1361,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \trte_intr_enable(intr_handle);\n \n \t/* By default disable flexible payload in global configuration */\n-\ti40e_flex_payload_reg_set_default(hw);\n+\tif (!pf->support_multi_driver)\n+\t\ti40e_flex_payload_reg_set_default(hw);\n \n \t/*\n \t * Add an ethertype filter to drop all flow control frames transmitted\n@@ -2225,7 +2296,8 @@ i40e_dev_close(struct rte_eth_dev *dev)\n \ti40e_res_pool_destroy(&pf->msix_pool);\n \n \t/* Disable flexible payload in global configuration */\n-\ti40e_flex_payload_reg_set_default(hw);\n+\tif (!pf->support_multi_driver)\n+\t\ti40e_flex_payload_reg_set_default(hw);\n \n \t/* force a PF reset to clean anything leftover */\n \treg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);\n@@ -3242,6 +3314,7 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,\n \t\t uint16_t tpid)\n {\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tint qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;\n \tint ret = 0;\n \n@@ -3252,6 +3325,12 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,\n \t\t\t \"Unsupported vlan type.\");\n \t\treturn -EINVAL;\n \t}\n+\n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Setting TPID is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \t/* 802.1ad frames ability is added in NVM API 1.7*/\n \tif (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {\n \t\tif (qinq) {\n@@ -3504,20 +3583,25 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n \t\tI40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);\n \t}\n \n-\t/* config the water marker both based on the packets and bytes */\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,\n-\t\t (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,\n-\t\t (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,\n-\t\t pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT);\n-\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,\n-\t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n-\t\t << I40E_KILOSHIFT);\n-\ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n+\tif (!pf->support_multi_driver) {\n+\t\t/* config water marker both based on the packets and bytes */\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,\n+\t\t\t\t (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,\n+\t\t\t\t (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,\n+\t\t\t\t pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT);\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,\n+\t\t\t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t\t\t << I40E_KILOSHIFT);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t \"Water marker configuration is not supported.\");\n+\t}\n \n \tI40E_WRITE_FLUSH(hw);\n \n@@ -4050,7 +4134,6 @@ i40e_get_cap(struct i40e_hw *hw)\n \n #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF\t4\n #define QUEUE_NUM_PER_VF_ARG\t\t\t\"queue-num-per-vf\"\n-RTE_PMD_REGISTER_PARAM_STRING(net_i40e,\tQUEUE_NUM_PER_VF_ARG \"=1|2|4|8|16\");\n \n static int i40e_pf_parse_vf_queue_number_handler(const char *key,\n \t\tconst char *value,\n@@ -7264,6 +7347,11 @@ i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)\n \tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n \tenum i40e_status_code status = I40E_SUCCESS;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Replace l1 filter is not supported.\");\n+\t\treturn I40E_NOT_SUPPORTED;\n+\t}\n+\n \tmemset(&filter_replace, 0,\n \t sizeof(struct i40e_aqc_replace_cloud_filters_cmd));\n \tmemset(&filter_replace_buf, 0,\n@@ -7318,6 +7406,11 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)\n \tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n \tenum i40e_status_code status = I40E_SUCCESS;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Replace cloud filter is not supported.\");\n+\t\treturn I40E_NOT_SUPPORTED;\n+\t}\n+\n \t/* For MPLSoUDP */\n \tmemset(&filter_replace, 0,\n \t sizeof(struct i40e_aqc_replace_cloud_filters_cmd));\n@@ -7383,6 +7476,11 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf)\n \tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n \tenum i40e_status_code status = I40E_SUCCESS;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Replace l1 filter is not supported.\");\n+\t\treturn I40E_NOT_SUPPORTED;\n+\t}\n+\n \t/* For GTP-C */\n \tmemset(&filter_replace, 0,\n \t sizeof(struct i40e_aqc_replace_cloud_filters_cmd));\n@@ -7461,6 +7559,11 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)\n \tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n \tenum i40e_status_code status = I40E_SUCCESS;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Replace cloud filter is not supported.\");\n+\t\treturn I40E_NOT_SUPPORTED;\n+\t}\n+\n \t/* for GTP-C */\n \tmemset(&filter_replace, 0,\n \t sizeof(struct i40e_aqc_replace_cloud_filters_cmd));\n@@ -8042,9 +8145,15 @@ i40e_tunnel_filter_param_check(struct i40e_pf *pf,\n static int\n i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)\n {\n+\tstruct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;\n \tuint32_t val, reg;\n \tint ret = -EINVAL;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"GRE key length configuration is unsupported\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tval = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));\n \tPMD_DRV_LOG(DEBUG, \"Read original GL_PRS_FVBM with 0x%08x\", val);\n \n@@ -8299,11 +8408,17 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t\t\t struct rte_eth_hash_global_conf *g_cfg)\n {\n \tstruct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;\n+\tstruct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;\n \tint ret;\n \tuint16_t i, j;\n \tuint32_t reg;\n \tuint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Hash global configuration is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \t/* Check the input parameters */\n \tret = i40e_hash_global_config_check(adapter, g_cfg);\n \tif (ret < 0)\n@@ -8975,6 +9090,10 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\t\t\t\t\t I40E_INSET_MASK_NUM_REG);\n \t\tif (num < 0)\n \t\t\treturn;\n+\t\tif (pf->support_multi_driver && num > 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Input set setting is not supported.\");\n+\t\t\treturn;\n+\t\t}\n \t\tinset_reg = i40e_translate_input_set_reg(hw->mac.type,\n \t\t\t\t\tinput_set);\n \n@@ -8983,39 +9102,48 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),\n \t\t\t\t (uint32_t)((inset_reg >>\n \t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n-\t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n-\t\t\t\t (uint32_t)((inset_reg >>\n-\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\n-\t\tfor (i = 0; i < num; i++) {\n+\t\tif (!pf->support_multi_driver) {\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t I40E_GLQF_HASH_INSET(0, pctype),\n+\t\t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n \t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t I40E_GLQF_HASH_INSET(1, pctype),\n+\t\t\t\t\t (uint32_t)((inset_reg >>\n+\t\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n+\n+\t\t\tfor (i = 0; i < num; i++) {\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n \t\t\t\t\t\t mask_reg[i]);\n-\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n \t\t\t\t\t\t mask_reg[i]);\n-\t\t}\n-\t\t/*clear unused mask registers of the pctype */\n-\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {\n-\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t}\n+\t\t\t/*clear unused mask registers of the pctype */\n+\t\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n \t\t\t\t\t\t 0);\n-\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\ti40e_check_write_global_reg(hw,\n \t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n \t\t\t\t\t\t 0);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tPMD_DRV_LOG(ERR, \"Input set setting is not supported.\");\n \t\t}\n \t\tI40E_WRITE_FLUSH(hw);\n \n \t\t/* store the default input set */\n-\t\tpf->hash_input_set[pctype] = input_set;\n+\t\tif (!pf->support_multi_driver)\n+\t\t\tpf->hash_input_set[pctype] = input_set;\n \t\tpf->fdir.input_set[pctype] = input_set;\n \t}\n \n-\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n-\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n-\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n+\tif (!pf->support_multi_driver) {\n+\t\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n+\t}\n }\n \n int\n@@ -9038,6 +9166,11 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,\n \t\treturn -EINVAL;\n \t}\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Hash input set setting is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tpctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);\n \tif (pctype == I40E_FILTER_PCTYPE_INVALID) {\n \t\tPMD_DRV_LOG(ERR, \"invalid flow_type input.\");\n@@ -9143,6 +9276,10 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \t\t\t\t\t I40E_INSET_MASK_NUM_REG);\n \tif (num < 0)\n \t\treturn -EINVAL;\n+\tif (pf->support_multi_driver && num > 0) {\n+\t\tPMD_DRV_LOG(ERR, \"FDIR bit mask is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n \n \tinset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);\n \n@@ -9152,14 +9289,20 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \t\t\t (uint32_t)((inset_reg >>\n \t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \n-\tfor (i = 0; i < num; i++)\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t mask_reg[i]);\n-\t/*clear unused mask registers of the pctype */\n-\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t 0);\n-\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n+\tif (!pf->support_multi_driver) {\n+\t\tfor (i = 0; i < num; i++)\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t mask_reg[i]);\n+\t\t/*clear unused mask registers of the pctype */\n+\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t 0);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"FDIR bit mask is not supported.\");\n+\t}\n \tI40E_WRITE_FLUSH(hw);\n \n \tpf->fdir.input_set[pctype] = input_set;\n@@ -11676,6 +11819,11 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf)\n \tstruct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;\n \tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n \n+\tif (pf->support_multi_driver) {\n+\t\tPMD_DRV_LOG(ERR, \"Replace cloud filter is not supported.\");\n+\t\treturn ret;\n+\t}\n+\n \t/* Init */\n \tmemset(&filter_replace, 0,\n \t sizeof(struct i40e_aqc_replace_cloud_filters_cmd));\n@@ -11828,3 +11976,7 @@ i40e_init_log(void)\n \tif (i40e_logtype_driver >= 0)\n \t\trte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);\n }\n+\n+RTE_PMD_REGISTER_PARAM_STRING(net_i40e,\n+\t\t\t QUEUE_NUM_PER_VF_ARG \"=1|2|4|8|16\"\n+\t\t\t ETH_I40E_SUPPORT_MULTI_DRIVER \"=1\");\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 12da379..deefb11 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -950,6 +950,7 @@ struct i40e_pf {\n \tbool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */\n \tbool qinq_replace_flag; /* QINQ filter replace is done */\n \tstruct i40e_tm_conf tm_conf;\n+\tbool support_multi_driver; /* 1 - support multiple driver */\n \n \t/* Dynamic Device Personalization */\n \tbool gtp_support; /* 1 - support GTP-C and GTP-U */\ndiff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c\nindex 97c6d4f..b83a0cf 100644\n--- a/drivers/net/i40e/i40e_fdir.c\n+++ b/drivers/net/i40e/i40e_fdir.c\n@@ -649,22 +649,31 @@ i40e_fdir_configure(struct rte_eth_dev *dev)\n \t\tPMD_DRV_LOG(ERR, \" invalid configuration arguments.\");\n \t\treturn -EINVAL;\n \t}\n-\t/* configure flex payload */\n-\tfor (i = 0; i < conf->nb_payloads; i++)\n-\t\ti40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);\n-\t/* configure flex mask*/\n-\tfor (i = 0; i < conf->nb_flexmasks; i++) {\n-\t\tif (hw->mac.type == I40E_MAC_X722) {\n-\t\t\t/* get translated pctype value in fd pctype register */\n-\t\t\tpctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(\n-\t\t\t\thw, I40E_GLQF_FD_PCTYPES(\n-\t\t\t\t(int)i40e_flowtype_to_pctype(pf->adapter,\n-\t\t\t\tconf->flex_mask[i].flow_type)));\n-\t\t} else\n-\t\t\tpctype = i40e_flowtype_to_pctype(pf->adapter,\n-\t\t\t\t\t\tconf->flex_mask[i].flow_type);\n \n-\t\ti40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);\n+\tif (!pf->support_multi_driver) {\n+\t\t/* configure flex payload */\n+\t\tfor (i = 0; i < conf->nb_payloads; i++)\n+\t\t\ti40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);\n+\t\t/* configure flex mask*/\n+\t\tfor (i = 0; i < conf->nb_flexmasks; i++) {\n+\t\t\tif (hw->mac.type == I40E_MAC_X722) {\n+\t\t\t\t/* get pctype value in fd pctype register */\n+\t\t\t\tpctype = (enum i40e_filter_pctype)\n+\t\t\t\t\t i40e_read_rx_ctl(hw,\n+\t\t\t\t\t\tI40E_GLQF_FD_PCTYPES(\n+\t\t\t\t\t\t(int)i40e_flowtype_to_pctype(\n+\t\t\t\t\t\tpf->adapter,\n+\t\t\t\t\t\tconf->flex_mask[i].flow_type)));\n+\t\t\t} else {\n+\t\t\t\tpctype = i40e_flowtype_to_pctype(pf->adapter,\n+\t\t\t\t\t\t conf->flex_mask[i].flow_type);\n+\t\t\t}\n+\n+\t\t\ti40e_set_flex_mask_on_pctype(pf, pctype,\n+\t\t\t\t\t\t &conf->flex_mask[i]);\n+\t\t}\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"Not support flexible payload.\");\n \t}\n \n \treturn ret;\ndiff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c\nindex 30b0db8..b7ef3b2 100644\n--- a/drivers/net/i40e/i40e_flow.c\n+++ b/drivers/net/i40e/i40e_flow.c\n@@ -2851,6 +2851,14 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,\n \t\t\t\treturn -rte_errno;\n \t\t\t}\n \n+\t\t\tif (pf->support_multi_driver) {\n+\t\t\t\trte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\t item,\n+\t\t\t\t\t\t \"Unsupported flexible payload.\");\n+\t\t\t\treturn -rte_errno;\n+\t\t\t}\n+\n \t\t\tret = i40e_flow_check_raw_item(item, raw_spec, error);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n", "prefixes": [ "dpdk-dev", "v4", "3/4" ] }