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GET /api/patches/34881/?format=api
{ "id": 34881, "url": "http://patches.dpdk.org/api/patches/34881/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1517573152-92442-3-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1517573152-92442-3-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1517573152-92442-3-git-send-email-beilei.xing@intel.com", "date": "2018-02-02T12:05:50", "name": "[dpdk-dev,v4,2/4] net/i40e: add debug logs when writing global registers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0f732f10ea5272c2ab85e52af0ea19a4739803ff", "submitter": { "id": 410, "url": "http://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 24, "url": "http://patches.dpdk.org/api/users/24/?format=api", "username": "helin_zhang", "first_name": "Helin", "last_name": "Zhang", "email": "helin.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1517573152-92442-3-git-send-email-beilei.xing@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/34881/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/34881/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1A6C11B026;\n\tFri, 2 Feb 2018 13:05:19 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id D9DBBA499\n\tfor <dev@dpdk.org>; Fri, 2 Feb 2018 13:05:16 +0100 (CET)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t02 Feb 2018 04:05:16 -0800", "from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52])\n\tby orsmga005.jf.intel.com with ESMTP; 02 Feb 2018 04:05:15 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.46,448,1511856000\"; d=\"scan'208\";a=\"198139815\"", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "dev@dpdk.org,\n\tjingjing.wu@intel.com", "Date": "Fri, 2 Feb 2018 20:05:50 +0800", "Message-Id": "<1517573152-92442-3-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1517573152-92442-1-git-send-email-beilei.xing@intel.com>", "References": "<1517485772-80595-1-git-send-email-beilei.xing@intel.com>\n\t<1517573152-92442-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 2/4] net/i40e: add debug logs when writing\n\tglobal registers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add debug logs when writing global registers.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 153 ++++++++++++++++++++++++++++++-----------\n drivers/net/i40e/i40e_ethdev.h | 11 +++\n 2 files changed, 123 insertions(+), 41 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex b4a2857..aad00aa 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -656,6 +656,15 @@ rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+static inline void\n+i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)\n+{\n+\ti40e_write_rx_ctl(hw, reg_addr, reg_val);\n+\tPMD_DRV_LOG(DEBUG, \"Global register 0x%08x is modified \"\n+\t\t \"with value 0x%08x\",\n+\t\t reg_addr, reg_val);\n+}\n+\n RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);\n RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);\n RTE_PMD_REGISTER_KMOD_DEP(net_i40e, \"* igb_uio | uio_pci_generic | vfio-pci\");\n@@ -678,8 +687,8 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)\n \t * configuration API is added to avoid configuration conflicts\n \t * between ports of the same device.\n \t */\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);\n-\tI40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);\n \ti40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);\n }\n \n@@ -1134,6 +1143,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \t\t\t\t 0x00000028,\tNULL);\n \tif (ret)\n \t\tPMD_INIT_LOG(ERR, \"Failed to write L3 MAP register %d\", ret);\n+\tPMD_INIT_LOG(DEBUG, \"Global register 0x%08x is changed with value 0x28\",\n+\t\t I40E_GLQF_L3_MAP(40));\n \ti40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);\n \n \t/* Need the special FW version to support floating VEB */\n@@ -1412,9 +1423,9 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)\n \t * Disable by default flexible payload\n \t * for corresponding L2/L3/L4 layers.\n \t */\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);\n-\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);\n \ti40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);\n }\n \n@@ -3219,8 +3230,8 @@ i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,\n \t\treturn -EIO;\n \t}\n \tPMD_DRV_LOG(DEBUG,\n-\t\t \"Debug write 0x%08\"PRIx64\" to I40E_GL_SWT_L2TAGCTRL[%d]\",\n-\t\t reg_w, reg_id);\n+\t\t \"Global register 0x%08x is changed with value 0x%08x\",\n+\t\t I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);\n \n \treturn 0;\n }\n@@ -3494,16 +3505,16 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n \t}\n \n \t/* config the water marker both based on the packets and bytes */\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_PHW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,\n \t\t (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_PLW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,\n \t\t (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_GHW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,\n \t\t pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT);\n-\tI40E_WRITE_REG(hw, I40E_GLRPB_GLW,\n+\tI40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,\n \t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT);\n \ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n@@ -7289,8 +7300,13 @@ i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)\n \n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n-\tif (!status)\n+\tif (!status) {\n \t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n+\t\tPMD_DRV_LOG(DEBUG, \"Global configuration modification: \"\n+\t\t\t \"cloud l1 type is changed from 0x%x to 0x%x\",\n+\t\t\t filter_replace.old_filter_type,\n+\t\t\t filter_replace.new_filter_type);\n+\t}\n \treturn status;\n }\n \n@@ -7323,6 +7339,10 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)\n \t\t\t\t\t &filter_replace_buf);\n \tif (status < 0)\n \t\treturn status;\n+\tPMD_DRV_LOG(DEBUG, \"Global configuration modification: \"\n+\t\t \"cloud filter type is changed from 0x%x to 0x%x\",\n+\t\t filter_replace.old_filter_type,\n+\t\t filter_replace.new_filter_type);\n \n \t/* For MPLSoGRE */\n \tmemset(&filter_replace, 0,\n@@ -7345,8 +7365,13 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)\n \n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n-\tif (!status)\n+\tif (!status) {\n \t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n+\t\tPMD_DRV_LOG(DEBUG, \"Global configuration modification: \"\n+\t\t\t \"cloud filter type is changed from 0x%x to 0x%x\",\n+\t\t\t filter_replace.old_filter_type,\n+\t\t\t filter_replace.new_filter_type);\n+\t}\n \treturn status;\n }\n \n@@ -7386,6 +7411,10 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf)\n \t\t\t\t\t &filter_replace_buf);\n \tif (status < 0)\n \t\treturn status;\n+\tPMD_DRV_LOG(DEBUG, \"Global configuration modification: \"\n+\t\t \"cloud l1 type is changed from 0x%x to 0x%x\",\n+\t\t filter_replace.old_filter_type,\n+\t\t filter_replace.new_filter_type);\n \n \t/* for GTP-U */\n \tmemset(&filter_replace, 0,\n@@ -7414,8 +7443,13 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf)\n \n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n-\tif (!status)\n+\tif (!status) {\n \t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n+\t\tPMD_DRV_LOG(DEBUG, \"Global configuration modification: \"\n+\t\t\t \"cloud l1 type is changed from 0x%x to 0x%x\",\n+\t\t\t filter_replace.old_filter_type,\n+\t\t\t filter_replace.new_filter_type);\n+\t}\n \treturn status;\n }\n \n@@ -7447,6 +7481,10 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)\n \t\t\t\t\t &filter_replace_buf);\n \tif (status < 0)\n \t\treturn status;\n+\tPMD_DRV_LOG(DEBUG, \"Global configuration modification: \"\n+\t\t \"cloud filter type is changed from 0x%x to 0x%x\",\n+\t\t filter_replace.old_filter_type,\n+\t\t filter_replace.new_filter_type);\n \n \t/* for GTP-U */\n \tmemset(&filter_replace, 0,\n@@ -7468,8 +7506,13 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)\n \n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n-\tif (!status)\n+\tif (!status) {\n \t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n+\t\tPMD_DRV_LOG(DEBUG, \"Global configuration modification: \"\n+\t\t\t \"cloud filter type is changed from 0x%x to 0x%x\",\n+\t\t\t filter_replace.old_filter_type,\n+\t\t\t filter_replace.new_filter_type);\n+\t}\n \treturn status;\n }\n \n@@ -8019,6 +8062,9 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)\n \t\t\t\t\t\t reg, NULL);\n \t\tif (ret != 0)\n \t\t\treturn ret;\n+\t\tPMD_DRV_LOG(DEBUG, \"Global register 0x%08x is changed \"\n+\t\t\t \"with value 0x%08x\",\n+\t\t\t I40E_GL_PRS_FVBM(2), reg);\n \t\ti40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);\n \t} else {\n \t\tret = 0;\n@@ -8275,7 +8321,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t\tfor (j = I40E_FILTER_PCTYPE_INVALID + 1;\n \t\t\t j < I40E_FILTER_PCTYPE_MAX; j++) {\n \t\t\t\tif (adapter->pctypes_tbl[i] & (1ULL << j))\n-\t\t\t\t\ti40e_write_rx_ctl(hw,\n+\t\t\t\t\ti40e_write_global_rx_ctl(hw,\n \t\t\t\t\t\t\t I40E_GLQF_HSYM(j),\n \t\t\t\t\t\t\t reg);\n \t\t\t}\n@@ -8304,7 +8350,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t/* Use the default, and keep it as it is */\n \t\tgoto out;\n \n-\ti40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);\n+\ti40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);\n \ti40e_global_cfg_warning(I40E_WARNING_QF_CTL);\n \n out:\n@@ -8894,6 +8940,18 @@ i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)\n \t\t (uint32_t)i40e_read_rx_ctl(hw, addr));\n }\n \n+void\n+i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)\n+{\n+\tuint32_t reg = i40e_read_rx_ctl(hw, addr);\n+\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] original: 0x%08x\", addr, reg);\n+\tif (reg != val)\n+\t\ti40e_write_global_rx_ctl(hw, addr, val);\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] after: 0x%08x\", addr,\n+\t\t (uint32_t)i40e_read_rx_ctl(hw, addr));\n+}\n+\n static void\n i40e_filter_input_set_init(struct i40e_pf *pf)\n {\n@@ -8925,24 +8983,28 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),\n \t\t\t\t (uint32_t)((inset_reg >>\n \t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n \t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n \t\t\t\t (uint32_t)((inset_reg >>\n \t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \n \t\tfor (i = 0; i < num; i++) {\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t mask_reg[i]);\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t\t mask_reg[i]);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t mask_reg[i]);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t\t mask_reg[i]);\n \t\t}\n \t\t/*clear unused mask registers of the pctype */\n \t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t\t 0);\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t\t 0);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t\t 0);\n+\t\t\ti40e_check_write_global_reg(hw,\n+\t\t\t\t\t\t I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t\t 0);\n \t\t}\n \t\tI40E_WRITE_FLUSH(hw);\n \n@@ -9009,20 +9071,20 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,\n \n \tinset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);\n \n-\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n-\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n-\ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n-\t\t\t (uint32_t)((inset_reg >>\n-\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n+\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n+\t\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n+\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n+\t\t\t\t (uint32_t)((inset_reg >>\n+\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n \n \tfor (i = 0; i < num; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t mask_reg[i]);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t mask_reg[i]);\n \t/*clear unused mask registers of the pctype */\n \tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n-\t\t\t\t 0);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n+\t\t\t\t\t 0);\n \ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n \tI40E_WRITE_FLUSH(hw);\n \n@@ -9091,12 +9153,12 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n \n \tfor (i = 0; i < num; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t mask_reg[i]);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t mask_reg[i]);\n \t/*clear unused mask registers of the pctype */\n \tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\t 0);\n+\t\ti40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\t\t 0);\n \ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n \tI40E_WRITE_FLUSH(hw);\n \n@@ -11644,6 +11706,10 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf)\n \t\t\t&filter_replace_buf);\n \tif (ret != I40E_SUCCESS)\n \t\treturn ret;\n+\tPMD_DRV_LOG(DEBUG, \"Global configuration modification: \"\n+\t\t \"cloud l1 type is changed from 0x%x to 0x%x\",\n+\t\t filter_replace.old_filter_type,\n+\t\t filter_replace.new_filter_type);\n \n \t/* Apply the second L2 cloud filter */\n \tmemset(&filter_replace, 0,\n@@ -11665,8 +11731,13 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf)\n \t\tI40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;\n \tret = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t&filter_replace_buf);\n-\tif (!ret)\n+\tif (!ret) {\n \t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n+\t\tPMD_DRV_LOG(DEBUG, \"Global configuration modification: \"\n+\t\t\t \"cloud filter type is changed from 0x%x to 0x%x\",\n+\t\t\t filter_replace.old_filter_type,\n+\t\t\t filter_replace.new_filter_type);\n+\t}\n \treturn ret;\n }\n \ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex d446f1a..12da379 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -78,6 +78,15 @@\n \t(((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \\\n \t((vf)->version_minor == 1))\n \n+#define I40E_WRITE_GLB_REG(hw, reg, value)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tI40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw),\t\t\\\n+\t\t\t\t\t\t (reg)), (value));\t\\\n+\t\tPMD_DRV_LOG(DEBUG, \"Global register 0x%08x is modified \" \\\n+\t\t\t \"with value 0x%08x\",\t\t\t\\\n+\t\t\t (reg), (value));\t\t\t\t\\\n+\t} while (0)\n+\n /* index flex payload per layer */\n enum i40e_flxpld_layer_idx {\n \tI40E_FLXPLD_L2_IDX = 0,\n@@ -1187,6 +1196,8 @@ int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,\n \t\t\t\t uint8_t nb_elem);\n uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);\n void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);\n+void i40e_check_write_global_reg(struct i40e_hw *hw,\n+\t\t\t\t uint32_t addr, uint32_t val);\n \n int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);\n void i40e_tm_conf_init(struct rte_eth_dev *dev);\n", "prefixes": [ "dpdk-dev", "v4", "2/4" ] }