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GET /api/patches/34880/?format=api
{ "id": 34880, "url": "http://patches.dpdk.org/api/patches/34880/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1517573152-92442-2-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1517573152-92442-2-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1517573152-92442-2-git-send-email-beilei.xing@intel.com", "date": "2018-02-02T12:05:49", "name": "[dpdk-dev,v4,1/4] net/i40e: add warnings when writing global registers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d2f759814b466efc18a572618a07d820f6868ecb", "submitter": { "id": 410, "url": "http://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 24, "url": "http://patches.dpdk.org/api/users/24/?format=api", "username": "helin_zhang", "first_name": "Helin", "last_name": "Zhang", "email": "helin.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1517573152-92442-2-git-send-email-beilei.xing@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/34880/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/34880/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 14EF8199B4;\n\tFri, 2 Feb 2018 13:05:18 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id 2A6C1A499\n\tfor <dev@dpdk.org>; Fri, 2 Feb 2018 13:05:15 +0100 (CET)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t02 Feb 2018 04:05:15 -0800", "from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52])\n\tby orsmga005.jf.intel.com with ESMTP; 02 Feb 2018 04:05:14 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.46,448,1511856000\"; d=\"scan'208\";a=\"198139810\"", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "dev@dpdk.org,\n\tjingjing.wu@intel.com", "Date": "Fri, 2 Feb 2018 20:05:49 +0800", "Message-Id": "<1517573152-92442-2-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1517573152-92442-1-git-send-email-beilei.xing@intel.com>", "References": "<1517485772-80595-1-git-send-email-beilei.xing@intel.com>\n\t<1517573152-92442-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 1/4] net/i40e: add warnings when writing\n\tglobal registers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add warnings when writing global registers.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n doc/guides/nics/i40e.rst | 12 ++++++++++++\n drivers/net/i40e/i40e_ethdev.c | 25 ++++++++++++++++++++++++\n drivers/net/i40e/i40e_ethdev.h | 43 ++++++++++++++++++++++++++++++++++++++++++\n drivers/net/i40e/i40e_fdir.c | 1 +\n drivers/net/i40e/i40e_flow.c | 1 +\n 5 files changed, 82 insertions(+)", "diff": "diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst\nindex 29601f1..166f447 100644\n--- a/doc/guides/nics/i40e.rst\n+++ b/doc/guides/nics/i40e.rst\n@@ -566,6 +566,18 @@ DCB function\n \n DCB works only when RSS is enabled.\n \n+Global configuration warning\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+I40E PMD will set some global registers to enable some function or set some\n+configure. Then when using different ports of the same NIC with Linux kernel\n+and DPDK, the port with Linux kernel will be impacted by the port with DPDK.\n+For example, register I40E_GL_SWT_L2TAGCTRL is used to control L2 tag, i40e\n+PMD uses I40E_GL_SWT_L2TAGCTRL to set vlan TPID. If setting TPID in port A\n+with DPDK, then the configuration will also impact port B in the NIC with\n+kernel driver, which don't want to use the TPID.\n+So PMD reports warning to clarify what is changed by writing global register.\n+\n High Performance of Small Packets on 40G NIC\n --------------------------------------------\n \ndiff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 277c1a8..b4a2857 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -680,6 +680,7 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)\n \t */\n \tI40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);\n \tI40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);\n+\ti40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);\n }\n \n #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808\n@@ -1133,6 +1134,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \t\t\t\t 0x00000028,\tNULL);\n \tif (ret)\n \t\tPMD_INIT_LOG(ERR, \"Failed to write L3 MAP register %d\", ret);\n+\ti40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);\n \n \t/* Need the special FW version to support floating VEB */\n \tconfig_floating_veb(dev);\n@@ -1413,6 +1415,7 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)\n \tI40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);\n \tI40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);\n \tI40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);\n+\ti40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);\n }\n \n static int\n@@ -3260,6 +3263,7 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,\n \t\t/* If NVM API < 1.7, keep the register setting */\n \t\tret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,\n \t\t\t\t\t\t tpid, qinq);\n+\ti40e_global_cfg_warning(I40E_WARNING_TPID);\n \n \treturn ret;\n }\n@@ -3502,6 +3506,7 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n \tI40E_WRITE_REG(hw, I40E_GLRPB_GLW,\n \t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n \t\t << I40E_KILOSHIFT);\n+\ti40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);\n \n \tI40E_WRITE_FLUSH(hw);\n \n@@ -7284,6 +7289,8 @@ i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)\n \n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n+\tif (!status)\n+\t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n \treturn status;\n }\n \n@@ -7338,6 +7345,8 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)\n \n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n+\tif (!status)\n+\t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n \treturn status;\n }\n \n@@ -7405,6 +7414,8 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf)\n \n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n+\tif (!status)\n+\t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n \treturn status;\n }\n \n@@ -7457,6 +7468,8 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)\n \n \tstatus = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t\t\t &filter_replace_buf);\n+\tif (!status)\n+\t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n \treturn status;\n }\n \n@@ -8006,6 +8019,7 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)\n \t\t\t\t\t\t reg, NULL);\n \t\tif (ret != 0)\n \t\t\treturn ret;\n+\t\ti40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);\n \t} else {\n \t\tret = 0;\n \t}\n@@ -8265,6 +8279,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\t\t\t\t\t\t I40E_GLQF_HSYM(j),\n \t\t\t\t\t\t\t reg);\n \t\t\t}\n+\t\t\ti40e_global_cfg_warning(I40E_WARNING_HSYM);\n \t\t}\n \t}\n \n@@ -8290,6 +8305,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n \t\tgoto out;\n \n \ti40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);\n+\ti40e_global_cfg_warning(I40E_WARNING_QF_CTL);\n \n out:\n \tI40E_WRITE_FLUSH(hw);\n@@ -8934,6 +8950,10 @@ i40e_filter_input_set_init(struct i40e_pf *pf)\n \t\tpf->hash_input_set[pctype] = input_set;\n \t\tpf->fdir.input_set[pctype] = input_set;\n \t}\n+\n+\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n+\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n+\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n }\n \n int\n@@ -8994,6 +9014,7 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,\n \ti40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n \t\t\t (uint32_t)((inset_reg >>\n \t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n+\ti40e_global_cfg_warning(I40E_WARNING_HASH_INSET);\n \n \tfor (i = 0; i < num; i++)\n \t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n@@ -9002,6 +9023,7 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,\n \tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n \t\ti40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),\n \t\t\t\t 0);\n+\ti40e_global_cfg_warning(I40E_WARNING_HASH_MSK);\n \tI40E_WRITE_FLUSH(hw);\n \n \tpf->hash_input_set[pctype] = input_set;\n@@ -9075,6 +9097,7 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,\n \tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n \t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n \t\t\t\t 0);\n+\ti40e_global_cfg_warning(I40E_WARNING_FD_MSK);\n \tI40E_WRITE_FLUSH(hw);\n \n \tpf->fdir.input_set[pctype] = input_set;\n@@ -11642,6 +11665,8 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf)\n \t\tI40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;\n \tret = i40e_aq_replace_cloud_filters(hw, &filter_replace,\n \t\t\t&filter_replace_buf);\n+\tif (!ret)\n+\t\ti40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);\n \treturn ret;\n }\n \ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 69ea6c1..d446f1a 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -1069,6 +1069,22 @@ struct i40e_valid_pattern {\n \tparse_filter_t parse_filter;\n };\n \n+enum I40E_WARNING_IDX {\n+\tI40E_WARNING_DIS_FLX_PLD,\n+\tI40E_WARNING_ENA_FLX_PLD,\n+\tI40E_WARNING_QINQ_PARSER,\n+\tI40E_WARNING_QINQ_CLOUD_FILTER,\n+\tI40E_WARNING_TPID,\n+\tI40E_WARNING_FLOW_CTL,\n+\tI40E_WARNING_GRE_KEY_LEN,\n+\tI40E_WARNING_QF_CTL,\n+\tI40E_WARNING_HASH_INSET,\n+\tI40E_WARNING_HSYM,\n+\tI40E_WARNING_HASH_MSK,\n+\tI40E_WARNING_FD_MSK,\n+\tI40E_WARNING_RPL_CLD_FILTER,\n+};\n+\n int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);\n int i40e_vsi_release(struct i40e_vsi *vsi);\n struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,\n@@ -1277,6 +1293,33 @@ i40e_calc_itr_interval(int16_t interval, bool is_pf)\n \treturn interval / 2;\n }\n \n+static inline void\n+i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)\n+{\n+\tconst char *warning;\n+\tstatic const char *const warning_list[] = {\n+\t\t[I40E_WARNING_DIS_FLX_PLD] = \"disable FDIR flexible payload\",\n+\t\t[I40E_WARNING_ENA_FLX_PLD] = \"enable FDIR flexible payload\",\n+\t\t[I40E_WARNING_QINQ_PARSER] = \"support QinQ parser\",\n+\t\t[I40E_WARNING_QINQ_CLOUD_FILTER] = \"support QinQ cloud filter\",\n+\t\t[I40E_WARNING_TPID] = \"support TPID configuration\",\n+\t\t[I40E_WARNING_FLOW_CTL] = \"configure water marker\",\n+\t\t[I40E_WARNING_GRE_KEY_LEN] = \"support GRE key length setting\",\n+\t\t[I40E_WARNING_QF_CTL] = \"support hash function setting\",\n+\t\t[I40E_WARNING_HASH_INSET] = \"configure hash input set\",\n+\t\t[I40E_WARNING_HSYM] = \"set symmetric hash\",\n+\t\t[I40E_WARNING_HASH_MSK] = \"configure hash mask\",\n+\t\t[I40E_WARNING_FD_MSK] = \"configure fdir mask\",\n+\t\t[I40E_WARNING_RPL_CLD_FILTER] = \"replace cloud filter\",\n+\t};\n+\n+\twarning = warning_list[idx];\n+\n+\tRTE_LOG(WARNING, PMD,\n+\t\t\"Global register is changed during %s\\n\",\n+\t\twarning);\n+}\n+\n #define I40E_VALID_FLOW(flow_type) \\\n \t((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \\\n \t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \\\ndiff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c\nindex c392dc4..97c6d4f 100644\n--- a/drivers/net/i40e/i40e_fdir.c\n+++ b/drivers/net/i40e/i40e_fdir.c\n@@ -526,6 +526,7 @@ i40e_set_flx_pld_cfg(struct i40e_pf *pf,\n \t\t\t (num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |\n \t\t\t (layer_idx * I40E_MAX_FLXPLD_FIED);\n \t\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);\n \t}\n \n \tfor (i = 0; i < num; i++) {\ndiff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c\nindex 34661c8..30b0db8 100644\n--- a/drivers/net/i40e/i40e_flow.c\n+++ b/drivers/net/i40e/i40e_flow.c\n@@ -2260,6 +2260,7 @@ i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,\n \t\t\t (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |\n \t\t\t (layer_idx * I40E_MAX_FLXPLD_FIED);\n \t\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);\n+\t\ti40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);\n \t}\n \n \t/* Set flex pit */\n", "prefixes": [ "dpdk-dev", "v4", "1/4" ] }