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GET /api/patches/31782/?format=api
{ "id": 31782, "url": "http://patches.dpdk.org/api/patches/31782/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20171130081329.5566-1-somnath.kotur@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20171130081329.5566-1-somnath.kotur@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20171130081329.5566-1-somnath.kotur@broadcom.com", "date": "2017-11-30T08:13:29", "name": "[dpdk-dev] net/bnxt: Support time_sync related APIs", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "5924ab0c7570ac9cebd695bfa2c64437a66ffa80", "submitter": { "id": 908, "url": "http://patches.dpdk.org/api/people/908/?format=api", "name": "Somnath Kotur", "email": "somnath.kotur@broadcom.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20171130081329.5566-1-somnath.kotur@broadcom.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/31782/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/31782/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C12C728EE;\n\tThu, 30 Nov 2017 09:23:55 +0100 (CET)", "from relay.smtp.broadcom.com (lpdvsmtp02.broadcom.com\n\t[192.19.232.149]) by dpdk.org (Postfix) with ESMTP id 23CA114E8\n\tfor <dev@dpdk.org>; Thu, 30 Nov 2017 09:23:54 +0100 (CET)", "from dhcp-10-192-204-91.dhcp.broadcom.net\n\t(bgccx-dev-host-lnx35.bec.broadcom.net [10.123.153.55])\n\tby relay.smtp.broadcom.com (Postfix) with ESMTP id 4E0BC1A0018\n\tfor <dev@dpdk.org>; Thu, 30 Nov 2017 00:23:49 -0800 (PST)" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 4E0BC1A0018", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n\ts=dkimrelay; t=1512030230;\n\tbh=iagxiMov3KjEyF4BIGMu3sWGvBR39mGVZaxEDNCBu1U=;\n\th=From:To:Subject:Date:From;\n\tb=Qblxyiaxncmnzk/SNG9cktPmOwGqnWOS1yn0NEAeNgRhewuT7+bnXZR04OzlEcA3z\n\tyG7dvtU0sCH/JHj02XV1+rICjsC4yoXYIeQwcKLiK36IM3n8DyawdJSzRbOd2aXcFG\n\todWkSpNXM735vn76j8gDJ8xy/WdQZhE5aSZVahw4=", "From": "Somnath Kotur <somnath.kotur@broadcom.com>", "To": "dev@dpdk.org", "Date": "Thu, 30 Nov 2017 13:43:29 +0530", "Message-Id": "<20171130081329.5566-1-somnath.kotur@broadcom.com>", "X-Mailer": "git-send-email 2.10.1.613.g2cc2e70", "Subject": "[dpdk-dev] [PATCH] net/bnxt: Support time_sync related APIs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Implemented the 'time_sync' related APIs for supporting PTP.\nDefined new FW structs, opcodes and cmds for the same.\n\nSigned-off-by: Somnath Kotur <somnath.kotur@broadcom.com>\n---\n drivers/net/bnxt/bnxt.h | 49 +++++++\n drivers/net/bnxt/bnxt_ethdev.c | 245 ++++++++++++++++++++++++++++++++-\n drivers/net/bnxt/bnxt_hwrm.c | 94 ++++++++++++-\n drivers/net/bnxt/bnxt_hwrm.h | 1 +\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 222 +++++++++++++++++++++++++++++\n 5 files changed, 609 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex 8ab1c7f..03ec785 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -44,6 +44,7 @@\n #include <rte_memory.h>\n #include <rte_lcore.h>\n #include <rte_spinlock.h>\n+#include <rte_time.h>\n \n #include \"bnxt_cpr.h\"\n \n@@ -180,6 +181,52 @@ struct rte_flow {\n \tstruct bnxt_vnic_info\t*vnic;\n };\n \n+struct bnxt_ptp_cfg {\n+#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400\n+#define BNXT_GRCPF_REG_SYNC_TIME 0x480\n+\tstruct rte_timecounter tc;\n+\tstruct rte_timecounter tx_tstamp_tc;\n+\tstruct rte_timecounter rx_tstamp_tc;\n+\tstruct bnxt\t\t*bp;\n+#define BNXT_MAX_TX_TS\t1\n+\tuint16_t\t\t\trxctl;\n+#define BNXT_PTP_MSG_SYNC\t\t\t(1 << 0)\n+#define BNXT_PTP_MSG_DELAY_REQ\t\t\t(1 << 1)\n+#define BNXT_PTP_MSG_PDELAY_REQ\t\t\t(1 << 2)\n+#define BNXT_PTP_MSG_PDELAY_RESP\t\t(1 << 3)\n+#define BNXT_PTP_MSG_FOLLOW_UP\t\t\t(1 << 8)\n+#define BNXT_PTP_MSG_DELAY_RESP\t\t\t(1 << 9)\n+#define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP\t(1 << 10)\n+#define BNXT_PTP_MSG_ANNOUNCE\t\t\t(1 << 11)\n+#define BNXT_PTP_MSG_SIGNALING\t\t\t(1 << 12)\n+#define BNXT_PTP_MSG_MANAGEMENT\t\t\t(1 << 13)\n+#define BNXT_PTP_MSG_EVENTS\t\t(BNXT_PTP_MSG_SYNC |\t\t\\\n+\t\t\t\t\t BNXT_PTP_MSG_DELAY_REQ |\t\\\n+\t\t\t\t\t BNXT_PTP_MSG_PDELAY_REQ |\t\\\n+\t\t\t\t\t BNXT_PTP_MSG_PDELAY_RESP)\n+\tuint8_t\t\t\ttx_tstamp_en:1;\n+\tint\t\t\trx_filter;\n+\n+#define BNXT_PTP_RX_TS_L\t0\n+#define BNXT_PTP_RX_TS_H\t1\n+#define BNXT_PTP_RX_SEQ\t\t2\n+#define BNXT_PTP_RX_FIFO\t3\n+#define BNXT_PTP_RX_FIFO_PENDING 0x1\n+#define BNXT_PTP_RX_FIFO_ADV\t4\n+#define BNXT_PTP_RX_REGS\t5\n+\n+#define BNXT_PTP_TX_TS_L\t0\n+#define BNXT_PTP_TX_TS_H\t1\n+#define BNXT_PTP_TX_SEQ\t\t2\n+#define BNXT_PTP_TX_FIFO\t3\n+#define BNXT_PTP_TX_FIFO_EMPTY\t 0x2\n+#define BNXT_PTP_TX_REGS\t4\n+\tuint32_t\t\t\trx_regs[BNXT_PTP_RX_REGS];\n+\tuint32_t\t\t\trx_mapped_regs[BNXT_PTP_RX_REGS];\n+\tuint32_t\t\t\ttx_regs[BNXT_PTP_TX_REGS];\n+\tuint32_t\t\t\ttx_mapped_regs[BNXT_PTP_TX_REGS];\n+};\n+\n #define BNXT_HWRM_SHORT_REQ_LEN\t\tsizeof(struct hwrm_short_input)\n struct bnxt {\n \tvoid\t\t\t\t*bar0;\n@@ -195,6 +242,7 @@ struct bnxt {\n #define BNXT_FLAG_JUMBO\t\t(1 << 3)\n #define BNXT_FLAG_SHORT_CMD\t(1 << 4)\n #define BNXT_FLAG_UPDATE_HASH\t(1 << 5)\n+#define BNXT_FLAG_PTP_SUPPORTED\t(1 << 6)\n #define BNXT_PF(bp)\t\t(!((bp)->flags & BNXT_FLAG_VF))\n #define BNXT_VF(bp)\t\t((bp)->flags & BNXT_FLAG_VF)\n #define BNXT_NPAR_ENABLED(bp)\t((bp)->port_partition_type)\n@@ -272,6 +320,7 @@ struct bnxt {\n \n \tstruct bnxt_led_info\tleds[BNXT_MAX_LED];\n \tuint8_t\t\t\tnum_leds;\n+\tstruct bnxt_ptp_cfg *ptp_cfg;\n };\n \n int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);\ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex 3b6813c..38854f8 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -869,7 +869,7 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,\n \t\t\t\"(%d)\\n\", reta_size, HW_HASH_INDEX_SIZE);\n \t\treturn -EINVAL;\n \t}\n-\t/* EW - need to revisit here copying from u64 to u16 */\n+\t/* EW - need to revisit here copying from uint64_t to uint16_t */\n \tmemcpy(reta_conf, vnic->rss_table, reta_size);\n \n \tif (rte_intr_allow_others(intr_handle)) {\n@@ -2536,7 +2536,243 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)\n \treturn NULL;\n }\n \n+static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,\n+\t\t\t int reg_win)\n+{\n+\tuint32_t reg_base = *reg_arr & 0xfffff000;\n+\tuint32_t win_off;\n+\tint i;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\tif ((reg_arr[i] & 0xfffff000) != reg_base)\n+\t\t\treturn -ERANGE;\n+\t}\n+\twin_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;\n+\trte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));\n+\treturn 0;\n+}\n+\n+static int bnxt_map_ptp_regs(struct bnxt *bp)\n+{\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\tuint32_t *reg_arr;\n+\tint rc, i;\n+\n+\treg_arr = ptp->rx_regs;\n+\trc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treg_arr = ptp->tx_regs;\n+\trc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tfor (i = 0; i < BNXT_PTP_RX_REGS; i++)\n+\t\tptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);\n+\n+\tfor (i = 0; i < BNXT_PTP_TX_REGS; i++)\n+\t\tptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);\n+\n+\treturn 0;\n+}\n+\n+static void bnxt_unmap_ptp_regs(struct bnxt *bp)\n+{\n+\trte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +\n+\t\t\t BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));\n+\trte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +\n+\t\t\t BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));\n+}\n+\n+static uint64_t bnxt_cc_read(struct bnxt *bp)\n+{\n+\tuint64_t ns;\n+\n+\tns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +\n+\t\t\t BNXT_GRCPF_REG_SYNC_TIME));\n+\tns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +\n+\t\t\t\t\t BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;\n+\treturn ns;\n+}\n+\n+static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)\n+{\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\tuint32_t fifo;\n+\n+\tfifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +\n+\t\t\t\tptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));\n+\tif (fifo & BNXT_PTP_TX_FIFO_EMPTY)\n+\t\treturn -EAGAIN;\n+\n+\tfifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +\n+\t\t\t\tptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));\n+\t*ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +\n+\t\t\t\tptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));\n+\t*ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +\n+\t\t\t\tptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;\n+\n+\treturn 0;\n+}\n+\n+static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)\n+{\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\tstruct bnxt_pf_info *pf = &bp->pf;\n+\tuint16_t port_id;\n+\tuint32_t fifo;\n+\n+\tif (!ptp)\n+\t\treturn -ENODEV;\n+\n+\tfifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +\n+\t\t\t\tptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));\n+\tif (!(fifo & BNXT_PTP_RX_FIFO_PENDING))\n+\t\treturn -EAGAIN;\n+\n+\tport_id = pf->port_id;\n+\trte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +\n+\t ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));\n+\n+\tfifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +\n+\t\t\t\t ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));\n+\tif (fifo & BNXT_PTP_RX_FIFO_PENDING) {\n+/*\t\tbnxt_clr_rx_ts(bp);\t TBD */\n+\t\treturn -EBUSY;\n+\t}\n+\n+\t*ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +\n+\t\t\t\tptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));\n+\t*ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +\n+\t\t\t\tptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;\n+\n+\treturn 0;\n+}\n+\n+static int\n+bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)\n+{\n+\tuint64_t ns;\n+\tstruct bnxt *bp = (struct bnxt *)dev->data->dev_private;\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\n+\tif (!ptp)\n+\t\treturn 0;\n+\n+\tns = rte_timespec_to_ns(ts);\n+\t/* Set the timecounters to a new value. */\n+\tptp->tc.nsec = ns;\n+\n+\treturn 0;\n+}\n+\n+static int\n+bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)\n+{\n+\tuint64_t ns, systime_cycles;\n+\tstruct bnxt *bp = (struct bnxt *)dev->data->dev_private;\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\n+\tif (!ptp)\n+\t\treturn 0;\n+\n+\tsystime_cycles = bnxt_cc_read(bp);\n+\tns = rte_timecounter_update(&ptp->tc, systime_cycles);\n+\t*ts = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+static int\n+bnxt_timesync_enable(struct rte_eth_dev *dev)\n+{\n+\tstruct bnxt *bp = (struct bnxt *)dev->data->dev_private;\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\n+\tif (!ptp)\n+\t\treturn 0;\n+\n+\tptp->rx_filter = 1;\n+\tptp->tx_tstamp_en = 1;\n+\tptp->rxctl = BNXT_PTP_MSG_EVENTS;\n+\n+\tif (!bnxt_hwrm_ptp_cfg(bp))\n+\t\tbnxt_map_ptp_regs(bp);\n \n+\treturn 0;\n+}\n+\n+static int\n+bnxt_timesync_disable(struct rte_eth_dev *dev)\n+{\n+\tstruct bnxt *bp = (struct bnxt *)dev->data->dev_private;\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\n+\tif (!ptp)\n+\t\treturn 0;\n+\n+\tptp->rx_filter = 0;\n+\tptp->tx_tstamp_en = 0;\n+\tptp->rxctl = 0;\n+\n+\tbnxt_hwrm_ptp_cfg(bp);\n+\n+\tbnxt_unmap_ptp_regs(bp);\n+\n+\treturn 0;\n+}\n+\n+static int\n+bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t\t struct timespec *timestamp,\n+\t\t\t\t uint32_t flags __rte_unused)\n+{\n+\tstruct bnxt *bp = (struct bnxt *)dev->data->dev_private;\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\tuint64_t rx_tstamp_cycles = 0;\n+\tuint64_t ns;\n+\n+\tif (!ptp)\n+\t\treturn 0;\n+\n+\tbnxt_get_rx_ts(bp, &rx_tstamp_cycles);\n+\tns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);\n+\t*timestamp = rte_ns_to_timespec(ns);\n+\treturn 0;\n+}\n+\n+static int\n+bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t\t struct timespec *timestamp)\n+{\n+\tstruct bnxt *bp = (struct bnxt *)dev->data->dev_private;\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\tuint64_t tx_tstamp_cycles = 0;\n+\tuint64_t ns;\n+\n+\tif (!ptp)\n+\t\treturn 0;\n+\n+\tbnxt_get_tx_ts(bp, &tx_tstamp_cycles);\n+\tns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);\n+\t*timestamp = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n+static int\n+bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)\n+{\n+\tstruct bnxt *bp = (struct bnxt *)dev->data->dev_private;\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\n+\tif (!ptp)\n+\t\treturn 0;\n+\n+\tptp->tc.nsec += delta;\n+\n+\treturn 0;\n+}\n \n static int\n bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)\n@@ -2732,6 +2968,13 @@ static bool bnxt_dir_type_is_executable(uint16_t dir_type)\n \t.get_eeprom_length = bnxt_get_eeprom_length_op,\n \t.get_eeprom = bnxt_get_eeprom_op,\n \t.set_eeprom = bnxt_set_eeprom_op,\n+\t.timesync_enable = bnxt_timesync_enable,\n+\t.timesync_disable = bnxt_timesync_disable,\n+\t.timesync_read_time = bnxt_timesync_read_time,\n+\t.timesync_write_time = bnxt_timesync_write_time,\n+\t.timesync_adjust_time = bnxt_timesync_adjust_time,\n+\t.timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,\n+\t.timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,\n };\n \n static bool bnxt_vf_pciid(uint16_t id)\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex d2c800d..2f1d88f 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -427,12 +427,95 @@ int bnxt_hwrm_set_l2_filter(struct bnxt *bp,\n \treturn rc;\n }\n \n+int bnxt_hwrm_ptp_cfg(struct bnxt *bp)\n+{\n+\tstruct hwrm_port_mac_cfg_input req = {.req_type = 0};\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\tuint32_t flags = 0;\n+\tint rc;\n+\n+\tif (!ptp)\n+\t\treturn 0;\n+\n+\tHWRM_PREP(req, PORT_MAC_CFG);\n+\n+\tif (ptp->rx_filter)\n+\t\tflags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;\n+\telse\n+\t\tflags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;\n+\tif (ptp->tx_tstamp_en)\n+\t\tflags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;\n+\telse\n+\t\tflags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;\n+\treq.flags = rte_cpu_to_le_32(flags);\n+\treq.enables =\n+\trte_cpu_to_le_32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);\n+\treq.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);\n+\n+\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req));\n+\tHWRM_UNLOCK();\n+\n+\treturn rc;\n+}\n+\n+static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)\n+{\n+\tint rc = 0;\n+\tstruct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};\n+\tstruct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;\n+\tstruct bnxt_ptp_cfg *ptp = bp->ptp_cfg;\n+\n+/*\tif (bp->hwrm_spec_code < 0x10801 || ptp) TBD */\n+\tif (ptp)\n+\t\treturn 0;\n+\n+\tHWRM_PREP(req, PORT_MAC_PTP_QCFG);\n+\n+\treq.port_id = rte_cpu_to_le_16(bp->pf.port_id);\n+\n+\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req));\n+\n+\tHWRM_CHECK_RESULT();\n+\n+\tif (!(resp->flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS))\n+\t\treturn 0;\n+\n+\tptp = rte_zmalloc(\"ptp_cfg\", sizeof(*ptp), 0);\n+\tif (!ptp)\n+\t\treturn -ENOMEM;\n+\n+\tptp->rx_regs[BNXT_PTP_RX_TS_L] =\n+\t\trte_le_to_cpu_32(resp->rx_ts_reg_off_lower);\n+\tptp->rx_regs[BNXT_PTP_RX_TS_H] =\n+\t\trte_le_to_cpu_32(resp->rx_ts_reg_off_upper);\n+\tptp->rx_regs[BNXT_PTP_RX_SEQ] =\n+\t\trte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);\n+\tptp->rx_regs[BNXT_PTP_RX_FIFO] =\n+\t\trte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);\n+\tptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =\n+\t\trte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);\n+\tptp->tx_regs[BNXT_PTP_TX_TS_L] =\n+\t\trte_le_to_cpu_32(resp->tx_ts_reg_off_lower);\n+\tptp->tx_regs[BNXT_PTP_TX_TS_H] =\n+\t\trte_le_to_cpu_32(resp->tx_ts_reg_off_upper);\n+\tptp->tx_regs[BNXT_PTP_TX_SEQ] =\n+\t\trte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);\n+\tptp->tx_regs[BNXT_PTP_TX_FIFO] =\n+\t\trte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);\n+\n+\tptp->bp = bp;\n+\tbp->ptp_cfg = ptp;\n+\n+\treturn 0;\n+}\n+\n int bnxt_hwrm_func_qcaps(struct bnxt *bp)\n {\n \tint rc = 0;\n \tstruct hwrm_func_qcaps_input req = {.req_type = 0 };\n \tstruct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;\n \tuint16_t new_max_vfs;\n+\tuint32_t flags;\n \tint i;\n \n \tHWRM_PREP(req, FUNC_QCAPS);\n@@ -444,6 +527,7 @@ int bnxt_hwrm_func_qcaps(struct bnxt *bp)\n \tHWRM_CHECK_RESULT();\n \n \tbp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);\n+\tflags = rte_le_to_cpu_32(resp->flags);\n \tif (BNXT_PF(bp)) {\n \t\tbp->pf.port_id = resp->port_id;\n \t\tbp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);\n@@ -500,8 +584,16 @@ int bnxt_hwrm_func_qcaps(struct bnxt *bp)\n \t\tbp->max_vnics = 1;\n \t}\n \tbp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);\n-\tif (BNXT_PF(bp))\n+\tif (BNXT_PF(bp)) {\n \t\tbp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);\n+\t\tif (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {\n+\t\t\tbp->flags |= BNXT_FLAG_PTP_SUPPORTED;\n+\t\t\tRTE_LOG(INFO, PMD, \"PTP SUPPORTED\");\n+\t\t\tHWRM_UNLOCK();\n+\t\t\tbnxt_hwrm_ptp_qcfg(bp);\n+\t\t}\n+\t}\n+\n \tHWRM_UNLOCK();\n \n \treturn rc;\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h\nindex 85083e6..46f6f32 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.h\n+++ b/drivers/net/bnxt/bnxt_hwrm.h\n@@ -175,4 +175,5 @@ int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,\n \t\t\t uint16_t dir_ordinal, uint16_t dir_ext,\n \t\t\t uint16_t dir_attr, const uint8_t *data,\n \t\t\t size_t data_len);\n+int bnxt_hwrm_ptp_cfg(struct bnxt *bp);\n #endif\ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex c16edba..93a44d3 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -85,6 +85,7 @@\n #define HWRM_PORT_CLR_STATS\t\t(UINT32_C(0x25))\n #define HWRM_PORT_PHY_QCFG\t\t(UINT32_C(0x27))\n #define HWRM_PORT_MAC_QCFG\t\t(UINT32_C(0x28))\n+#define HWRM_PORT_MAC_PTP_QCFG (UINT32_C(0x29))\n #define HWRM_PORT_PHY_QCAPS\t\t(UINT32_C(0x2a))\n #define HWRM_PORT_LED_CFG\t\t(UINT32_C(0x2d))\n #define HWRM_PORT_LED_QCFG\t\t(UINT32_C(0x2e))\n@@ -7121,6 +7122,227 @@ struct hwrm_queue_qportcfg_output {\n \t */\n } __attribute__((packed));\n \n+/*********************\n+ * hwrm_port_mac_cfg *\n+ *********************/\n+\n+\n+/* hwrm_port_mac_cfg_input (size:320b/40B) */\n+struct hwrm_port_mac_cfg_input {\n+\tuint16_t\treq_type;\n+\tuint16_t\tcmpl_ring;\n+\tuint16_t\tseq_id;\n+\tuint16_t\ttarget_id;\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t#define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL\n+\t#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL\n+\tuint32_t\tenables;\n+\t#define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL\n+\t#define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL\n+\t#define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL\n+\t#define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL\n+\t#define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL\n+\t#define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL\n+\t#define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL\n+\t#define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL\n+\tuint16_t\tport_id;\n+\tuint8_t\t\tipg;\n+\tuint8_t\t\tlpbk;\n+\t#define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL\n+\t#define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL\n+\t#define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL\n+\t#define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE\n+\tuint8_t\t\tvlan_pri2cos_map_pri;\n+\tuint8_t\t\treserved1;\n+\tuint8_t\t\ttunnel_pri2cos_map_pri;\n+\tuint8_t\t\tdscp2pri_map_pri;\n+\tuint16_t\trx_ts_capture_ptp_msg_type;\n+\tuint16_t\ttx_ts_capture_ptp_msg_type;\n+\tuint8_t\t\tcos_field_cfg;\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \\\n+\t\t(0x0UL << 1)\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \\\n+\t\t(0x1UL << 1)\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \\\n+\t\t(0x2UL << 1)\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \\\n+\t\t(0x3UL << 1)\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \\\n+\t\tPORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \\\n+\t\t(0x0UL << 3)\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \\\n+\t\t(0x1UL << 3)\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \\\n+\t\t(0x2UL << 3)\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \\\n+\t\t(0x3UL << 3)\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \\\n+\t\tPORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL\n+\t#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5\n+\tuint8_t\t\tunused_0[3];\n+};\n+\n+\n+/* hwrm_port_mac_cfg_output (size:128b/16B) */\n+struct hwrm_port_mac_cfg_output {\n+\tuint16_t\terror_code;\n+\tuint16_t\treq_type;\n+\tuint16_t\tseq_id;\n+\tuint16_t\tresp_len;\n+\tuint16_t\tmru;\n+\tuint16_t\tmtu;\n+\tuint8_t\t\tipg;\n+\tuint8_t\t\tlpbk;\n+\t#define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL\n+\t#define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL\n+\t#define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL\n+\t#define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE\n+\tuint8_t\t\tunused_0;\n+\tuint8_t\t\tvalid;\n+};\n+\n+\n+/**********************\n+ * hwrm_port_mac_qcfg *\n+ **********************/\n+\n+\n+/* hwrm_port_mac_qcfg_input (size:192b/24B) */\n+struct hwrm_port_mac_qcfg_input {\n+\tuint16_t\treq_type;\n+\tuint16_t\tcmpl_ring;\n+\tuint16_t\tseq_id;\n+\tuint16_t\ttarget_id;\n+\tuint64_t\tresp_addr;\n+\tuint16_t\tport_id;\n+\tuint8_t\t\tunused_0[6];\n+};\n+\n+\n+/* hwrm_port_mac_qcfg_output (size:192b/24B) */\n+struct hwrm_port_mac_qcfg_output {\n+\tuint16_t\terror_code;\n+\tuint16_t\treq_type;\n+\tuint16_t\tseq_id;\n+\tuint16_t\tresp_len;\n+\tuint16_t\tmru;\n+\tuint16_t\tmtu;\n+\tuint8_t\t\tipg;\n+\tuint8_t\t\tlpbk;\n+\t#define PORT_MAC_QCFG_RESP_LPBK_NONE 0x0UL\n+\t#define PORT_MAC_QCFG_RESP_LPBK_LOCAL 0x1UL\n+\t#define PORT_MAC_QCFG_RESP_LPBK_REMOTE 0x2UL\n+\t#define PORT_MAC_QCFG_RESP_LPBK_LAST PORT_MAC_QCFG_RESP_LPBK_REMOTE\n+\tuint8_t\t\tvlan_pri2cos_map_pri;\n+\tuint8_t\t\tflags;\n+\t#define PORT_MAC_QCFG_RESP_FLAGS_VLAN_PRI2COS_ENABLE 0x1UL\n+\t#define PORT_MAC_QCFG_RESP_FLAGS_TUNNEL_PRI2COS_ENABLE 0x2UL\n+\t#define PORT_MAC_QCFG_RESP_FLAGS_IP_DSCP2COS_ENABLE 0x4UL\n+\t#define PORT_MAC_QCFG_RESP_FLAGS_OOB_WOL_ENABLE 0x8UL\n+\t#define PORT_MAC_QCFG_RESP_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL\n+\t#define PORT_MAC_QCFG_RESP_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x20UL\n+\tuint8_t\t\ttunnel_pri2cos_map_pri;\n+\tuint8_t\t\tdscp2pri_map_pri;\n+\tuint16_t\trx_ts_capture_ptp_msg_type;\n+\tuint16_t\ttx_ts_capture_ptp_msg_type;\n+\tuint8_t\t\tcos_field_cfg;\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_RSVD 0x1UL\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \\\n+\t\t(0x0UL << 1)\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \\\n+\t\t(0x1UL << 1)\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \\\n+\t\t(0x2UL << 1)\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \\\n+\t\t(0x3UL << 1)\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \\\n+\t\tPORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK\t0x18UL\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \\\n+\t\t(0x0UL << 3)\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \\\n+\t\t(0x1UL << 3)\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \\\n+\t\t(0x2UL << 3)\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \\\n+\t\t(0x3UL << 3)\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \\\n+\t\tPORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_DEFAULT_COS_MASK\t0xe0UL\n+\t#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_DEFAULT_COS_SFT 5\n+\tuint8_t\t\tvalid;\n+};\n+\n+\n+/**************************\n+ * hwrm_port_mac_ptp_qcfg *\n+ **************************/\n+\n+\n+/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */\n+struct hwrm_port_mac_ptp_qcfg_input {\n+\tuint16_t\treq_type;\n+\tuint16_t\tcmpl_ring;\n+\tuint16_t\tseq_id;\n+\tuint16_t\ttarget_id;\n+\tuint64_t\tresp_addr;\n+\tuint16_t\tport_id;\n+\tuint8_t\t\tunused_0[6];\n+};\n+\n+\n+/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */\n+struct hwrm_port_mac_ptp_qcfg_output {\n+\tuint16_t\terror_code;\n+\tuint16_t\treq_type;\n+\tuint16_t\tseq_id;\n+\tuint16_t\tresp_len;\n+\tuint8_t\t\tflags;\n+\t#define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL\n+\t#define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL\n+\tuint8_t\t\tunused_0[3];\n+\tuint32_t\trx_ts_reg_off_lower;\n+\tuint32_t\trx_ts_reg_off_upper;\n+\tuint32_t\trx_ts_reg_off_seq_id;\n+\tuint32_t\trx_ts_reg_off_src_id_0;\n+\tuint32_t\trx_ts_reg_off_src_id_1;\n+\tuint32_t\trx_ts_reg_off_src_id_2;\n+\tuint32_t\trx_ts_reg_off_domain_id;\n+\tuint32_t\trx_ts_reg_off_fifo;\n+\tuint32_t\trx_ts_reg_off_fifo_adv;\n+\tuint32_t\trx_ts_reg_off_granularity;\n+\tuint32_t\ttx_ts_reg_off_lower;\n+\tuint32_t\ttx_ts_reg_off_upper;\n+\tuint32_t\ttx_ts_reg_off_seq_id;\n+\tuint32_t\ttx_ts_reg_off_fifo;\n+\tuint32_t\ttx_ts_reg_off_granularity;\n+\tuint8_t\t\tunused_1[7];\n+\tuint8_t\t\tvalid;\n+};\n+\n+\n /* hwrm_vnic_alloc */\n /*\n * Description: This VNIC is a resource in the RX side of the chip that is used\n", "prefixes": [ "dpdk-dev" ] }