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GET /api/patches/30729/?format=api
{ "id": 30729, "url": "http://patches.dpdk.org/api/patches/30729/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1508776177-11264-1-git-send-email-pbhagavatula@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1508776177-11264-1-git-send-email-pbhagavatula@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1508776177-11264-1-git-send-email-pbhagavatula@caviumnetworks.com", "date": "2017-10-23T16:29:35", "name": "[dpdk-dev,v2,1/3] evendev: fix inconsistency in event queue config", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "17768ef1756dcfdb221baa1e1a3a8652ce96d4d4", "submitter": { "id": 768, "url": "http://patches.dpdk.org/api/people/768/?format=api", "name": "Pavan Nikhilesh", "email": "pbhagavatula@caviumnetworks.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1508776177-11264-1-git-send-email-pbhagavatula@caviumnetworks.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/30729/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/30729/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9FB331B655;\n\tMon, 23 Oct 2017 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)\n\tsmtp.mailfrom=Pavan.Bhagavatula@cavium.com; ", "From": "Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>", "To": "harry.van.haaren@intel.com, hemant.agrawal@nxp.com,\n\tjerin.jacob@caviumnetworks.com", "Cc": "dev@dpdk.org,\n\tPavan Bhagavatula <pbhagavatula@caviumnetworks.com>", "Date": "Mon, 23 Oct 2017 21:59:35 +0530", "Message-Id": "<1508776177-11264-1-git-send-email-pbhagavatula@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1507814147-8223-1-git-send-email-pbhagavatula@caviumnetworks.com>", "References": "<1507814147-8223-1-git-send-email-pbhagavatula@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[103.16.71.47]", "X-ClientProxiedBy": "HK2PR04CA0047.apcprd04.prod.outlook.com (10.170.154.15) To\n\tMWHPR07MB3472.namprd07.prod.outlook.com (10.164.192.23)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b6b6e674-514a-4748-2b58-08d51a334c32", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(22001)(4534020)(4602075)(4627075)(201703031133081)(201702281549075)(2017052603199);\n\tSRVR:MWHPR07MB3472; ", "X-Microsoft-Exchange-Diagnostics": [ "1; MWHPR07MB3472;\n\t3:w2fev4sVtCgzYN4uonyQrykA4/dCqnU6bhJ6QGbY/70CfW6KHdJ7qnB6yn4eVyE/RztU1mbHFnI6Nq0RZ/SFwXOgcPnpw6PCDEqnOkYiuIqtyj9ma5MIrfp5TorW/GzTUBTjt7jNkx4rmuFaGEBWcwwbgjUxFEf1jHkD3w9VeooFO4bCpWR7weYYs5TIbwBkrTn3z4vLV0B8q/fCd2HhmUgyp3pUpqc0nnFpvSh505fCYLB8x+PcFwdhmupjWwAL;\n\t25:3KvaG5rj2A3WJNuBANacpzDZNbhTniZqc4FeSmw0y4ioOxi/STQcJNfXV4WrOeuATEqrmB9xK5UuATdd5tfDYYh3+3GniMLLknDfnk63QjK/70QaBe4z732hdgwfojBKE4UaBBY8669tUN3O2ZNV2fCUINZDKTTrs0ysmUa9gfMHgL3DwXKbzFE6bcw18pQQw5xBsmSXU1ZyzXnLJwZhcY70pWb1OOSW6VCXDdv8DJOI7iyiUigm2kOzfyAXR7a9WVI1PMcbH6FRapoq3glAt/VaL0x3yX1cKQovGLr/qDSGwDLVwZoAHG+R7rpm/ChB8T2zO2M1WApeQQCZBL+hYA==;\n\t31:JHtOzO3ddqWOjmpiWgR9q6Y5kDuzXDXAP9rfdd2Z3K2MKJShqs+pxSEflERStJ5GldiXoxqDfB9D3tF8fTsL4+FtfYBu/nJwM/3jU6MOE8qfGuOg0i4XwO2T36ByuNPztYi3fUwHYz3G4wr/T2Bjwt/WJxPjPk6klc2WELOwzt6SEhdTB3l32wc2q2SvidEaNY4LC5TPY+8snj728892Rdzw66znqBzzGBJqdiXHkos=", "1; MWHPR07MB3472;\n\t20:X6ps995KWhHopEsyVMDRiTvfrLa9+vQ6+Yv6WuyTpzi/C5Bfqm95R+mP/IBmlVHi2Xu9KPrtJz1Qjr5LJXBmgbYqwJwcSSBnDJ9+N37FSIrtdqbI1yAGie03ByXHhkgcxP1zP3SJXbNyrJPPcrfHKZqRmbmJfm28M9J8bWPlQRfc//g8YSBJVEwbNKSwerqreP04SNj9yEfi5mTbwDSrB1O8y2zGqIw5Su/zhhBN2Cq3stAUd5eu5IRdwDOP8iuA3zxuSvChxintlIKkfqHnnKN2LcuTG0UxwD/JEzyWVEwVBhw+QyODYyeeFzVKJLtgqOnrN6hkfkvEj1iIMov7t+SVpfPPhAHpRdwkCCWpkNeoHWb+6RjJpQxqmWkO63X0DIw/IGncFnynw2ekjK37p9bAlir0NRY8JVpYwUtk3tW7pNr1Jg1696tdzzuG38SiAgeYIA/MYmQlOQtBVK4dfNWCnyWdhIlYii/kWb8FQ9d4Spid/WjSW60Q9/7ENPWOFalcths7+Mw/iggnH60tS7GJiBwDW7OoV/XqTpDrt2KTEnMnwDo32UIbh0Ht4/pN1Sp1oAr/R3d0NWun1HIydGOn09Rev+n8RP9Z6/Niv74=;\n\t4:siRuiwY4j66p/XVh7bWDT8LcWw3dzWsDK7qCbIr4lC+/wfAQKhXOUkcSTYEJcCuWDdsI8UrWjgKKwUmiZA39F09YgvPW6GEyh7KOI4H/FLvbdAeNXoV0dDsBJwtbXbhshIg07fDLBKdl8kMBVW78KzP8/BLs9NNcKnu0nA2qw+TLn+EHt4uMsmDFJimXhCHS/qtz+kaIKHTc9OrpvLRH/ZbDw8dJi2gPfhu3DiAva4bbkUfHv1mFGPNOUaw6TTxW", "=?us-ascii?Q?1; MWHPR07MB3472;\n\t23:Hfo9KOunkqff8nmtINT3GrPy/sy6PhsybJayLI9w9?=\n\tCpGU7OsK0aKZwHMjOJqwL7UUtYOGcrRF73+7KEOD+lL4VTJCPiLFBWI2OHUGpg6H7JxY8095RtCLxQj6PV32bqN8iWvTH4y1uHms7oR4mdV1DqRaW/jIwJy+egSdf5bwmPwoIcCcTxVIqYdrX5dfDyYAd7o//1t2f4+sctcmAimzIIAkALc3jc3sRx+4M0xBoD16tJjPERag/Z6y1BMiI2bcEoqg4zKGfVliQoOnBsz9Dxx/M56K37WPvoYktTxI82Fkv681wXLQMFcfGG7kKgw9isuSgYunB52O4X3rMKG6sQ7gsKJKwZ0UDnAcIbOztv2p5XrPi8vDHRVklccwjR3HlYjHb7AMzDd4H/aMWwQwG7nA7qsItDPArF+98iSYThDCqg07DLbOxTyntWRmdUb3fGjr3PN44sLyQmVa2KmlmbhXmGlImrtacIInO+gCGjxd5V4saxozJxkzAdWzUMWhAQ8VHpkOVQ/LQSgfsJTulE1pj0/pAEWM37z/m7AtW2uGottQHulX2HAnrTXy51w3BURfDiXgeREpCyR1Ot24vMPM6tpIz127GY1UTdaEZaD998MAWlMqcQA4OIWCjXrG1lVGfuaZSb9CcuRdUazKZ6mCSKmAJHnn5+BFqZ9pmoppRwDjmcAkc+KMueLi5xhHsjneY8BqLtN8BfJVs9pHblowS8XaaqCbRJ4jhJPxrHQsatnPEn6hxGUgb/js6YfDH2mX4pzVBu1iT1PFOFH6SPDpvmHZlIJhrqccOorqd76JXtNuTj0iIiNlawGWKEzIUPxHnb/gg39uzTY9xfxT0BPNHcG3E158vUZE4MA/iCBgnPYujq6n4Ws6zX1WINSEfWd/rzxZr5sD6gAK7ArakFuqpym7G3o3Eh2tb7JmTxzf47wItJz5l/ZLQ/JJTx8xvHhK7x9txiEOkBZoKoI0g4050/zoFt3HpiL6byvrfdhTjdsVeppFbm5OKhNK5RQteuJU/+5A2hSuD7GyyRRbFYru04BF8Krt3nMBWk6QRrTrO8ts21oJcvBvsGo443/JYNsaFJYwwugeW4TG2IKKsH4IPZJcujbP63xD9OP9N4RbhVAjWP6/dqGRG2sgCuhldoFOtJVmWQpZ39INCqzNMLXx+QybNzY1jLulsJOgbk=", "1; MWHPR07MB3472;\n\t6:04u3p1H3SgJKr8ZxDj7Vgs/3FBALoZawl+fbJOIXpQcp2/TACzTg7Jlp1YVTUD+nLnaseCZ2f4sF0GB5YxfL+LqsgbdZbk+jJxcBAxkD5PDVbhCRSX/Aa3SE5idEFIYkrx9+5SNOfYV8GO3xKlq1z+4bG+OS67BuzMN2J8N9WZrPDsfXp9K+vcP/fXzidmUc2p/zIate/SErHttcU8NNlZLN7Bo16EFLdsLMiJjHnE2O0+b/8W/HxbIiQfmZ/fGkmOq1h6bsLMcaR14EmgJo9dy42RhVBjMznx3r1D8uPgxk2eUAhAi7hYLc+h7gI03rtq6/Sv6quvvNStzotECzOA==;\n\t5:ePLjTbhf0o6ZSHDci5YW4Q4gBVldrOtf8whLyQ4ZFITdWgIZyOEvbBuU3B/SgXjfezPYRdq6oR9R02HPOMGNt3atn4GD0sdp6AWQQEDD/cV8ehsK5BK4RQNiPHqlme3bkj8Feknz1c4fJcAeXsRz1Q==;\n\t24:4DQoKBOIysVpNTdAIrJ1Xk9wXbh/YarQWOhHLt3QKYAWe5+ViqkdHXi1xbViV+GrNxaJ6Ho9dQFgPSrCBGkUuqelHJZJKw04xfhrU2sp2Ks=;\n\t7:quzzQt8Ei4lmqYauUQSGOaIlBItR2Lfh1Mwkrnsbe7kGJDpWdZJR7vu4CROijp6zkiuA2lI1VLihbxrkBb6goD7OafzGY+d78+pEF+3vWuhl5WsxZgBcRonw56XmMUpFMfKmKpyem4RY7xfTn5NyD9xx1oj6RP0uJSEq5PxE9O3cOBgK+yTV3PP9hbmwkbd/t/GAFXew/dXt9x+zQxWdTkSldxjIVKX/hsuBCKiUWH4=" ], "X-MS-TrafficTypeDiagnostic": "MWHPR07MB3472:", "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Microsoft-Antispam-PRVS": "<MWHPR07MB3472D3A01EA6C3AE1AB4C70B80460@MWHPR07MB3472.namprd07.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(5005006)(8121501046)(3231020)(3002001)(10201501046)(100000703101)(100105400095)(93006095)(6041248)(20161123555025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123564025)(20161123562025)(20161123558100)(20161123560025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:MWHPR07MB3472; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:MWHPR07MB3472; ", "X-Forefront-PRVS": "046985391D", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(6069001)(6009001)(376002)(346002)(189002)(199003)(4326008)(48376002)(42882006)(8936002)(2950100002)(8656005)(8656005)(36756003)(6116002)(3846002)(316002)(33646002)(189998001)(107886003)(81156014)(2906002)(81166006)(8676002)(50466002)(16586007)(6636002)(6666003)(66066001)(97736004)(53936002)(47776003)(105586002)(72206003)(7736002)(106356001)(478600001)(101416001)(50986999)(76176999)(5660300001)(6512007)(305945005)(6506006)(50226002)(25786009)(6486002)(16526018)(5003940100001)(68736007)(42262002);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR07MB3472; H:localhost.localdomain;\n\tFPR:; \n\tSPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Oct 2017 16:29:55.1491\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "b6b6e674-514a-4748-2b58-08d51a334c32", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR07MB3472", "Subject": "[dpdk-dev] [PATCH v2 1/3] evendev: fix inconsistency in event queue\n\tconfig", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Bhagavatula <pbhagavatula@caviumnetworks.com>\n\nWith the current scheme of event queue configuration the cfg schedule\ntype macros (RTE_EVENT_QUEUE_CFG_*_ONLY) are inconsistent with the\nevent schedule type (RTE_SCHED_TYPE_*) this requires unnecessary\nconversion between the fastpath and slowpath API's while scheduling\nevents or configuring event queues.\n\nThis patch aims to fix such inconsistency by using event schedule\ntypes (RTE_SCHED_TYPE_*) for event queue configuration.\n\nThis patch also fixes example/eventdev_pipeline_sw_pmd as it doesn't\nconvert RTE_EVENT_QUEUE_CFG_*_ONLY to RTE_SCHED_TYPE_* which leads to\nimproper events being enqueued to the eventdev.\n\nFixes: adb5d5486c39 (\"examples/eventdev_pipeline_sw_pmd: add sample app\")\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>\n---\n app/test-eventdev/evt_common.h | 21 -------------\n app/test-eventdev/test_order_queue.c | 4 +--\n app/test-eventdev/test_perf_queue.c | 4 +--\n drivers/event/dpaa2/dpaa2_eventdev.c | 4 +--\n drivers/event/sw/sw_evdev.c | 28 +++++------------\n examples/eventdev_pipeline_sw_pmd/main.c | 18 +++++------\n lib/librte_eventdev/rte_eventdev.c | 20 +++++-------\n lib/librte_eventdev/rte_eventdev.h | 54 ++++++++++----------------------\n test/test/test_eventdev.c | 12 +++----\n test/test/test_eventdev_sw.c | 16 +++++-----\n 10 files changed, 60 insertions(+), 121 deletions(-)", "diff": "diff --git a/app/test-eventdev/evt_common.h b/app/test-eventdev/evt_common.h\nindex 4102076..ee896a2 100644\n--- a/app/test-eventdev/evt_common.h\n+++ b/app/test-eventdev/evt_common.h\n@@ -92,25 +92,4 @@ evt_has_all_types_queue(uint8_t dev_id)\n \t\t\ttrue : false;\n }\n \n-static inline uint32_t\n-evt_sched_type2queue_cfg(uint8_t sched_type)\n-{\n-\tuint32_t ret;\n-\n-\tswitch (sched_type) {\n-\tcase RTE_SCHED_TYPE_ATOMIC:\n-\t\tret = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY;\n-\t\tbreak;\n-\tcase RTE_SCHED_TYPE_ORDERED:\n-\t\tret = RTE_EVENT_QUEUE_CFG_ORDERED_ONLY;\n-\t\tbreak;\n-\tcase RTE_SCHED_TYPE_PARALLEL:\n-\t\tret = RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY;\n-\t\tbreak;\n-\tdefault:\n-\t\trte_panic(\"Invalid sched_type %d\\n\", sched_type);\n-\t}\n-\treturn ret;\n-}\n-\n #endif /* _EVT_COMMON_*/\ndiff --git a/app/test-eventdev/test_order_queue.c b/app/test-eventdev/test_order_queue.c\nindex beadd9c..1fa4082 100644\n--- a/app/test-eventdev/test_order_queue.c\n+++ b/app/test-eventdev/test_order_queue.c\n@@ -164,7 +164,7 @@ order_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t/* q0 (ordered queue) configuration */\n \tstruct rte_event_queue_conf q0_ordered_conf = {\n \t\t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,\n-\t\t\t.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ORDERED_ONLY,\n+\t\t\t.schedule_type = RTE_SCHED_TYPE_ORDERED,\n \t\t\t.nb_atomic_flows = opt->nb_flows,\n \t\t\t.nb_atomic_order_sequences = opt->nb_flows,\n \t};\n@@ -177,7 +177,7 @@ order_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t/* q1 (atomic queue) configuration */\n \tstruct rte_event_queue_conf q1_atomic_conf = {\n \t\t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,\n-\t\t\t.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY,\n+\t\t\t.schedule_type = RTE_SCHED_TYPE_ATOMIC,\n \t\t\t.nb_atomic_flows = opt->nb_flows,\n \t\t\t.nb_atomic_order_sequences = opt->nb_flows,\n \t};\ndiff --git a/app/test-eventdev/test_perf_queue.c b/app/test-eventdev/test_perf_queue.c\nindex 658c08a..28c2096 100644\n--- a/app/test-eventdev/test_perf_queue.c\n+++ b/app/test-eventdev/test_perf_queue.c\n@@ -205,8 +205,8 @@ perf_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t};\n \t/* queue configurations */\n \tfor (queue = 0; queue < perf_queue_nb_event_queues(opt); queue++) {\n-\t\tq_conf.event_queue_cfg = evt_sched_type2queue_cfg\n-\t\t\t\t(opt->sched_type_list[queue % nb_stages]);\n+\t\tq_conf.event_queue_cfg =\n+\t\t\t(opt->sched_type_list[queue % nb_stages]);\n \n \t\tif (opt->q_priority) {\n \t\t\tuint8_t stage_pos = queue % nb_stages;\ndiff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c\nindex 81286a8..3dbc337 100644\n--- a/drivers/event/dpaa2/dpaa2_eventdev.c\n+++ b/drivers/event/dpaa2/dpaa2_eventdev.c\n@@ -378,8 +378,8 @@ dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,\n \tRTE_SET_USED(queue_conf);\n \n \tqueue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;\n-\tqueue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY |\n-\t\t\t\t RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY;\n+\tqueue_conf->schedule_type = RTE_SCHED_TYPE_ATOMIC |\n+\t\t\t\t RTE_SCHED_TYPE_PARALLEL;\n \tqueue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;\n }\n \ndiff --git a/drivers/event/sw/sw_evdev.c b/drivers/event/sw/sw_evdev.c\nindex aed8b72..522cd71 100644\n--- a/drivers/event/sw/sw_evdev.c\n+++ b/drivers/event/sw/sw_evdev.c\n@@ -345,28 +345,14 @@ sw_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,\n {\n \tint type;\n \n-\t/* SINGLE_LINK can be OR-ed with other types, so handle first */\n+\ttype = conf->schedule_type;\n+\n \tif (RTE_EVENT_QUEUE_CFG_SINGLE_LINK & conf->event_queue_cfg) {\n \t\ttype = SW_SCHED_TYPE_DIRECT;\n-\t} else {\n-\t\tswitch (conf->event_queue_cfg) {\n-\t\tcase RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY:\n-\t\t\ttype = RTE_SCHED_TYPE_ATOMIC;\n-\t\t\tbreak;\n-\t\tcase RTE_EVENT_QUEUE_CFG_ORDERED_ONLY:\n-\t\t\ttype = RTE_SCHED_TYPE_ORDERED;\n-\t\t\tbreak;\n-\t\tcase RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY:\n-\t\t\ttype = RTE_SCHED_TYPE_PARALLEL;\n-\t\t\tbreak;\n-\t\tcase RTE_EVENT_QUEUE_CFG_ALL_TYPES:\n-\t\t\tSW_LOG_ERR(\"QUEUE_CFG_ALL_TYPES not supported\\n\");\n-\t\t\treturn -ENOTSUP;\n-\t\tdefault:\n-\t\t\tSW_LOG_ERR(\"Unknown queue type %d requested\\n\",\n-\t\t\t\t conf->event_queue_cfg);\n-\t\t\treturn -EINVAL;\n-\t\t}\n+\t} else if (RTE_EVENT_QUEUE_CFG_ALL_TYPES\n+\t\t\t& conf->event_queue_cfg) {\n+\t\tSW_LOG_ERR(\"QUEUE_CFG_ALL_TYPES not supported\\n\");\n+\t\treturn -ENOTSUP;\n \t}\n \n \tstruct sw_evdev *sw = sw_pmd_priv(dev);\n@@ -400,7 +386,7 @@ sw_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,\n \tstatic const struct rte_event_queue_conf default_conf = {\n \t\t.nb_atomic_flows = 4096,\n \t\t.nb_atomic_order_sequences = 1,\n-\t\t.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY,\n+\t\t.schedule_type = RTE_SCHED_TYPE_ATOMIC,\n \t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,\n \t};\n \ndiff --git a/examples/eventdev_pipeline_sw_pmd/main.c b/examples/eventdev_pipeline_sw_pmd/main.c\nindex 09b90c3..2e6787b 100644\n--- a/examples/eventdev_pipeline_sw_pmd/main.c\n+++ b/examples/eventdev_pipeline_sw_pmd/main.c\n@@ -108,7 +108,7 @@ struct config_data {\n static struct config_data cdata = {\n \t.num_packets = (1L << 25), /* do ~32M packets */\n \t.num_fids = 512,\n-\t.queue_type = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY,\n+\t.queue_type = RTE_SCHED_TYPE_ATOMIC,\n \t.next_qid = {-1},\n \t.qid = {-1},\n \t.num_stages = 1,\n@@ -490,10 +490,10 @@ parse_app_args(int argc, char **argv)\n \t\t\tcdata.enable_queue_priorities = 1;\n \t\t\tbreak;\n \t\tcase 'o':\n-\t\t\tcdata.queue_type = RTE_EVENT_QUEUE_CFG_ORDERED_ONLY;\n+\t\t\tcdata.queue_type = RTE_SCHED_TYPE_ORDERED;\n \t\t\tbreak;\n \t\tcase 'p':\n-\t\t\tcdata.queue_type = RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY;\n+\t\t\tcdata.queue_type = RTE_SCHED_TYPE_PARALLEL;\n \t\t\tbreak;\n \t\tcase 'q':\n \t\t\tcdata.quiet = 1;\n@@ -684,7 +684,7 @@ setup_eventdev(struct prod_data *prod_data,\n \t\t\t.new_event_threshold = 4096,\n \t};\n \tstruct rte_event_queue_conf wkr_q_conf = {\n-\t\t\t.event_queue_cfg = cdata.queue_type,\n+\t\t\t.schedule_type = cdata.queue_type,\n \t\t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,\n \t\t\t.nb_atomic_flows = 1024,\n \t\t\t.nb_atomic_order_sequences = 1024,\n@@ -751,11 +751,11 @@ setup_eventdev(struct prod_data *prod_data,\n \t\t}\n \n \t\tconst char *type_str = \"Atomic\";\n-\t\tswitch (wkr_q_conf.event_queue_cfg) {\n-\t\tcase RTE_EVENT_QUEUE_CFG_ORDERED_ONLY:\n+\t\tswitch (wkr_q_conf.schedule_type) {\n+\t\tcase RTE_SCHED_TYPE_ORDERED:\n \t\t\ttype_str = \"Ordered\";\n \t\t\tbreak;\n-\t\tcase RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY:\n+\t\tcase RTE_SCHED_TYPE_PARALLEL:\n \t\t\ttype_str = \"Parallel\";\n \t\t\tbreak;\n \t\t}\n@@ -907,9 +907,9 @@ main(int argc, char **argv)\n \t\tprintf(\"\\tworkers: %u\\n\", cdata.num_workers);\n \t\tprintf(\"\\tpackets: %\"PRIi64\"\\n\", cdata.num_packets);\n \t\tprintf(\"\\tQueue-prio: %u\\n\", cdata.enable_queue_priorities);\n-\t\tif (cdata.queue_type == RTE_EVENT_QUEUE_CFG_ORDERED_ONLY)\n+\t\tif (cdata.queue_type == RTE_SCHED_TYPE_ORDERED)\n \t\t\tprintf(\"\\tqid0 type: ordered\\n\");\n-\t\tif (cdata.queue_type == RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY)\n+\t\tif (cdata.queue_type == RTE_SCHED_TYPE_ATOMIC)\n \t\t\tprintf(\"\\tqid0 type: atomic\\n\");\n \t\tprintf(\"\\tCores available: %u\\n\", rte_lcore_count());\n \t\tprintf(\"\\tCores used: %u\\n\", cores_needed);\ndiff --git a/lib/librte_eventdev/rte_eventdev.c b/lib/librte_eventdev/rte_eventdev.c\nindex 378ccb5..db96552 100644\n--- a/lib/librte_eventdev/rte_eventdev.c\n+++ b/lib/librte_eventdev/rte_eventdev.c\n@@ -517,13 +517,11 @@ is_valid_atomic_queue_conf(const struct rte_event_queue_conf *queue_conf)\n {\n \tif (queue_conf &&\n \t\t!(queue_conf->event_queue_cfg &\n-\t\t RTE_EVENT_QUEUE_CFG_SINGLE_LINK) && (\n+\t\t RTE_EVENT_QUEUE_CFG_SINGLE_LINK) &&\n \t\t((queue_conf->event_queue_cfg &\n-\t\t\tRTE_EVENT_QUEUE_CFG_TYPE_MASK)\n-\t\t\t== RTE_EVENT_QUEUE_CFG_ALL_TYPES) ||\n-\t\t((queue_conf->event_queue_cfg &\n-\t\t\tRTE_EVENT_QUEUE_CFG_TYPE_MASK)\n-\t\t\t== RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY)\n+\t\t\t RTE_EVENT_QUEUE_CFG_ALL_TYPES) ||\n+\t\t(queue_conf->schedule_type\n+\t\t\t== RTE_SCHED_TYPE_ATOMIC)\n \t\t))\n \t\treturn 1;\n \telse\n@@ -535,13 +533,11 @@ is_valid_ordered_queue_conf(const struct rte_event_queue_conf *queue_conf)\n {\n \tif (queue_conf &&\n \t\t!(queue_conf->event_queue_cfg &\n-\t\t RTE_EVENT_QUEUE_CFG_SINGLE_LINK) && (\n-\t\t((queue_conf->event_queue_cfg &\n-\t\t\tRTE_EVENT_QUEUE_CFG_TYPE_MASK)\n-\t\t\t== RTE_EVENT_QUEUE_CFG_ALL_TYPES) ||\n+\t\t RTE_EVENT_QUEUE_CFG_SINGLE_LINK) &&\n \t\t((queue_conf->event_queue_cfg &\n-\t\t\tRTE_EVENT_QUEUE_CFG_TYPE_MASK)\n-\t\t\t== RTE_EVENT_QUEUE_CFG_ORDERED_ONLY)\n+\t\t\t RTE_EVENT_QUEUE_CFG_ALL_TYPES) ||\n+\t\t(queue_conf->schedule_type\n+\t\t\t== RTE_SCHED_TYPE_ORDERED)\n \t\t))\n \t\treturn 1;\n \telse\ndiff --git a/lib/librte_eventdev/rte_eventdev.h b/lib/librte_eventdev/rte_eventdev.h\nindex 1dbc872..fa16f82 100644\n--- a/lib/librte_eventdev/rte_eventdev.h\n+++ b/lib/librte_eventdev/rte_eventdev.h\n@@ -270,9 +270,9 @@ struct rte_mbuf; /* we just use mbuf pointers; no need to include rte_mbuf.h */\n #define RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES (1ULL << 3)\n /**< Event device is capable of enqueuing events of any type to any queue.\n * If this capability is not set, the queue only supports events of the\n- * *RTE_EVENT_QUEUE_CFG_* type that it was created with.\n+ * *RTE_SCHED_TYPE_* type that it was created with.\n *\n- * @see RTE_EVENT_QUEUE_CFG_* values\n+ * @see RTE_SCHED_TYPE_* values\n */\n #define RTE_EVENT_DEV_CAP_BURST_MODE (1ULL << 4)\n /**< Event device is capable of operating in burst mode for enqueue(forward,\n@@ -515,39 +515,13 @@ rte_event_dev_configure(uint8_t dev_id,\n /* Event queue specific APIs */\n \n /* Event queue configuration bitmap flags */\n-#define RTE_EVENT_QUEUE_CFG_TYPE_MASK (3ULL << 0)\n-/**< Mask for event queue schedule type configuration request */\n-#define RTE_EVENT_QUEUE_CFG_ALL_TYPES (0ULL << 0)\n+#define RTE_EVENT_QUEUE_CFG_ALL_TYPES (1ULL << 0)\n /**< Allow ATOMIC,ORDERED,PARALLEL schedule type enqueue\n *\n * @see RTE_SCHED_TYPE_ORDERED, RTE_SCHED_TYPE_ATOMIC, RTE_SCHED_TYPE_PARALLEL\n * @see rte_event_enqueue_burst()\n */\n-#define RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY (1ULL << 0)\n-/**< Allow only ATOMIC schedule type enqueue\n- *\n- * The rte_event_enqueue_burst() result is undefined if the queue configured\n- * with ATOMIC only and sched_type != RTE_SCHED_TYPE_ATOMIC\n- *\n- * @see RTE_SCHED_TYPE_ATOMIC, rte_event_enqueue_burst()\n- */\n-#define RTE_EVENT_QUEUE_CFG_ORDERED_ONLY (2ULL << 0)\n-/**< Allow only ORDERED schedule type enqueue\n- *\n- * The rte_event_enqueue_burst() result is undefined if the queue configured\n- * with ORDERED only and sched_type != RTE_SCHED_TYPE_ORDERED\n- *\n- * @see RTE_SCHED_TYPE_ORDERED, rte_event_enqueue_burst()\n- */\n-#define RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY (3ULL << 0)\n-/**< Allow only PARALLEL schedule type enqueue\n- *\n- * The rte_event_enqueue_burst() result is undefined if the queue configured\n- * with PARALLEL only and sched_type != RTE_SCHED_TYPE_PARALLEL\n- *\n- * @see RTE_SCHED_TYPE_PARALLEL, rte_event_enqueue_burst()\n- */\n-#define RTE_EVENT_QUEUE_CFG_SINGLE_LINK (1ULL << 2)\n+#define RTE_EVENT_QUEUE_CFG_SINGLE_LINK (1ULL << 1)\n /**< This event queue links only to a single event port.\n *\n * @see rte_event_port_setup(), rte_event_port_link()\n@@ -558,8 +532,8 @@ struct rte_event_queue_conf {\n \tuint32_t nb_atomic_flows;\n \t/**< The maximum number of active flows this queue can track at any\n \t * given time. If the queue is configured for atomic scheduling (by\n-\t * applying the RTE_EVENT_QUEUE_CFG_ALL_TYPES or\n-\t * RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY flags to event_queue_cfg), then the\n+\t * applying the RTE_EVENT_QUEUE_CFG_ALL_TYPES flag to event_queue_cfg\n+\t * or RTE_SCHED_TYPE_ATOMIC flag to schedule_type), then the\n \t * value must be in the range of [1, nb_event_queue_flows], which was\n \t * previously provided in rte_event_dev_configure().\n \t */\n@@ -572,12 +546,18 @@ struct rte_event_queue_conf {\n \t * event will be returned from dequeue until one or more entries are\n \t * freed up/released.\n \t * If the queue is configured for ordered scheduling (by applying the\n-\t * RTE_EVENT_QUEUE_CFG_ALL_TYPES or RTE_EVENT_QUEUE_CFG_ORDERED_ONLY\n-\t * flags to event_queue_cfg), then the value must be in the range of\n-\t * [1, nb_event_queue_flows], which was previously supplied to\n-\t * rte_event_dev_configure().\n+\t * RTE_EVENT_QUEUE_CFG_ALL_TYPES flag to event_queue_cfg or\n+\t * RTE_SCHED_TYPE_ORDERED flag to schedule_type), then the value must\n+\t * be in the range of [1, nb_event_queue_flows], which was\n+\t * previously supplied to rte_event_dev_configure().\n+\t */\n+\tuint32_t event_queue_cfg;\n+\t/**< Queue cfg flags(EVENT_QUEUE_CFG_) */\n+\tuint8_t schedule_type;\n+\t/**< Queue schedule type(RTE_SCHED_TYPE_*).\n+\t * Valid when RTE_EVENT_QUEUE_CFG_ALL_TYPES bit is not set in\n+\t * event_queue_cfg.\n \t */\n-\tuint32_t event_queue_cfg; /**< Queue cfg flags(EVENT_QUEUE_CFG_) */\n \tuint8_t priority;\n \t/**< Priority for this event queue relative to other event queues.\n \t * The requested priority should in the range of\ndiff --git a/test/test/test_eventdev.c b/test/test/test_eventdev.c\nindex d6ade78..4118b75 100644\n--- a/test/test/test_eventdev.c\n+++ b/test/test/test_eventdev.c\n@@ -300,15 +300,13 @@ test_eventdev_queue_setup(void)\n \t/* Negative cases */\n \tret = rte_event_queue_default_conf_get(TEST_DEV_ID, 0, &qconf);\n \tTEST_ASSERT_SUCCESS(ret, \"Failed to get queue0 info\");\n-\tqconf.event_queue_cfg =\t(RTE_EVENT_QUEUE_CFG_ALL_TYPES &\n-\t\t RTE_EVENT_QUEUE_CFG_TYPE_MASK);\n+\tqconf.event_queue_cfg =\tRTE_EVENT_QUEUE_CFG_ALL_TYPES;\n \tqconf.nb_atomic_flows = info.max_event_queue_flows + 1;\n \tret = rte_event_queue_setup(TEST_DEV_ID, 0, &qconf);\n \tTEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n \n \tqconf.nb_atomic_flows = info.max_event_queue_flows;\n-\tqconf.event_queue_cfg =\t(RTE_EVENT_QUEUE_CFG_ORDERED_ONLY &\n-\t\t RTE_EVENT_QUEUE_CFG_TYPE_MASK);\n+\tqconf.schedule_type = RTE_SCHED_TYPE_ORDERED;\n \tqconf.nb_atomic_order_sequences = info.max_event_queue_flows + 1;\n \tret = rte_event_queue_setup(TEST_DEV_ID, 0, &qconf);\n \tTEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n@@ -423,7 +421,7 @@ test_eventdev_queue_attr_nb_atomic_flows(void)\n \t\t/* Assume PMD doesn't support atomic flows, return early */\n \t\treturn -ENOTSUP;\n \n-\tqconf.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY;\n+\tqconf.schedule_type = RTE_SCHED_TYPE_ATOMIC;\n \n \tfor (i = 0; i < (int)queue_count; i++) {\n \t\tret = rte_event_queue_setup(TEST_DEV_ID, i, &qconf);\n@@ -466,7 +464,7 @@ test_eventdev_queue_attr_nb_atomic_order_sequences(void)\n \t\t/* Assume PMD doesn't support reordering */\n \t\treturn -ENOTSUP;\n \n-\tqconf.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ORDERED_ONLY;\n+\tqconf.schedule_type = RTE_SCHED_TYPE_ORDERED;\n \n \tfor (i = 0; i < (int)queue_count; i++) {\n \t\tret = rte_event_queue_setup(TEST_DEV_ID, i, &qconf);\n@@ -507,7 +505,7 @@ test_eventdev_queue_attr_event_queue_cfg(void)\n \tret = rte_event_queue_default_conf_get(TEST_DEV_ID, 0, &qconf);\n \tTEST_ASSERT_SUCCESS(ret, \"Failed to get queue0 def conf\");\n \n-\tqconf.event_queue_cfg = RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY;\n+\tqconf.event_queue_cfg = RTE_EVENT_QUEUE_CFG_SINGLE_LINK;\n \n \tfor (i = 0; i < (int)queue_count; i++) {\n \t\tret = rte_event_queue_setup(TEST_DEV_ID, i, &qconf);\ndiff --git a/test/test/test_eventdev_sw.c b/test/test/test_eventdev_sw.c\nindex 7219886..dea302f 100644\n--- a/test/test/test_eventdev_sw.c\n+++ b/test/test/test_eventdev_sw.c\n@@ -219,7 +219,7 @@ create_lb_qids(struct test *t, int num_qids, uint32_t flags)\n \n \t/* Q creation */\n \tconst struct rte_event_queue_conf conf = {\n-\t\t\t.event_queue_cfg = flags,\n+\t\t\t.schedule_type = flags,\n \t\t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,\n \t\t\t.nb_atomic_flows = 1024,\n \t\t\t.nb_atomic_order_sequences = 1024,\n@@ -242,20 +242,20 @@ create_lb_qids(struct test *t, int num_qids, uint32_t flags)\n static inline int\n create_atomic_qids(struct test *t, int num_qids)\n {\n-\treturn create_lb_qids(t, num_qids, RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY);\n+\treturn create_lb_qids(t, num_qids, RTE_SCHED_TYPE_ATOMIC);\n }\n \n static inline int\n create_ordered_qids(struct test *t, int num_qids)\n {\n-\treturn create_lb_qids(t, num_qids, RTE_EVENT_QUEUE_CFG_ORDERED_ONLY);\n+\treturn create_lb_qids(t, num_qids, RTE_SCHED_TYPE_ORDERED);\n }\n \n \n static inline int\n create_unordered_qids(struct test *t, int num_qids)\n {\n-\treturn create_lb_qids(t, num_qids, RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY);\n+\treturn create_lb_qids(t, num_qids, RTE_SCHED_TYPE_PARALLEL);\n }\n \n static inline int\n@@ -1238,7 +1238,7 @@ port_reconfig_credits(struct test *t)\n \tconst uint32_t NUM_ITERS = 32;\n \tfor (i = 0; i < NUM_ITERS; i++) {\n \t\tconst struct rte_event_queue_conf conf = {\n-\t\t\t.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY,\n+\t\t\t.schedule_type = RTE_SCHED_TYPE_ATOMIC,\n \t\t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,\n \t\t\t.nb_atomic_flows = 1024,\n \t\t\t.nb_atomic_order_sequences = 1024,\n@@ -1320,7 +1320,7 @@ port_single_lb_reconfig(struct test *t)\n \n \tstatic const struct rte_event_queue_conf conf_lb_atomic = {\n \t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,\n-\t\t.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY,\n+\t\t.schedule_type = RTE_SCHED_TYPE_ATOMIC,\n \t\t.nb_atomic_flows = 1024,\n \t\t.nb_atomic_order_sequences = 1024,\n \t};\n@@ -1818,7 +1818,7 @@ ordered_reconfigure(struct test *t)\n \t}\n \n \tconst struct rte_event_queue_conf conf = {\n-\t\t\t.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ORDERED_ONLY,\n+\t\t\t.schedule_type = RTE_SCHED_TYPE_ORDERED,\n \t\t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,\n \t\t\t.nb_atomic_flows = 1024,\n \t\t\t.nb_atomic_order_sequences = 1024,\n@@ -1865,7 +1865,7 @@ qid_priorities(struct test *t)\n \tfor (i = 0; i < 3; i++) {\n \t\t/* Create QID */\n \t\tconst struct rte_event_queue_conf conf = {\n-\t\t\t.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY,\n+\t\t\t.schedule_type = RTE_SCHED_TYPE_ATOMIC,\n \t\t\t/* increase priority (0 == highest), as we go */\n \t\t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL - i,\n \t\t\t.nb_atomic_flows = 1024,\n", "prefixes": [ "dpdk-dev", "v2", "1/3" ] }