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GET /api/patches/30275/?format=api
{ "id": 30275, "url": "http://patches.dpdk.org/api/patches/30275/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/6a50316ed3b2b7a8607baa6c8cf8414e2400a980.1507809961.git.adrien.mazarguil@6wind.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<6a50316ed3b2b7a8607baa6c8cf8414e2400a980.1507809961.git.adrien.mazarguil@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/6a50316ed3b2b7a8607baa6c8cf8414e2400a980.1507809961.git.adrien.mazarguil@6wind.com", "date": "2017-10-12T12:19:38", "name": "[dpdk-dev,v2,24/29] net/mlx4: allocate queues and mbuf rings together", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8b79d583e97d6e26feb3a3e923820fa93c405c6f", "submitter": { "id": 165, "url": "http://patches.dpdk.org/api/people/165/?format=api", "name": "Adrien Mazarguil", "email": "adrien.mazarguil@6wind.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/6a50316ed3b2b7a8607baa6c8cf8414e2400a980.1507809961.git.adrien.mazarguil@6wind.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/30275/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/30275/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9D9381B332;\n\tThu, 12 Oct 2017 14:20:53 +0200 (CEST)", "from mail-wm0-f47.google.com (mail-wm0-f47.google.com\n\t[74.125.82.47]) by dpdk.org (Postfix) with ESMTP id DE12D1B2C7\n\tfor <dev@dpdk.org>; Thu, 12 Oct 2017 14:20:38 +0200 (CEST)", "by mail-wm0-f47.google.com with SMTP id m72so12692846wmc.1\n\tfor <dev@dpdk.org>; Thu, 12 Oct 2017 05:20:38 -0700 (PDT)", "from 6wind.com (host.78.145.23.62.rev.coltfrance.com.\n\t[62.23.145.78]) by smtp.gmail.com with ESMTPSA id\n\t67sm144623wmw.22.2017.10.12.05.20.37\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 12 Oct 2017 05:20:37 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=6wind-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=wS0VKQfx98w4TgkVtRp8qXvUtS56Kq6/J3ooLENKkVc=;\n\tb=d3yghcsPs63NThoO3GGTe+4I31hvyK6dQMGdqZR3Byb6CvYrqXLZ8bQHLMlyLJ/Lpp\n\tbjAzYYSiH3QBSUju02u2WT+nuoimYc/K1OvMOHtN6vtMXja6wKZy6EMEgPem/ZHVwXr1\n\tnO6ncXK1g9Mw9ndmlX77s8X8gJc0lfsn9QYbQk1/UvzaJ9nLi++WE7dfnw2iP8Vnl236\n\tSHxiS28p3wWhxdEQ+VmDKci87O/ezRVK3zR/9xRFpUgZTriW53KxG4Euv3q0heY+sMxg\n\t0iS5KN6Eu7JYTwj29xR0EQatk9CUyumMeJK5MpbbqpxwiUKUO09CET02Wb1N2wwyU9Fx\n\tQn+A==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=wS0VKQfx98w4TgkVtRp8qXvUtS56Kq6/J3ooLENKkVc=;\n\tb=A6IcfMjEV+/d6VS7rxEG3rZoQAsMTnug7bduKWvEcMikpB9TLbqc33PJwM7YsczgCC\n\thLsbQ3KiYj8XT7V/q2B5myCFmECLoW96409Kg25iSd0Qu0sI3cdOOr6957ovM+x7PP2J\n\tU2FDghtCVls/eZ+KAaHQlo6qqBVZhmCZ4S9SE//zV9CJNB+2KqlQInVuOrVF9A94dElo\n\tat+4hBsPl+SG20llRePpGb5MVM53sPqUZDjVmVpXiPpMS2/xAuTc44bogr6EN1NNQ4xz\n\tiRHQoW6h2UwJt928v3z7UX47IMdRR0N1P6d7FDoHxQDmRe2QICKKhG49hGVWry3fvrhc\n\tUNfA==", "X-Gm-Message-State": "AMCzsaWvkLqEA8AEQl//wuY3FsLlQ4exp5w1/zrLCLgo/iqaMU3BMUQ2\n\tqq+gpvy9Ny64+TykHRHD5UWCATlv", "X-Google-Smtp-Source": "AOwi7QAkgJ/H49nPpicofPtaZK6B17oAOoJuZ9jZbMin4ORBL2CjBzx90BpgKdUmNH862awiqZL7yQ==", "X-Received": "by 10.223.188.13 with SMTP id s13mr2233954wrg.39.1507810838364; \n\tThu, 12 Oct 2017 05:20:38 -0700 (PDT)", "From": "Adrien Mazarguil <adrien.mazarguil@6wind.com>", "To": "Ferruh Yigit <ferruh.yigit@intel.com>", "Cc": "Nelio Laranjeiro <nelio.laranjeiro@6wind.com>,\n\tdev@dpdk.org", "Date": "Thu, 12 Oct 2017 14:19:38 +0200", "Message-Id": "<6a50316ed3b2b7a8607baa6c8cf8414e2400a980.1507809961.git.adrien.mazarguil@6wind.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<cover.1507809961.git.adrien.mazarguil@6wind.com>", "References": "<cover.1507730496.git.adrien.mazarguil@6wind.com>\n\t<cover.1507809961.git.adrien.mazarguil@6wind.com>", "Subject": "[dpdk-dev] [PATCH v2 24/29] net/mlx4: allocate queues and mbuf\n\trings together", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Since live Tx and Rx queues cannot be reused anymore without being\ndestroyed first, mbuf ring sizes are fixed and known from the start.\n\nThis allows a single allocation for queue data structures and mbuf ring\ntogether, saving space and bringing them closer in memory.\n\nSigned-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>\nAcked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>\n---\n drivers/net/mlx4/mlx4_rxq.c | 71 +++++++++++--------------\n drivers/net/mlx4/mlx4_rxtx.h | 2 +\n drivers/net/mlx4/mlx4_txq.c | 109 +++++++++++---------------------------\n 3 files changed, 65 insertions(+), 117 deletions(-)", "diff": "diff --git a/drivers/net/mlx4/mlx4_rxq.c b/drivers/net/mlx4/mlx4_rxq.c\nindex 30b0654..9978e5d 100644\n--- a/drivers/net/mlx4/mlx4_rxq.c\n+++ b/drivers/net/mlx4/mlx4_rxq.c\n@@ -69,36 +69,30 @@\n *\n * @param rxq\n * Pointer to Rx queue structure.\n- * @param elts_n\n- * Number of elements to allocate.\n *\n * @return\n * 0 on success, negative errno value otherwise and rte_errno is set.\n */\n static int\n-mlx4_rxq_alloc_elts(struct rxq *rxq, unsigned int elts_n)\n+mlx4_rxq_alloc_elts(struct rxq *rxq)\n {\n+\tstruct rxq_elt (*elts)[rxq->elts_n] = rxq->elts;\n \tunsigned int i;\n-\tstruct rxq_elt (*elts)[elts_n] =\n-\t\trte_calloc_socket(\"RXQ elements\", 1, sizeof(*elts), 0,\n-\t\t\t\t rxq->socket);\n \n-\tif (elts == NULL) {\n-\t\trte_errno = ENOMEM;\n-\t\tERROR(\"%p: can't allocate packets array\", (void *)rxq);\n-\t\tgoto error;\n-\t}\n \t/* For each WR (packet). */\n-\tfor (i = 0; (i != elts_n); ++i) {\n+\tfor (i = 0; i != RTE_DIM(*elts); ++i) {\n \t\tstruct rxq_elt *elt = &(*elts)[i];\n \t\tstruct ibv_recv_wr *wr = &elt->wr;\n \t\tstruct ibv_sge *sge = &(*elts)[i].sge;\n \t\tstruct rte_mbuf *buf = rte_pktmbuf_alloc(rxq->mp);\n \n \t\tif (buf == NULL) {\n+\t\t\twhile (i--) {\n+\t\t\t\trte_pktmbuf_free_seg((*elts)[i].buf);\n+\t\t\t\t(*elts)[i].buf = NULL;\n+\t\t\t}\n \t\t\trte_errno = ENOMEM;\n-\t\t\tERROR(\"%p: empty mbuf pool\", (void *)rxq);\n-\t\t\tgoto error;\n+\t\t\treturn -rte_errno;\n \t\t}\n \t\telt->buf = buf;\n \t\twr->next = &(*elts)[(i + 1)].wr;\n@@ -121,21 +115,7 @@ mlx4_rxq_alloc_elts(struct rxq *rxq, unsigned int elts_n)\n \t}\n \t/* The last WR pointer must be NULL. */\n \t(*elts)[(i - 1)].wr.next = NULL;\n-\tDEBUG(\"%p: allocated and configured %u single-segment WRs\",\n-\t (void *)rxq, elts_n);\n-\trxq->elts_n = elts_n;\n-\trxq->elts_head = 0;\n-\trxq->elts = elts;\n \treturn 0;\n-error:\n-\tif (elts != NULL) {\n-\t\tfor (i = 0; (i != RTE_DIM(*elts)); ++i)\n-\t\t\trte_pktmbuf_free_seg((*elts)[i].buf);\n-\t\trte_free(elts);\n-\t}\n-\tDEBUG(\"%p: failed, freed everything\", (void *)rxq);\n-\tassert(rte_errno > 0);\n-\treturn -rte_errno;\n }\n \n /**\n@@ -148,17 +128,15 @@ static void\n mlx4_rxq_free_elts(struct rxq *rxq)\n {\n \tunsigned int i;\n-\tunsigned int elts_n = rxq->elts_n;\n-\tstruct rxq_elt (*elts)[elts_n] = rxq->elts;\n+\tstruct rxq_elt (*elts)[rxq->elts_n] = rxq->elts;\n \n \tDEBUG(\"%p: freeing WRs\", (void *)rxq);\n-\trxq->elts_n = 0;\n-\trxq->elts = NULL;\n-\tif (elts == NULL)\n-\t\treturn;\n-\tfor (i = 0; (i != RTE_DIM(*elts)); ++i)\n+\tfor (i = 0; (i != RTE_DIM(*elts)); ++i) {\n+\t\tif (!(*elts)[i].buf)\n+\t\t\tcontinue;\n \t\trte_pktmbuf_free_seg((*elts)[i].buf);\n-\trte_free(elts);\n+\t\t(*elts)[i].buf = NULL;\n+\t}\n }\n \n /**\n@@ -187,8 +165,21 @@ mlx4_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n {\n \tstruct priv *priv = dev->data->dev_private;\n \tuint32_t mb_len = rte_pktmbuf_data_room_size(mp);\n+\tstruct rxq_elt (*elts)[desc];\n \tstruct rte_flow_error error;\n \tstruct rxq *rxq;\n+\tstruct mlx4_malloc_vec vec[] = {\n+\t\t{\n+\t\t\t.align = RTE_CACHE_LINE_SIZE,\n+\t\t\t.size = sizeof(*rxq),\n+\t\t\t.addr = (void **)&rxq,\n+\t\t},\n+\t\t{\n+\t\t\t.align = RTE_CACHE_LINE_SIZE,\n+\t\t\t.size = sizeof(*elts),\n+\t\t\t.addr = (void **)&elts,\n+\t\t},\n+\t};\n \tint ret;\n \n \t(void)conf; /* Thresholds configuration (ignored). */\n@@ -213,9 +204,8 @@ mlx4_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\treturn -rte_errno;\n \t}\n \t/* Allocate and initialize Rx queue. */\n-\trxq = rte_calloc_socket(\"RXQ\", 1, sizeof(*rxq), 0, socket);\n+\tmlx4_zmallocv_socket(\"RXQ\", vec, RTE_DIM(vec), socket);\n \tif (!rxq) {\n-\t\trte_errno = ENOMEM;\n \t\tERROR(\"%p: unable to allocate queue index %u\",\n \t\t (void *)dev, idx);\n \t\treturn -rte_errno;\n@@ -224,6 +214,9 @@ mlx4_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\t.priv = priv,\n \t\t.mp = mp,\n \t\t.port_id = dev->data->port_id,\n+\t\t.elts_n = desc,\n+\t\t.elts_head = 0,\n+\t\t.elts = elts,\n \t\t.stats.idx = idx,\n \t\t.socket = socket,\n \t};\n@@ -307,7 +300,7 @@ mlx4_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\t (void *)dev, strerror(rte_errno));\n \t\tgoto error;\n \t}\n-\tret = mlx4_rxq_alloc_elts(rxq, desc);\n+\tret = mlx4_rxq_alloc_elts(rxq);\n \tif (ret) {\n \t\tERROR(\"%p: RXQ allocation failed: %s\",\n \t\t (void *)dev, strerror(rte_errno));\ndiff --git a/drivers/net/mlx4/mlx4_rxtx.h b/drivers/net/mlx4/mlx4_rxtx.h\nindex d62120e..d90f2f9 100644\n--- a/drivers/net/mlx4/mlx4_rxtx.h\n+++ b/drivers/net/mlx4/mlx4_rxtx.h\n@@ -81,6 +81,7 @@ struct rxq {\n \tstruct rxq_elt (*elts)[]; /**< Rx elements. */\n \tstruct mlx4_rxq_stats stats; /**< Rx queue counters. */\n \tunsigned int socket; /**< CPU socket ID for allocations. */\n+\tuint8_t data[]; /**< Remaining queue resources. */\n };\n \n /** Tx element. */\n@@ -118,6 +119,7 @@ struct txq {\n \tunsigned int elts_comp_cd_init; /**< Initial value for countdown. */\n \tstruct mlx4_txq_stats stats; /**< Tx queue counters. */\n \tunsigned int socket; /**< CPU socket ID for allocations. */\n+\tuint8_t data[]; /**< Remaining queue resources. */\n };\n \n /* mlx4_rxq.c */\ndiff --git a/drivers/net/mlx4/mlx4_txq.c b/drivers/net/mlx4/mlx4_txq.c\nindex f102c68..915f8d7 100644\n--- a/drivers/net/mlx4/mlx4_txq.c\n+++ b/drivers/net/mlx4/mlx4_txq.c\n@@ -64,59 +64,6 @@\n #include \"mlx4_utils.h\"\n \n /**\n- * Allocate Tx queue elements.\n- *\n- * @param txq\n- * Pointer to Tx queue structure.\n- * @param elts_n\n- * Number of elements to allocate.\n- *\n- * @return\n- * 0 on success, negative errno value otherwise and rte_errno is set.\n- */\n-static int\n-mlx4_txq_alloc_elts(struct txq *txq, unsigned int elts_n)\n-{\n-\tunsigned int i;\n-\tstruct txq_elt (*elts)[elts_n] =\n-\t\trte_calloc_socket(\"TXQ\", 1, sizeof(*elts), 0, txq->socket);\n-\tint ret = 0;\n-\n-\tif (elts == NULL) {\n-\t\tERROR(\"%p: can't allocate packets array\", (void *)txq);\n-\t\tret = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\tfor (i = 0; (i != elts_n); ++i) {\n-\t\tstruct txq_elt *elt = &(*elts)[i];\n-\n-\t\telt->buf = NULL;\n-\t}\n-\tDEBUG(\"%p: allocated and configured %u WRs\", (void *)txq, elts_n);\n-\ttxq->elts_n = elts_n;\n-\ttxq->elts = elts;\n-\ttxq->elts_head = 0;\n-\ttxq->elts_tail = 0;\n-\ttxq->elts_comp = 0;\n-\t/*\n-\t * Request send completion every MLX4_PMD_TX_PER_COMP_REQ packets or\n-\t * at least 4 times per ring.\n-\t */\n-\ttxq->elts_comp_cd_init =\n-\t\t((MLX4_PMD_TX_PER_COMP_REQ < (elts_n / 4)) ?\n-\t\t MLX4_PMD_TX_PER_COMP_REQ : (elts_n / 4));\n-\ttxq->elts_comp_cd = txq->elts_comp_cd_init;\n-\tassert(ret == 0);\n-\treturn 0;\n-error:\n-\trte_free(elts);\n-\tDEBUG(\"%p: failed, freed everything\", (void *)txq);\n-\tassert(ret > 0);\n-\trte_errno = ret;\n-\treturn -rte_errno;\n-}\n-\n-/**\n * Free Tx queue elements.\n *\n * @param txq\n@@ -125,34 +72,21 @@ mlx4_txq_alloc_elts(struct txq *txq, unsigned int elts_n)\n static void\n mlx4_txq_free_elts(struct txq *txq)\n {\n-\tunsigned int elts_n = txq->elts_n;\n \tunsigned int elts_head = txq->elts_head;\n \tunsigned int elts_tail = txq->elts_tail;\n-\tstruct txq_elt (*elts)[elts_n] = txq->elts;\n+\tstruct txq_elt (*elts)[txq->elts_n] = txq->elts;\n \n \tDEBUG(\"%p: freeing WRs\", (void *)txq);\n-\ttxq->elts_n = 0;\n-\ttxq->elts_head = 0;\n-\ttxq->elts_tail = 0;\n-\ttxq->elts_comp = 0;\n-\ttxq->elts_comp_cd = 0;\n-\ttxq->elts_comp_cd_init = 0;\n-\ttxq->elts = NULL;\n-\tif (elts == NULL)\n-\t\treturn;\n \twhile (elts_tail != elts_head) {\n \t\tstruct txq_elt *elt = &(*elts)[elts_tail];\n \n \t\tassert(elt->buf != NULL);\n \t\trte_pktmbuf_free(elt->buf);\n-#ifndef NDEBUG\n-\t\t/* Poisoning. */\n-\t\tmemset(elt, 0x77, sizeof(*elt));\n-#endif\n-\t\tif (++elts_tail == elts_n)\n+\t\telt->buf = NULL;\n+\t\tif (++elts_tail == RTE_DIM(*elts))\n \t\t\telts_tail = 0;\n \t}\n-\trte_free(elts);\n+\ttxq->elts_tail = txq->elts_head;\n }\n \n struct txq_mp2mr_mbuf_check_data {\n@@ -235,8 +169,21 @@ mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\t unsigned int socket, const struct rte_eth_txconf *conf)\n {\n \tstruct priv *priv = dev->data->dev_private;\n+\tstruct txq_elt (*elts)[desc];\n \tstruct ibv_qp_init_attr qp_init_attr;\n \tstruct txq *txq;\n+\tstruct mlx4_malloc_vec vec[] = {\n+\t\t{\n+\t\t\t.align = RTE_CACHE_LINE_SIZE,\n+\t\t\t.size = sizeof(*txq),\n+\t\t\t.addr = (void **)&txq,\n+\t\t},\n+\t\t{\n+\t\t\t.align = RTE_CACHE_LINE_SIZE,\n+\t\t\t.size = sizeof(*elts),\n+\t\t\t.addr = (void **)&elts,\n+\t\t},\n+\t};\n \tint ret;\n \n \t(void)conf; /* Thresholds configuration (ignored). */\n@@ -261,9 +208,8 @@ mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\treturn -rte_errno;\n \t}\n \t/* Allocate and initialize Tx queue. */\n-\ttxq = rte_calloc_socket(\"TXQ\", 1, sizeof(*txq), 0, socket);\n+\tmlx4_zmallocv_socket(\"TXQ\", vec, RTE_DIM(vec), socket);\n \tif (!txq) {\n-\t\trte_errno = ENOMEM;\n \t\tERROR(\"%p: unable to allocate queue index %u\",\n \t\t (void *)dev, idx);\n \t\treturn -rte_errno;\n@@ -272,6 +218,19 @@ mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\t.priv = priv,\n \t\t.stats.idx = idx,\n \t\t.socket = socket,\n+\t\t.elts_n = desc,\n+\t\t.elts = elts,\n+\t\t.elts_head = 0,\n+\t\t.elts_tail = 0,\n+\t\t.elts_comp = 0,\n+\t\t/*\n+\t\t * Request send completion every MLX4_PMD_TX_PER_COMP_REQ\n+\t\t * packets or at least 4 times per ring.\n+\t\t */\n+\t\t.elts_comp_cd =\n+\t\t\tRTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),\n+\t\t.elts_comp_cd_init =\n+\t\t\tRTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),\n \t};\n \ttxq->cq = ibv_create_cq(priv->ctx, desc, NULL, NULL, 0);\n \tif (!txq->cq) {\n@@ -314,12 +273,6 @@ mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\t (void *)dev, strerror(rte_errno));\n \t\tgoto error;\n \t}\n-\tret = mlx4_txq_alloc_elts(txq, desc);\n-\tif (ret) {\n-\t\tERROR(\"%p: TXQ allocation failed: %s\",\n-\t\t (void *)dev, strerror(rte_errno));\n-\t\tgoto error;\n-\t}\n \tret = ibv_modify_qp\n \t\t(txq->qp,\n \t\t &(struct ibv_qp_attr){\n", "prefixes": [ "dpdk-dev", "v2", "24/29" ] }