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GET /api/patches/29954/?format=api
{ "id": 29954, "url": "http://patches.dpdk.org/api/patches/29954/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20171009142142.23067-5-akhil.goyal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20171009142142.23067-5-akhil.goyal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20171009142142.23067-5-akhil.goyal@nxp.com", "date": "2017-10-09T14:21:42", "name": "[dpdk-dev,v5,4/4] doc: add NXP DPAA SEC", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b24d427a9490db36337a00d3fa298f732859c4ab", "submitter": { "id": 517, "url": "http://patches.dpdk.org/api/people/517/?format=api", "name": "Akhil Goyal", "email": "akhil.goyal@nxp.com" }, "delegate": { "id": 22, "url": "http://patches.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20171009142142.23067-5-akhil.goyal@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/29954/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/29954/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0C5EB1B204;\n\tMon, 9 Oct 2017 16:24:42 +0200 (CEST)", "from NAM01-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam01on0059.outbound.protection.outlook.com [104.47.34.59])\n\tby dpdk.org (Postfix) with ESMTP id 73C481B1EB\n\tfor <dev@dpdk.org>; Mon, 9 Oct 2017 16:24:35 +0200 (CEST)", "from CY4PR03CA0098.namprd03.prod.outlook.com (10.171.242.167) by\n\tMWHPR03MB2704.namprd03.prod.outlook.com (10.168.207.138) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.77.7; Mon, 9 Oct 2017 14:24:33 +0000", "from BY2FFO11FD045.protection.gbl (2a01:111:f400:7c0c::100) by\n\tCY4PR03CA0098.outlook.office365.com (2603:10b6:910:4d::39) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.77.7 via\n\tFrontend Transport; Mon, 9 Oct 2017 14:24:33 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBY2FFO11FD045.mail.protection.outlook.com (10.1.15.177) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.77.10\n\tvia Frontend Transport; Mon, 9 Oct 2017 14:24:32 +0000", "from netperf2.ap.freescale.net ([10.232.133.164])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv99EOGQb001503; Mon, 9 Oct 2017 07:24:29 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=nxp.com; NXP1.onmicrosoft.com;\n\tdkim=none (message not signed)\n\theader.d=none;NXP1.onmicrosoft.com; dmarc=fail action=none\n\theader.from=nxp.com;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "From": "<akhil.goyal@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<declan.doherty@intel.com>, <pablo.de.lara.guarch@intel.com>,\n\t<hemant.agrawal@nxp.com>, <john.mcnamara@intel.com>", "Date": "Mon, 9 Oct 2017 19:51:42 +0530", "Message-ID": "<20171009142142.23067-5-akhil.goyal@nxp.com>", "X-Mailer": "git-send-email 2.9.3", "In-Reply-To": "<20171009142142.23067-1-akhil.goyal@nxp.com>", "References": "<20171005133323.19886-1-akhil.goyal@nxp.com>\n\t<20171009142142.23067-1-akhil.goyal@nxp.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; 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", "X-Forefront-PRVS": "045584D28C", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Oct 2017 14:24:32.6099\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.158.2]; \n\tHelo=[az84smr01.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR03MB2704", "Subject": "[dpdk-dev] [PATCH v5 4/4] doc: add NXP DPAA SEC", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Akhil Goyal <akhil.goyal@nxp.com>\n\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\nSigned-off-by: Akhil Goyal <akhil.goyal@nxp.com>\nAcked-by: John McNamara <john.mcnamara@intel.com>\n---\n MAINTAINERS | 2 +\n doc/guides/cryptodevs/dpaa_sec.rst | 182 ++++++++++++++++++++++++++++\n doc/guides/cryptodevs/features/dpaa_sec.ini | 40 ++++++\n doc/guides/cryptodevs/index.rst | 1 +\n doc/guides/rel_notes/release_17_11.rst | 6 +\n doc/guides/tools/cryptoperf.rst | 1 +\n 6 files changed, 232 insertions(+)\n create mode 100644 doc/guides/cryptodevs/dpaa_sec.rst\n create mode 100644 doc/guides/cryptodevs/features/dpaa_sec.ini", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex b051892..fb16711 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -556,6 +556,8 @@ NXP DPAA_SEC\n M: Akhil Goyal <akhil.goyal@nxp.com>\n M: Hemant Agrawal <hemant.agrawal@nxp.com>\n F: drivers/crypto/dpaa_sec/\n+F: doc/guides/cryptodevs/dpaa_sec.rst\n+F: doc/guides/cryptodevs/features/dpaa_sec.ini\n \n NXP DPAA2_SEC\n M: Akhil Goyal <akhil.goyal@nxp.com>\ndiff --git a/doc/guides/cryptodevs/dpaa_sec.rst b/doc/guides/cryptodevs/dpaa_sec.rst\nnew file mode 100644\nindex 0000000..d3438cc\n--- /dev/null\n+++ b/doc/guides/cryptodevs/dpaa_sec.rst\n@@ -0,0 +1,182 @@\n+.. BSD LICENSE\n+ Copyright 2017 NXP.\n+\n+ Redistribution and use in source and binary forms, with or without\n+ modification, are permitted provided that the following conditions\n+ are met:\n+\n+ * Redistributions of source code must retain the above copyright\n+ notice, this list of conditions and the following disclaimer.\n+ * Redistributions in binary form must reproduce the above copyright\n+ notice, this list of conditions and the following disclaimer in\n+ the documentation and/or other materials provided with the\n+ distribution.\n+ * Neither the name of NXP nor the names of its\n+ contributors may be used to endorse or promote products derived\n+ from this software without specific prior written permission.\n+\n+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+\n+NXP DPAA CAAM (DPAA_SEC)\n+========================\n+\n+The DPAA_SEC PMD provides poll mode crypto driver support for NXP DPAA CAAM\n+hardware accelerator.\n+\n+Architecture\n+------------\n+\n+SEC is the SOC's security engine, which serves as NXP's latest cryptographic\n+acceleration and offloading hardware. It combines functions previously\n+implemented in separate modules to create a modular and scalable acceleration\n+and assurance engine. It also implements block encryption algorithms, stream\n+cipher algorithms, hashing algorithms, public key algorithms, run-time\n+integrity checking, and a hardware random number generator. SEC performs\n+higher-level cryptographic operations than previous NXP cryptographic\n+accelerators. This provides significant improvement to system level performance.\n+\n+DPAA_SEC is one of the hardware resource in DPAA Architecture. More information\n+on DPAA Architecture is described in :ref:`dpaa_overview`.\n+\n+DPAA_SEC PMD is one of DPAA drivers which interacts with QBMAN to create,\n+configure and destroy the device instance using queue pair with CAAM portal.\n+\n+DPAA_SEC PMD also uses some of the other hardware resources like buffer pools,\n+queues, queue portals to store and to enqueue/dequeue data to the hardware SEC.\n+\n+Implementation\n+--------------\n+\n+SEC provides platform assurance by working with SecMon, which is a companion\n+logic block that tracks the security state of the SOC. SEC is programmed by\n+means of descriptors (not to be confused with frame descriptors (FDs)) that\n+indicate the operations to be performed and link to the message and\n+associated data. SEC incorporates two DMA engines to fetch the descriptors,\n+read the message data, and write the results of the operations. The DMA\n+engine provides a scatter/gather capability so that SEC can read and write\n+data scattered in memory. SEC may be configured by means of software for\n+dynamic changes in byte ordering. The default configuration for this version\n+of SEC is little-endian mode.\n+\n+Features\n+--------\n+\n+The DPAA PMD has support for:\n+\n+Cipher algorithms:\n+\n+* ``RTE_CRYPTO_CIPHER_3DES_CBC``\n+* ``RTE_CRYPTO_CIPHER_AES128_CBC``\n+* ``RTE_CRYPTO_CIPHER_AES192_CBC``\n+* ``RTE_CRYPTO_CIPHER_AES256_CBC``\n+* ``RTE_CRYPTO_CIPHER_AES128_CTR``\n+* ``RTE_CRYPTO_CIPHER_AES192_CTR``\n+* ``RTE_CRYPTO_CIPHER_AES256_CTR``\n+\n+Hash algorithms:\n+\n+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``\n+* ``RTE_CRYPTO_AUTH_MD5_HMAC``\n+\n+AEAD algorithms:\n+\n+* ``RTE_CRYPTO_AEAD_AES_GCM``\n+\n+Supported DPAA SoCs\n+--------------------\n+\n+* LS1046A/LS1026A\n+* LS1043A/LS1023A\n+\n+Limitations\n+-----------\n+\n+* Chained mbufs are not supported.\n+* Hash followed by Cipher mode is not supported\n+* Only supports the session-oriented API implementation (session-less APIs are not supported).\n+\n+Prerequisites\n+-------------\n+\n+DPAA_SEC driver has similar pre-requisites as described in :ref:`dpaa_overview`.\n+The following dependencies are not part of DPDK and must be installed separately:\n+\n+* **NXP Linux SDK**\n+\n+ NXP Linux software development kit (SDK) includes support for the family\n+ of QorIQ® ARM-Architecture-based system on chip (SoC) processors\n+ and corresponding boards.\n+\n+ It includes the Linux board support packages (BSPs) for NXP SoCs,\n+ a fully operational tool chain, kernel and board specific modules.\n+\n+ SDK and related information can be obtained from: `NXP QorIQ SDK <http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX>`_.\n+\n+* **DPDK Extras Scripts**\n+\n+ DPAA based resources can be configured easily with the help of ready scripts\n+ as provided in the DPDK Extras repository.\n+\n+ `DPDK Extras Scripts <https://github.com/qoriq-open-source/dpdk-extras>`_.\n+\n+Currently supported by DPDK:\n+\n+* NXP SDK **2.0+**.\n+* Supported architectures: **arm64 LE**.\n+\n+* Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment.\n+\n+Pre-Installation Configuration\n+------------------------------\n+\n+Config File Options\n+~~~~~~~~~~~~~~~~~~~\n+\n+Basic DPAA config file options are described in :ref:`dpaa_overview`.\n+In addition to those, the following options can be modified in the ``config`` file\n+to enable DPAA_SEC PMD.\n+\n+Please note that enabling debugging options may affect system performance.\n+\n+* ``CONFIG_RTE_LIBRTE_PMD_DPAA_SEC`` (default ``n``)\n+ By default it is only enabled in defconfig_arm64-dpaa-* config.\n+ Toggle compilation of the ``librte_pmd_dpaa_sec`` driver.\n+\n+* ``CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_INIT`` (default ``n``)\n+ Toggle display of initialization related driver messages\n+\n+* ``CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_DRIVER`` (default ``n``)\n+ Toggle display of driver runtime messages\n+\n+* ``CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_RX`` (default ``n``)\n+ Toggle display of receive fast path run-time message\n+\n+* ``CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS``\n+ By default it is set as 2048 in defconfig_arm64-dpaa-* config.\n+ It indicates Number of sessions to create in the session memory pool\n+ on a single DPAA SEC device.\n+\n+Installations\n+-------------\n+To compile the DPAA_SEC PMD for Linux arm64 gcc target, run the\n+following ``make`` command:\n+\n+.. code-block:: console\n+\n+ cd <DPDK-source-directory>\n+ make config T=arm64-dpaa-linuxapp-gcc install\ndiff --git a/doc/guides/cryptodevs/features/dpaa_sec.ini b/doc/guides/cryptodevs/features/dpaa_sec.ini\nnew file mode 100644\nindex 0000000..0e8f5b2\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/dpaa_sec.ini\n@@ -0,0 +1,40 @@\n+;\n+; Supported features of the 'dpaa_sec' crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Symmetric crypto = Y\n+Sym operation chaining = Y\n+HW Accelerated = Y\n+\n+;\n+; Supported crypto algorithms of the 'dpaa_sec' crypto driver.\n+;\n+[Cipher]\n+AES CBC (128) = Y\n+AES CBC (192) = Y\n+AES CBC (256) = Y\n+AES CTR (128) = Y\n+AES CTR (192) = Y\n+AES CTR (256) = Y\n+3DES CBC = Y\n+\n+;\n+; Supported authentication algorithms of the 'dpaa_sec' crypto driver.\n+;\n+[Auth]\n+MD5 HMAC = Y\n+SHA1 HMAC = Y\n+SHA224 HMAC = Y\n+SHA256 HMAC = Y\n+SHA384 HMAC = Y\n+SHA512 HMAC = Y\n+\n+;\n+; Supported AEAD algorithms of the 'dpaa_sec' crypto driver.\n+;\n+[AEAD]\n+AES GCM (128) = Y\n+AES GCM (192) = Y\n+AES GCM (256) = Y\ndiff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst\nindex 361b82d..3a39a2d 100644\n--- a/doc/guides/cryptodevs/index.rst\n+++ b/doc/guides/cryptodevs/index.rst\n@@ -40,6 +40,7 @@ Crypto Device Drivers\n aesni_gcm\n armv8\n dpaa2_sec\n+ dpaa_sec\n kasumi\n openssl\n null\ndiff --git a/doc/guides/rel_notes/release_17_11.rst b/doc/guides/rel_notes/release_17_11.rst\nindex f133ebf..f452f0b 100644\n--- a/doc/guides/rel_notes/release_17_11.rst\n+++ b/doc/guides/rel_notes/release_17_11.rst\n@@ -116,6 +116,12 @@ New Features\n that displays more detailed breakdown of CPU cycles used by hardware\n acceleration.\n \n+* **Added NXP DPAA SEC crypto PMD.**\n+\n+ A new \"dpaa_sec\" hardware based crypto PMD for NXP DPAA devices has been\n+ added. See the \"Crypto Device Drivers\" document for more details on this\n+ driver.\n+\n \n Resolved Issues\n ---------------\ndiff --git a/doc/guides/tools/cryptoperf.rst b/doc/guides/tools/cryptoperf.rst\nindex d587c20..2b3a5b6 100644\n--- a/doc/guides/tools/cryptoperf.rst\n+++ b/doc/guides/tools/cryptoperf.rst\n@@ -190,6 +190,7 @@ The following are the appication command-line options:\n crypto_snow3g\n crypto_kasumi\n crypto_zuc\n+ crypto_dpaa_sec\n crypto_dpaa2_sec\n crypto_armv8\n crypto_scheduler\n", "prefixes": [ "dpdk-dev", "v5", "4/4" ] }