Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/28753/?format=api
{ "id": 28753, "url": "http://patches.dpdk.org/api/patches/28753/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1505445188-70251-2-git-send-email-wei.zhao1@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1505445188-70251-2-git-send-email-wei.zhao1@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1505445188-70251-2-git-send-email-wei.zhao1@intel.com", "date": "2017-09-15T03:13:07", "name": "[dpdk-dev,v3,1/2] net/i40e: queue region set and flush", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2d3d267e2d7061592e5a686f1b669e5997161748", "submitter": { "id": 495, "url": "http://patches.dpdk.org/api/people/495/?format=api", "name": "Zhao1, Wei", "email": "wei.zhao1@intel.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1505445188-70251-2-git-send-email-wei.zhao1@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/28753/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/28753/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B2D067D4E;\n\tFri, 15 Sep 2017 05:24:06 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 8F09D2FDD\n\tfor <dev@dpdk.org>; Fri, 15 Sep 2017 05:24:03 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t14 Sep 2017 20:24:03 -0700", "from dpdk4.bj.intel.com ([172.16.182.85])\n\tby orsmga003.jf.intel.com with ESMTP; 14 Sep 2017 20:24:02 -0700" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,396,1500966000\"; d=\"scan'208\";\n\ta=\"1014658781\"", "From": "Wei Zhao <wei.zhao1@intel.com>", "To": "dev@dpdk.org", "Cc": "Wei Zhao <wei.zhao1@intel.com>", "Date": "Fri, 15 Sep 2017 11:13:07 +0800", "Message-Id": "<1505445188-70251-2-git-send-email-wei.zhao1@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505445188-70251-1-git-send-email-wei.zhao1@intel.com>", "References": "<1505282644-40415-1-git-send-email-wei.zhao1@intel.com>\n\t<1505445188-70251-1-git-send-email-wei.zhao1@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 1/2] net/i40e: queue region set and flush", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This feature enable queue regions configuration for RSS in PF/VF,\nso that different traffic classes or different packet\nclassification types can be separated to different queues in\ndifferent queue regions.This patch can set queue region range,\nit include queue number in a region and the index of first queue.\nThis patch enable mapping between different priorities (UP) and\ndifferent traffic classes.It also enable mapping between a region\nindex and a sepcific flowtype(PCTYPE).It also provide the solution\nof flush all configuration about queue region the above described.\n\nSigned-off-by: Wei Zhao <wei.zhao1@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 19 +-\n drivers/net/i40e/i40e_ethdev.h | 30 ++\n drivers/net/i40e/rte_pmd_i40e.c | 482 ++++++++++++++++++++++++++++++\n drivers/net/i40e/rte_pmd_i40e.h | 38 +++\n drivers/net/i40e/rte_pmd_i40e_version.map | 1 +\n 5 files changed, 566 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 8e0580c..1663fc0 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -137,10 +137,6 @@\n #define I40E_PRTTSYN_TSYNTYPE 0x0e000000\n #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL\n \n-#define I40E_MAX_PERCENT 100\n-#define I40E_DEFAULT_DCB_APP_NUM 1\n-#define I40E_DEFAULT_DCB_APP_PRIO 3\n-\n /**\n * Below are values for writing un-exposed registers suggested\n * by silicon experts\n@@ -1034,6 +1030,15 @@ i40e_init_fdir_filter_list(struct rte_eth_dev *dev)\n \treturn ret;\n }\n \n+static void\n+i40e_init_queue_region_conf(struct rte_eth_dev *dev)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct i40e_queue_region_info *info = &pf->queue_region;\n+\n+\tmemset(info, 0, sizeof(struct i40e_queue_region_info));\n+}\n+\n static int\n eth_i40e_dev_init(struct rte_eth_dev *dev)\n {\n@@ -1309,6 +1314,9 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \tif (ret < 0)\n \t\tgoto err_init_fdir_filter_list;\n \n+\t/* initialize queue region configuration */\n+\ti40e_init_queue_region_conf(dev);\n+\n \treturn 0;\n \n err_init_fdir_filter_list:\n@@ -1464,6 +1472,9 @@ eth_i40e_dev_uninit(struct rte_eth_dev *dev)\n \t/* Remove all Traffic Manager configuration */\n \ti40e_tm_conf_uninit(dev);\n \n+\t/* Remove all the queue region configuration */\n+\ti40e_flush_region_all_conf(hw, pf, 0);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex ad80f0f..d612886 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -260,6 +260,16 @@ enum i40e_flxpld_layer_idx {\n #define I40E_QOS_BW_WEIGHT_MIN 1\n /* The max bandwidth weight is 127. */\n #define I40E_QOS_BW_WEIGHT_MAX 127\n+/* The max queue region index is 7. */\n+#define I40E_REGION_MAX_INDEX 7\n+/* The max queue region userpriority is 7. */\n+#define I40E_REGION_USERPRIORITY_MAX_INDEX 7\n+/* The max pctype index is 63. */\n+#define I40E_REGION_PCTYPE_MAX_INDEX 63\n+\n+#define I40E_MAX_PERCENT 100\n+#define I40E_DEFAULT_DCB_APP_NUM 1\n+#define I40E_DEFAULT_DCB_APP_PRIO 3\n \n /**\n * The overhead from MTU to max frame size.\n@@ -541,6 +551,22 @@ struct i40e_ethertype_rule {\n \tstruct rte_hash *hash_table;\n };\n \n+/* queue region info */\n+struct i40e_region_info {\n+\tuint8_t region_id;\n+\tuint8_t queue_start_index;\n+\tuint8_t queue_num;\n+\tuint8_t user_priority_num;\n+\tuint8_t user_priority[I40E_MAX_USER_PRIORITY];\n+\tuint8_t flowtype_num;\n+\tuint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];\n+};\n+\n+struct i40e_queue_region_info {\n+\tuint16_t queue_region_number;\n+\tstruct i40e_region_info region[I40E_REGION_MAX_INDEX + 1];\n+};\n+\n /* Tunnel filter number HW supports */\n #define I40E_MAX_TUNNEL_FILTER_NUM 400\n \n@@ -776,6 +802,7 @@ struct i40e_pf {\n \tstruct i40e_fdir_info fdir; /* flow director info */\n \tstruct i40e_ethertype_rule ethertype; /* Ethertype filter rule */\n \tstruct i40e_tunnel_rule tunnel; /* Tunnel filter rule */\n+\tstruct i40e_queue_region_info queue_region; /* queue region info */\n \tstruct i40e_fc_conf fc_conf; /* Flow control conf */\n \tstruct i40e_mirror_rule_list mirror_list;\n \tuint16_t nb_mirror_rule; /* The number of mirror rules */\n@@ -1003,6 +1030,9 @@ void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);\n int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);\n void i40e_tm_conf_init(struct rte_eth_dev *dev);\n void i40e_tm_conf_uninit(struct rte_eth_dev *dev);\n+int i40e_flush_region_all_conf(struct i40e_hw *hw,\n+\t\t\t\tstruct i40e_pf *pf, uint16_t on);\n+\n \n #define I40E_DEV_TO_PCI(eth_dev) \\\n \tRTE_DEV_TO_PCI((eth_dev)->device)\ndiff --git a/drivers/net/i40e/rte_pmd_i40e.c b/drivers/net/i40e/rte_pmd_i40e.c\nindex d69a472..9a75f21 100644\n--- a/drivers/net/i40e/rte_pmd_i40e.c\n+++ b/drivers/net/i40e/rte_pmd_i40e.c\n@@ -35,6 +35,7 @@\n #include <rte_tailq.h>\n \n #include \"base/i40e_prototype.h\"\n+#include \"base/i40e_dcb.h\"\n #include \"i40e_ethdev.h\"\n #include \"i40e_pf.h\"\n #include \"i40e_rxtx.h\"\n@@ -2161,3 +2162,484 @@ rte_pmd_i40e_add_vf_mac_addr(uint8_t port, uint16_t vf_id,\n \n \treturn 0;\n }\n+\n+static int\n+i40e_vsi_update_queue_region_mapping(struct i40e_hw *hw,\n+\t\t\t struct i40e_pf *pf)\n+{\n+\tuint16_t i;\n+\tstruct i40e_vsi *vsi = pf->main_vsi;\n+\tuint16_t queue_offset, bsf, tc_index;\n+\tstruct i40e_vsi_context ctxt;\n+\tstruct i40e_aqc_vsi_properties_data *vsi_info;\n+\tstruct i40e_queue_region_info *region_info =\n+\t\t\t\t&pf->queue_region;\n+\tuint32_t ret = -EINVAL;\n+\n+\tif (!region_info->queue_region_number) {\n+\t\tPMD_INIT_LOG(ERR, \"there is no that region id been set before\");\n+\t\treturn ret;\n+\t}\n+\n+\tmemset(&ctxt, 0, sizeof(struct i40e_vsi_context));\n+\n+\t/* Update Queue Pairs Mapping for currently enabled UPs */\n+\tctxt.seid = vsi->seid;\n+\tctxt.pf_num = hw->pf_id;\n+\tctxt.vf_num = 0;\n+\tctxt.uplink_seid = vsi->uplink_seid;\n+\tctxt.info = vsi->info;\n+\tvsi_info = &ctxt.info;\n+\n+\tmemset(vsi_info->tc_mapping, 0, sizeof(uint16_t) * 8);\n+\tmemset(vsi_info->queue_mapping, 0, sizeof(uint16_t) * 16);\n+\n+\t/**\n+\t * Configure queue region and queue mapping parameters,\n+\t * for enabled queue region, allocate queues to this region.\n+\t */\n+\n+\tfor (i = 0; i < region_info->queue_region_number; i++) {\n+\t\ttc_index = region_info->region[i].region_id;\n+\t\tbsf = rte_bsf32(region_info->region[i].queue_num);\n+\t\tqueue_offset = region_info->region[i].queue_start_index;\n+\t\tvsi_info->tc_mapping[tc_index] = rte_cpu_to_le_16(\n+\t\t\t(queue_offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |\n+\t\t\t\t(bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));\n+\t}\n+\n+\t/* Associate queue number with VSI, Keep vsi->nb_qps unchanged */\n+\tif (vsi->type == I40E_VSI_SRIOV) {\n+\t\tvsi_info->mapping_flags |=\n+\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);\n+\t\tfor (i = 0; i < vsi->nb_qps; i++)\n+\t\t\tvsi_info->queue_mapping[i] =\n+\t\t\t\trte_cpu_to_le_16(vsi->base_queue + i);\n+\t} else {\n+\t\tvsi_info->mapping_flags |=\n+\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);\n+\t\tvsi_info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);\n+\t}\n+\tvsi_info->valid_sections |=\n+\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);\n+\n+\t/* Update the VSI after updating the VSI queue-mapping information */\n+\tret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to configure queue region \"\n+\t\t\t\"mapping = %d \", hw->aq.asq_last_status);\n+\t\treturn ret;\n+\t}\n+\t/* update the local VSI info with updated queue map */\n+\t(void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,\n+\t\t\t\t\tsizeof(vsi->info.tc_mapping));\n+\t(void)rte_memcpy(&vsi->info.queue_mapping,\n+\t\t\t&ctxt.info.queue_mapping,\n+\t\tsizeof(vsi->info.queue_mapping));\n+\tvsi->info.mapping_flags = ctxt.info.mapping_flags;\n+\tvsi->info.valid_sections = 0;\n+\n+\treturn 0;\n+}\n+\n+\n+static int\n+i40e_set_queue_region(struct i40e_pf *pf,\n+\t\t\t\tstruct rte_i40e_rss_region_conf *conf_ptr)\n+{\n+\tuint16_t tc_size_tb[7] = {1, 2, 4, 8, 16, 32, 64};\n+\tuint16_t i;\n+\tstruct i40e_vsi *main_vsi = pf->main_vsi;\n+\tstruct i40e_queue_region_info *info = &pf->queue_region;\n+\tuint32_t ret = -EINVAL;\n+\n+\tfor (i = 0; i < I40E_REGION_MAX_INDEX; i++)\n+\t\tif (conf_ptr->queue_num == tc_size_tb[i])\n+\t\t\tbreak;\n+\n+\tif (i == I40E_REGION_MAX_INDEX) {\n+\t\tprintf(\"The region sizes should be any of the following \"\n+\t\t\"values: 1, 2, 4, 8, 16, 32, 64 as long as the \"\n+\t\t\"total number of queues do not exceed the VSI allocation\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (conf_ptr->region_id >= I40E_REGION_MAX_INDEX) {\n+\t\tPMD_INIT_LOG(ERR, \"the queue region max index is 7\");\n+\t\treturn ret;\n+\t}\n+\n+\tif ((conf_ptr->queue_start_index + conf_ptr->queue_num)\n+\t\t\t\t\t> main_vsi->nb_used_qps) {\n+\t\tPMD_INIT_LOG(ERR, \"the queue index exceeds the VSI range\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (info->queue_region_number) {\n+\t\tfor (i = 0; i < info->queue_region_number; i++)\n+\t\t\tif (conf_ptr->region_id == info->region[i].region_id)\n+\t\t\t\tbreak;\n+\n+\t\tif ((i == info->queue_region_number) &&\n+\t\t\t(i <= I40E_REGION_MAX_INDEX)) {\n+\t\t\tinfo->region[i].region_id = conf_ptr->region_id;\n+\t\t\tinfo->region[i].queue_num = conf_ptr->queue_num;\n+\t\t\tinfo->region[i].queue_start_index =\n+\t\t\t\tconf_ptr->queue_start_index;\n+\t\t\tinfo->queue_region_number++;\n+\t\t} else {\n+\t\t\tPMD_INIT_LOG(ERR, \"queue region number \"\n+\t\t\t\t\"exceeds maxnum 8 or the \"\n+\t\t\t\t\"queue region id has \"\n+\t\t\t\t\"been set before\");\n+\t\t\treturn ret;\n+\t\t}\n+\t} else {\n+\t\tinfo->region[0].region_id = conf_ptr->region_id;\n+\t\tinfo->region[0].queue_num = conf_ptr->queue_num;\n+\t\tinfo->region[0].queue_start_index =\n+\t\t\tconf_ptr->queue_start_index;\n+\t\tinfo->queue_region_number++;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_set_region_flowtype_pf(struct i40e_hw *hw,\n+\t\tstruct i40e_pf *pf, struct rte_i40e_rss_region_conf *conf_ptr)\n+{\n+\tuint32_t pfqf_hregion;\n+\tuint32_t ret = -EINVAL;\n+\tstruct i40e_queue_region_info *info = &pf->queue_region;\n+\tuint16_t i, j, index, flowtype_set = 0;\n+\tuint16_t region_index, flowtype_index;\n+\n+\tif (conf_ptr->region_id > I40E_PFQF_HREGION_MAX_INDEX) {\n+\t\tPMD_INIT_LOG(ERR, \"the queue region max index is 7\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (conf_ptr->hw_flowtype >= I40E_FILTER_PCTYPE_MAX) {\n+\t\tPMD_INIT_LOG(ERR, \"the hw_flowtype or PCTYPE max index is 63\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (info->queue_region_number) {\n+\t\tfor (i = 0; i < info->queue_region_number; i++)\n+\t\t\tif (conf_ptr->region_id == info->region[i].region_id)\n+\t\t\t\tbreak;\n+\n+\t\tif (i == info->queue_region_number) {\n+\t\t\tPMD_INIT_LOG(ERR, \"that region id has not \"\n+\t\t\t\t\"been set before\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tregion_index = i;\n+\n+\t\tfor (i = 0; i < info->queue_region_number; i++) {\n+\t\t\tfor (j = 0; j < info->region[i].flowtype_num; j++) {\n+\t\t\t\tif (conf_ptr->hw_flowtype ==\n+\t\t\t\t\tinfo->region[i].hw_flowtype[j]) {\n+\t\t\t\t\tflowtype_set = 1;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (flowtype_set) {\n+\t\t\tPMD_INIT_LOG(ERR, \"that hw_flowtype \"\n+\t\t\t\t\"has been set before\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tflowtype_index = info->region[region_index].flowtype_num;\n+\t\tinfo->region[region_index].hw_flowtype[flowtype_index] =\n+\t\t\t\t\t\tconf_ptr->hw_flowtype;\n+\t\tinfo->region[region_index].flowtype_num++;\n+\t} else {\n+\t\tPMD_INIT_LOG(ERR, \"there is no that region id been set before\");\n+\t\treturn ret;\n+\t}\n+\n+\tindex = conf_ptr->hw_flowtype >> 3;\n+\tpfqf_hregion = i40e_read_rx_ctl(hw, I40E_PFQF_HREGION(index));\n+\n+\tif ((conf_ptr->hw_flowtype & 0x7) == 0) {\n+\t\tpfqf_hregion |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_0_SHIFT;\n+\t\tpfqf_hregion |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT;\n+\t} else if ((conf_ptr->hw_flowtype & 0x7) == 1) {\n+\t\tpfqf_hregion |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_1_SHIFT;\n+\t\tpfqf_hregion |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT;\n+\t} else if ((conf_ptr->hw_flowtype & 0x7) == 2) {\n+\t\tpfqf_hregion |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_2_SHIFT;\n+\t\tpfqf_hregion |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT;\n+\t} else if ((conf_ptr->hw_flowtype & 0x7) == 3) {\n+\t\tpfqf_hregion |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_3_SHIFT;\n+\t\tpfqf_hregion |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT;\n+\t} else if ((conf_ptr->hw_flowtype & 0x7) == 4) {\n+\t\tpfqf_hregion |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_4_SHIFT;\n+\t\tpfqf_hregion |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT;\n+\t} else if ((conf_ptr->hw_flowtype & 0x7) == 5) {\n+\t\tpfqf_hregion |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_5_SHIFT;\n+\t\tpfqf_hregion |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT;\n+\t} else if ((conf_ptr->hw_flowtype & 0x7) == 6) {\n+\t\tpfqf_hregion |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_6_SHIFT;\n+\t\tpfqf_hregion |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT;\n+\t} else {\n+\t\tpfqf_hregion |= conf_ptr->region_id <<\n+\t\t\t\tI40E_PFQF_HREGION_REGION_7_SHIFT;\n+\t\tpfqf_hregion |= 1 << I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT;\n+\t}\n+\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HREGION(index), pfqf_hregion);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_set_up_region(struct i40e_pf *pf,\n+\t\t\t\tstruct rte_i40e_rss_region_conf *conf_ptr)\n+{\n+\tstruct i40e_queue_region_info *info = &pf->queue_region;\n+\tuint32_t ret = -EINVAL;\n+\tuint16_t i, j, region_index, up_set = 0;\n+\n+\tif (conf_ptr->user_priority > I40E_REGION_USERPRIORITY_MAX_INDEX) {\n+\t\tPMD_INIT_LOG(ERR, \"the queue region max index is 7\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (conf_ptr->region_id >= I40E_REGION_MAX_INDEX) {\n+\t\tPMD_INIT_LOG(ERR, \"the region_id max index is 7\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (info->queue_region_number) {\n+\t\tfor (i = 0; i < info->queue_region_number; i++)\n+\t\t\tif (conf_ptr->region_id == info->region[i].region_id)\n+\t\t\t\tbreak;\n+\n+\t\tif (i == info->queue_region_number) {\n+\t\t\tPMD_INIT_LOG(ERR, \"that region id \"\n+\t\t\t\t\"has not been set before\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tregion_index = i;\n+\n+\t\tfor (i = 0; i < info->queue_region_number; i++) {\n+\t\t\tfor (j = 0; j <\n+\t\t\t\tinfo->region[i].user_priority_num; j++) {\n+\t\t\t\tif (info->region[i].user_priority[j] ==\n+\t\t\t\t\tconf_ptr->user_priority) {\n+\t\t\t\t\tup_set = 1;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (up_set) {\n+\t\t\tPMD_INIT_LOG(ERR, \"that user priority \"\n+\t\t\t\t\"has been set before\");\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tj = info->region[region_index].user_priority_num;\n+\t\tinfo->region[region_index].user_priority[j] =\n+\t\t\t\t\t\tconf_ptr->user_priority;\n+\t\tinfo->region[region_index].user_priority_num++;\n+\t} else {\n+\t\tPMD_INIT_LOG(ERR, \"there is no that region id been set before\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_queue_region_dcb_configure(struct i40e_hw *hw,\n+\t\t\t\tstruct i40e_pf *pf)\n+{\n+\tstruct i40e_dcbx_config dcb_cfg_local;\n+\tstruct i40e_dcbx_config *dcb_cfg;\n+\tstruct i40e_queue_region_info *info = &pf->queue_region;\n+\tstruct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;\n+\tuint32_t ret = -EINVAL;\n+\tuint16_t i, j, prio_index, region_index;\n+\tuint8_t tc_map, tc_bw, bw_lf;\n+\n+\tif (!info->queue_region_number) {\n+\t\tPMD_INIT_LOG(ERR, \"there is no that region id been set before\");\n+\t\treturn ret;\n+\t}\n+\n+\tdcb_cfg = &dcb_cfg_local;\n+\tmemset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));\n+\n+\t/* assume each tc has the same bw */\n+\ttc_bw = I40E_MAX_PERCENT / info->queue_region_number;\n+\tfor (i = 0; i < info->queue_region_number; i++)\n+\t\tdcb_cfg->etscfg.tcbwtable[i] = tc_bw;\n+\t/* to ensure the sum of tcbw is equal to 100 */\n+\tbw_lf = I40E_MAX_PERCENT % info->queue_region_number;\n+\tfor (i = 0; i < bw_lf; i++)\n+\t\tdcb_cfg->etscfg.tcbwtable[i]++;\n+\n+\t/* assume each tc has the same Transmission Selection Algorithm */\n+\tfor (i = 0; i < info->queue_region_number; i++)\n+\t\tdcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;\n+\n+\tfor (i = 0; i < info->queue_region_number; i++) {\n+\t\tfor (j = 0; j < info->region[i].user_priority_num; j++) {\n+\t\t\tprio_index = info->region[i].user_priority[j];\n+\t\t\tregion_index = info->region[i].region_id;\n+\t\t\tdcb_cfg->etscfg.prioritytable[prio_index] =\n+\t\t\t\t\t\tregion_index;\n+\t\t}\n+\t}\n+\n+\t/* FW needs one App to configure HW */\n+\tdcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;\n+\tdcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;\n+\tdcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;\n+\tdcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;\n+\n+\ttc_map = RTE_LEN2MASK(info->queue_region_number, uint8_t);\n+\n+\tdcb_cfg->pfc.willing = 0;\n+\tdcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;\n+\tdcb_cfg->pfc.pfcenable = tc_map;\n+\n+\t/* Copy the new config to the current config */\n+\t*old_cfg = *dcb_cfg;\n+\told_cfg->etsrec = old_cfg->etscfg;\n+\tret = i40e_set_dcb_config(hw);\n+\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Set queue region DCB Config failed, err\"\n+\t\t\t\" %s aq_err %s\",\n+\t\t\t i40e_stat_str(hw, ret),\n+\t\t\t i40e_aq_str(hw, hw->aq.asq_last_status));\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_queue_region_dcb_configure_default(struct i40e_hw *hw)\n+{\n+\tuint16_t i;\n+\tuint32_t ret = -EINVAL;\n+\n+\tmemset(&hw->local_dcbx_config, 0,\n+\tsizeof(struct i40e_dcbx_config));\n+\t/* set dcb default configuration */\n+\thw->local_dcbx_config.etscfg.willing = 0;\n+\thw->local_dcbx_config.etscfg.maxtcs = 0;\n+\thw->local_dcbx_config.etscfg.tcbwtable[0] = 100;\n+\thw->local_dcbx_config.etscfg.tsatable[0] =\n+\t\t\tI40E_IEEE_TSA_ETS;\n+\t/* all UPs mapping to region 0 */\n+\tfor (i = 0; i < I40E_MAX_USER_PRIORITY; i++)\n+\t\thw->local_dcbx_config.etscfg.prioritytable[i] = 0;\n+\thw->local_dcbx_config.etsrec =\n+\t\thw->local_dcbx_config.etscfg;\n+\thw->local_dcbx_config.pfc.willing = 0;\n+\thw->local_dcbx_config.pfc.pfccap =\n+\t\t\tI40E_MAX_TRAFFIC_CLASS;\n+\t/* FW needs one App to configure HW */\n+\thw->local_dcbx_config.numapps = 1;\n+\thw->local_dcbx_config.app[0].selector =\n+\t\t\tI40E_APP_SEL_ETHTYPE;\n+\thw->local_dcbx_config.app[0].priority = 3;\n+\thw->local_dcbx_config.app[0].protocolid =\n+\t\t\tI40E_APP_PROTOID_FCOE;\n+\tret = i40e_set_dcb_config(hw);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\"default dcb config fails. err = %d, aq_err = %d.\",\n+\t\t\tret, hw->aq.asq_last_status);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+i40e_flush_region_all_conf(struct i40e_hw *hw, struct i40e_pf *pf,\n+\t\t\t\tuint16_t on)\n+{\n+\tuint16_t i;\n+\tstruct i40e_queue_region_info *info = &pf->queue_region;\n+\n+\tif (on) {\n+\t\ti40e_vsi_update_queue_region_mapping(hw, pf);\n+\t\ti40e_queue_region_dcb_configure(hw, pf);\n+\t\treturn 0;\n+\t}\n+\n+\tinfo->queue_region_number = 1;\n+\tinfo->region[0].queue_num = 64;\n+\tinfo->region[0].queue_start_index = 0;\n+\n+\ti40e_vsi_update_queue_region_mapping(hw, pf);\n+\ti40e_queue_region_dcb_configure_default(hw);\n+\n+\tfor (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)\n+\t\ti40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);\n+\n+\tmemset(info, 0, sizeof(struct i40e_queue_region_info));\n+\n+\treturn 0;\n+}\n+\n+int rte_pmd_i40e_queue_region_conf(uint8_t port,\n+\t\t\tstruct rte_i40e_rss_region_conf *conf_ptr)\n+{\n+\tstruct rte_eth_dev *dev = &rte_eth_devices[port];\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tenum rte_pmd_i40e_queue_region_op op_type = conf_ptr->op;\n+\tuint32_t ret;\n+\n+\tif (!is_i40e_supported(dev))\n+\t\treturn -ENOTSUP;\n+\n+\tswitch (op_type) {\n+\tcase RTE_PMD_I40E_QUEUE_REGION_SET:\n+\t\tret = i40e_set_queue_region(pf, conf_ptr);\n+\t\tbreak;\n+\tcase RTE_PMD_I40E_REGION_FLOWTYPE_PF_SET:\n+\t\tret = i40e_set_region_flowtype_pf(hw, pf, conf_ptr);\n+\t\tbreak;\n+\tcase RTE_PMD_I40E_REGION_FLOWTYPE_VF_SET:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\tcase RTE_PMD_I40E_UP_REGION_SET:\n+\t\tret = i40e_set_up_region(pf, conf_ptr);\n+\t\tbreak;\n+\tcase RTE_PMD_I40E_REGION_ALL_FLUSH_ON:\n+\t\tret = i40e_flush_region_all_conf(hw, pf, 1);\n+\t\tbreak;\n+\tcase RTE_PMD_I40E_REGION_ALL_FLUSH_OFF:\n+\t\tret = i40e_flush_region_all_conf(hw, pf, 0);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tPMD_DRV_LOG(WARNING, \"op type (%d) not supported\",\n+\t\t\t op_type);\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn ret;\n+}\ndiff --git a/drivers/net/i40e/rte_pmd_i40e.h b/drivers/net/i40e/rte_pmd_i40e.h\nindex 155b7e8..a1329f4 100644\n--- a/drivers/net/i40e/rte_pmd_i40e.h\n+++ b/drivers/net/i40e/rte_pmd_i40e.h\n@@ -91,6 +91,20 @@ enum rte_pmd_i40e_package_info {\n \tRTE_PMD_I40E_PKG_INFO_MAX = 0xFFFFFFFF\n };\n \n+/**\n+ * Option types of queue region.\n+ */\n+enum rte_pmd_i40e_queue_region_op {\n+\tRTE_PMD_I40E_REGION_UNDEFINED = 0,\n+\tRTE_PMD_I40E_QUEUE_REGION_SET, /**< add queue region set*/\n+\tRTE_PMD_I40E_REGION_FLOWTYPE_PF_SET, /**< add pf region pctype set */\n+\tRTE_PMD_I40E_REGION_FLOWTYPE_VF_SET, /**< add vf region pctype set */\n+\tRTE_PMD_I40E_UP_REGION_SET, /**< add queue region pctype set */\n+\tRTE_PMD_I40E_REGION_ALL_FLUSH_ON, /**< flush on all configuration */\n+\tRTE_PMD_I40E_REGION_ALL_FLUSH_OFF, /**< flush off all configuration */\n+\tRTE_PMD_I40E_QUEUE_REGION_OP_MAX\n+};\n+\n #define RTE_PMD_I40E_DDP_NAME_SIZE 32\n \n /**\n@@ -146,6 +160,18 @@ struct rte_pmd_i40e_ptype_mapping {\n };\n \n /**\n+ * Queue region information get from CLI.\n+ */\n+struct rte_i40e_rss_region_conf {\n+\tuint8_t region_id;\n+\tuint8_t hw_flowtype;\n+\tuint8_t queue_start_index;\n+\tuint8_t queue_num;\n+\tuint8_t user_priority;\n+\tenum rte_pmd_i40e_queue_region_op op;\n+};\n+\n+/**\n * Notify VF when PF link status changes.\n *\n * @param port\n@@ -657,4 +683,16 @@ int rte_pmd_i40e_ptype_mapping_replace(uint8_t port,\n int rte_pmd_i40e_add_vf_mac_addr(uint8_t port, uint16_t vf_id,\n \t\t\t\t struct ether_addr *mac_addr);\n \n+/**\n+ * Get RSS queue region info from CLI and do configuration for\n+ * that port as the command otion type\n+ *\n+ * @param port\n+ * pointer to port identifier of the device\n+ * @param conf_ptr\n+ * pointer to the struct that contain all the\n+ * region configuration parameters\n+ */\n+int rte_pmd_i40e_queue_region_conf(uint8_t port,\n+\t\tstruct rte_i40e_rss_region_conf *conf_ptr);\n #endif /* _PMD_I40E_H_ */\ndiff --git a/drivers/net/i40e/rte_pmd_i40e_version.map b/drivers/net/i40e/rte_pmd_i40e_version.map\nindex ef8882b..c3ee2da 100644\n--- a/drivers/net/i40e/rte_pmd_i40e_version.map\n+++ b/drivers/net/i40e/rte_pmd_i40e_version.map\n@@ -50,5 +50,6 @@ DPDK_17.11 {\n \tglobal:\n \n \trte_pmd_i40e_add_vf_mac_addr;\n+\trte_pmd_i40e_queue_region_conf;\n \n } DPDK_17.08;\n", "prefixes": [ "dpdk-dev", "v3", "1/2" ] }