get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/28480/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 28480,
    "url": "http://patches.dpdk.org/api/patches/28480/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1504860327-18451-4-git-send-email-hemant.agrawal@nxp.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1504860327-18451-4-git-send-email-hemant.agrawal@nxp.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1504860327-18451-4-git-send-email-hemant.agrawal@nxp.com",
    "date": "2017-09-08T08:45:00",
    "name": "[dpdk-dev,v2,03/30] bus/fslmc: add qbman API to do enqueue with multiple frames",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "889a2d7690041a421237f98ff2c963de9929a8b4",
    "submitter": {
        "id": 477,
        "url": "http://patches.dpdk.org/api/people/477/?format=api",
        "name": "Hemant Agrawal",
        "email": "hemant.agrawal@nxp.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1504860327-18451-4-git-send-email-hemant.agrawal@nxp.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/28480/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/28480/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 068DC199BE;\n\tFri,  8 Sep 2017 10:46:02 +0200 (CEST)",
            "from NAM02-CY1-obe.outbound.protection.outlook.com\n\t(mail-cys01nam02on0064.outbound.protection.outlook.com\n\t[104.47.37.64]) by dpdk.org (Postfix) with ESMTP id C0ACE237\n\tfor <dev@dpdk.org>; Fri,  8 Sep 2017 10:45:58 +0200 (CEST)",
            "from CY4PR03CA0006.namprd03.prod.outlook.com (10.168.162.16) by\n\tCY1PR03MB2266.namprd03.prod.outlook.com (10.166.207.18) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.13.10; Fri, 8 Sep 2017 08:45:57 +0000",
            "from BY2FFO11FD011.protection.gbl (2a01:111:f400:7c0c::148) by\n\tCY4PR03CA0006.outlook.office365.com (2603:10b6:903:33::16) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.35.12 via\n\tFrontend Transport; Fri, 8 Sep 2017 08:45:57 +0000",
            "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBY2FFO11FD011.mail.protection.outlook.com (10.1.14.129) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1385.11\n\tvia Frontend Transport; Fri, 8 Sep 2017 08:45:57 +0000",
            "from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net\n\t[10.232.134.28])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv888jmoZ023063; Fri, 8 Sep 2017 01:45:55 -0700"
        ],
        "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;",
        "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;",
        "From": "Hemant Agrawal <hemant.agrawal@nxp.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<ferruh.yigit@intel.com>, <shreyansh.jain@nxp.com>",
        "Date": "Fri, 8 Sep 2017 14:15:00 +0530",
        "Message-ID": "<1504860327-18451-4-git-send-email-hemant.agrawal@nxp.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1504860327-18451-1-git-send-email-hemant.agrawal@nxp.com>",
        "References": "<1503658183-4078-1-git-send-email-hemant.agrawal@nxp.com>\n\t<1504860327-18451-1-git-send-email-hemant.agrawal@nxp.com>",
        "X-EOPAttributedMessage": "0",
        "X-Matching-Connectors": "131493339573136414;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()",
        "X-Forefront-Antispam-Report": "CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(336005)(39380400002)(39860400002)(2980300002)(1109001)(1110001)(339900001)(189002)(199003)(48376002)(33646002)(5003940100001)(50466002)(5660300001)(68736007)(189998001)(106466001)(2351001)(105606002)(47776003)(36756003)(498600001)(77096006)(97736004)(2950100002)(6666003)(2906002)(8676002)(81166006)(53936002)(6916009)(8936002)(54906002)(356003)(85426001)(81156014)(104016004)(8656003)(305945005)(86362001)(4326008)(50226002)(110136004)(50986999)(76176999);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR03MB2266;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; ",
        "X-Microsoft-Exchange-Diagnostics": [
            "1; BY2FFO11FD011;\n\t1:VqGOA+zVCDejVOqDStNsIQN2Cp+wJ+sKPYsxqNkGOjDsLB3hgTaOucgkqs6qtN4/I3S3VfCWDtgK1gCtoaGT2doLRcmCKMIbwBHce+YK3Ut/loeq6lavsoetJ+naa/xm",
            "1; CY1PR03MB2266;\n\t3:kK7T0q9HL0VgE/bLDsMlPNlz/fjjGJBS4ztQSfhCCb3947Pk6JxbGdEIys8VuyEH8487FDDbYyPOrGUzMehstQbTF5BgptjUo87B3JkGgx7EaYJ27O1qgrj4nkVZy/JCVeSI8W40qtbG3gxbvUf6hlSwLxFYXfev/JcQOnfaRcmaiylS1XG/Ish1PMLg0TR6+ITUZWoYprGRz76BzS42Ce/EVnDNvW+iKxaYyHSBNRBzgu4pdrIbK75hXatUtxVSCG8wgPagNS0aeFo74jobESU0R2OiKd3Fwj1EMGNdTGAvSE6jS8ZbWNPo7YVLXThFFZqIoauathXwvW7ADOtSuwrx/I7B+tzh30bs2m/KgWk=;\n\t25:Fnzz+gYAD+3nmcwF1c1htwVCTcw+rZ76CiUxPsbXZhTHycgTwxJ1/erUIFswgBSdtQt57wZjNYKkH0/mlAyZcXnImdB0a5SIxIwIxDgvdVp7/6KXuETjfQqO+1dTEnvzcFbllPhz6QX54zo9DUEizryJBITMT9OLALz4is1SsDE3dmdjDsrcfmKhIHpCZDzSWndwObqYXmL57GeEuoXEo4BUhKTJemIdTv/ZogcDyVN2lt+5C2ui9Ghf+ij6nGMBtWVF2/IeX6lu+Cy44GzjAfW1C/AunyAzpvkTDCyMIO9NrLr+dFZ3Grj4xkgN3W8Ty8KWbWj7Alqyl8vuF6gSOg==",
            "1; CY1PR03MB2266;\n\t31:tAIiISqkq2TyMwr3/P/1S5lEN08vPb9MQ5j90/XrR6PfmC9wXOcOxbaqFK11sHkVxV/rsc40c+KwpkFg0xqY6oLN+3K/GQkaaACXinmVEUOcHW9P3vNya0Ycd7vRVcO3HpD0z1m2BdhNtdK8LGKlYfqBBRl4mAuK3Y4x5g9Oa32vu10VOAnOe8MgNNAog4d0l01sTHe/WoPpQA3hjvB2dzVRF91Nth0SujXD7LyptO8=;\n\t4:pzmRY9jzPQAQB5Th9Ux5cYiOheu1+PvbhWACR0jJOrneC2fB3vfHTdtsKFVLuspOADMcK8/ogSY2fd0EYmMZZ5IDAGPIY0vJOu5z05Cc9I5qolDbS6e9L+M2H0F2hxGwrM77iB9WYQn9QQUOdZ6+7EdrtXGoQPhEIWGbwEVtMpB0C0VtAUO5HRkrSU4DjCWO7qyQ7YrTcvnHfPYgW13mVSzRpb5eM2h+jbeQC6wgESY28h++9pwi1fGDqvsg65MINtYVBFZckDXhNs6G+qcE232oBHXHjZYnG+eGxhEGe0oDa9fwuLy0070lxhrbR2JuOrXHnytZNAzBC3/3ezi+DA==",
            "=?us-ascii?Q?1; CY1PR03MB2266;\n\t23:vxPg6ygCXKpi8sjfLR70oIJaBosL5Mug0drNJogZC?=\n\tmLo0U+m2MX7pTDJqCMh89ig80X3oYtf5oqLli//ivEcXI3ZmJP6KfydNTHwyKXRilN7o96zIO1yBhRMyXB4dnSthM/rV+jQlfU2atvrWgEjaQqVISRpe2fYpejerOF+94YmKASzHhzrHHRap1vz3hGlmLVHRlIBz+OD5b8d6vivgOEHxMbKk51Ux7DBFcXkF9FKzeutTjQQMEUfahwLeox8CA0wsLd6hT2EuAVkwHZEr0AJGx1nxvSLIgCadgeuzvQUTPlS9B893c2tBGvRsKCP9cHH25B3q7Tg6URm0Zg45XXGviOii/qrWMW26eM63jhuWw2p09Hjyey/Enbbeb6/ey0Sxjy3hkgfwe0gy7SZXXXGnn1IxdpAyvmRmDYoSs+1tjBe3TrjmBMpejU7BM/rWKos9x5lXR1UhGZrWYTT9vZmolXlM/5W52w3ukBMfV2mA5fSXoDE1XXVVCKfAty44TPrVlI/rD2uF76YR5ccgwGX/CtRGVJBQKFYhzqm9ErFZtwMFGs9UXsqjAisYqXV63N0ebapfi4atOIwLUzuuatiYCrXYEuFg7V97Zn8Nv8iXWJKvFFYfmctmDktyXvmgI3+V5V09V5LtOvoQPQw4t21wj8yJ+wyjG2WN+xE7LpCieaDbMVCr/nII6LomVWAWaFGDywxD4wg1GDj9eTQAhN5eHfh+kTKkrAVZqCAew6WeLZ84eWVN/P6AnpYpzQ1SLaatUOJAiI5dcuoDAytGWf9+MGp76/OITtu9g4glZ9qjBO0CW/cOpiI2rWLExREkPXa0aiYEHcGHVK8PCMoQ/ds88heTjvcSaIQAUHZL//yFd00ftA+uzD5PG5hUoj7NzMo8cB0BwizxctFwQTOu8rhhIbaLLx5VqzK6s7YanNFrqO9hNHcXlvqXJSmXlUByFdXRLq6y0fCmh1O23QeB6yVK8N1lLxGSkNkPBdsbxjbS8HddJ12RXpy4Hls7U8W3BdBxEyeAMwjE2xfzTQ5hOmJX2Ijda1vlwrUHlOqne7NrBwfaziF+b3nO9NuNsGrF+GZ7SQqU3estltPq3NowecXLxVuOzm+b/Yhqvq6UiA=",
            "1; CY1PR03MB2266;\n\t6:bPWDtvWAl9EQSozkaXW8PH5MEKUjbzfLpXEuy1v3H/ArC3VTIjYszdOhD+FSPmynHwZcOiUk/G0p5cn4l+Ki0NTerQKBcebErFwMQYLOOk6ac5BARa2Ya1kBtbnkKT5VzLKCE5NCATapEwnDL7tyIN92BzFymmx942EPZJ4LCqi+EfYw1kvflg8ueEhL6ESjVG3yeGvKsvmDF3jJmC+ToYTO2HTb+4kBrk3ifhNh7tki1ORciM7A0KqDSzG8s2JR2B54OwCJRKR709kNaQqtW/w0pfUSLa/TdmOt9rxt1yzul8dxhLqRePj3NT8elo20Hha48/fNI99fqDXqwL2Msg==;\n\t5:C114ebQZ7aQE+rAwhkvJw3EO2l/aFMZMcEpmTZjSYTt7+nmDkhaAYblwcZpgbP6HuYNcvtdHAF1QFi59e2VBo0VPMpbaBDt7p5wRUGc885RpueI9d6Cg+ZWgeukJLaWEvJF6a22Be2HFcbBtEVPYvg==;\n\t24:smiGG23TA/ZoQDqwxcXlguJu74IPKvMwbTT0OC8fbNh+ufQQ/pt/jUxKl9f/rVoA51kKT7IU2J6YAmbuXFUlCTa4zk3cUKTDEq6Bjsb1S8E=;\n\t7:tyJNJ+K8BHYQLpjAitPgwaRQ6hA6yvz30fldxcig1Ke4y7ij0pPA7VV596wEL1nbX2W33bP4GYSh3vjOuzhG6r2v+0GJK6nfvA6NhrBbhV9Vm9lXS9KqodoOqkdFBRT2k6N/wOCC1OHMAVfa+cn0Fo95twyRMp/1XBxbrthEKP/LSQa9quF031viXts/q/9Wexrqqo+5oSl0x/HM8KFAu7ptv1WpFV0cSZVBNxDUGT0="
        ],
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-MS-PublicTrafficType": "Email",
        "X-MS-Office365-Filtering-Correlation-Id": "eeeb716f-cc28-4629-2116-08d4f69605fa",
        "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(300000502095)(300135100095)(22001)(300000503095)(300135400095)(2017052603199)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:CY1PR03MB2266; ",
        "X-MS-TrafficTypeDiagnostic": "CY1PR03MB2266:",
        "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197)(275809806118684); ",
        "X-Microsoft-Antispam-PRVS": "<CY1PR03MB2266DF7A9E399686F172823D89950@CY1PR03MB2266.namprd03.prod.outlook.com>",
        "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(2401047)(8121501046)(5005006)(93006095)(93001095)(10201501046)(3002001)(100000703101)(100105400095)(6055026)(6096035)(201703131430075)(201703131448075)(201703131433075)(201703161259150)(201703151042153)(20161123559100)(20161123563025)(20161123565025)(20161123561025)(20161123556025)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:CY1PR03MB2266; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY1PR03MB2266; ",
        "X-Forefront-PRVS": "04244E0DC5",
        "SpamDiagnosticOutput": "1:99",
        "SpamDiagnosticMetadata": "NSPM",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Sep 2017 08:45:57.0016\n\t(UTC)",
        "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e",
        "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY1PR03MB2266",
        "Subject": "[dpdk-dev] [PATCH v2 03/30] bus/fslmc: add qbman API to do enqueue\n\twith multiple frames",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Haiying Wang <Haiying.Wang@nxp.com>\n\nClean it up and update the prototype.\n\nSigned-off-by: Haiying Wang <Haiying.Wang@nxp.com>\nSigned-off-by: Hemant Agrawal <Hemant.Agrawal@nxp.com>\n---\n drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h |  32 ++--\n drivers/bus/fslmc/qbman/qbman_portal.c             | 200 +++++++--------------\n drivers/bus/fslmc/rte_bus_fslmc_version.map        |   3 +-\n drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c        |   2 +-\n drivers/event/dpaa2/dpaa2_eventdev.c               |   2 +-\n drivers/net/dpaa2/dpaa2_rxtx.c                     |   2 +-\n 6 files changed, 83 insertions(+), 158 deletions(-)",
    "diff": "diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\nindex 23c3d13..fe1cc94 100644\n--- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\n+++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\n@@ -914,19 +914,33 @@ void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable,\n int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,\n \t\t      const struct qbman_fd *fd);\n /**\n- * qbman_swp_enqueue_multiple_eqdesc() - Enqueue multiple frames with separte\n- * enqueue descriptors.\n+ * qbman_swp_enqueue_multiple() - Enqueue multiple frames with same\n+\t\t\t\t  eq descriptor\n  * @s: the software portal used for enqueue.\n- * @d: the enqueue descriptors\n+ * @d: the enqueue descriptor.\n  * @fd: the frame descriptor to be enqueued.\n  * @num_frames: the number of the frames to be enqueued.\n  *\n  * Return the number of enqueued frames, -EBUSY if the EQCR is not ready.\n  */\n-int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s,\n+int qbman_swp_enqueue_multiple(struct qbman_swp *s,\n \t\t\t       const struct qbman_eq_desc *d,\n \t\t\t       const struct qbman_fd *fd,\n \t\t\t       int num_frames);\n+/**\n+ * qbman_swp_enqueue_multiple_desc() - Enqueue multiple frames with\n+ *\t\t\t\t       individual eq descriptor.\n+ * @s: the software portal used for enqueue.\n+ * @d: the enqueue descriptor.\n+ * @fd: the frame descriptor to be enqueued.\n+ * @num_frames: the number of the frames to be enqueued.\n+ *\n+ * Return the number of enqueued frames, -EBUSY if the EQCR is not ready.\n+ */\n+int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,\n+\t\t\t\t    const struct qbman_eq_desc *d,\n+\t\t\t\t    const struct qbman_fd *fd,\n+\t\t\t\t    int num_frames);\n \n /* TODO:\n  * qbman_swp_enqueue_thresh() - Set threshold for EQRI interrupt.\n@@ -1119,16 +1133,6 @@ int qbman_swp_CDAN_disable(struct qbman_swp *s, uint16_t channelid);\n  */\n int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid,\n \t\t\t\t      uint64_t ctx);\n-int qbman_swp_fill_ring(struct qbman_swp *s,\n-\t\t\tconst struct qbman_eq_desc *d,\n-\t\t       const struct qbman_fd *fd,\n-\t\t       uint8_t burst_index);\n-int qbman_swp_flush_ring(struct qbman_swp *s);\n-void qbman_sync(void);\n-int qbman_swp_send_multiple(struct qbman_swp *s,\n-\t\t\t    const struct qbman_eq_desc *d,\n-\t\t\t    const struct qbman_fd *fd,\n-\t\t\t    int frames_to_send);\n \n int qbman_check_command_complete(struct qbman_swp *s,\n \t\t\t\t const struct qbman_result *dq);\ndiff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c\nindex 97df703..f212829 100644\n--- a/drivers/bus/fslmc/qbman/qbman_portal.c\n+++ b/drivers/bus/fslmc/qbman/qbman_portal.c\n@@ -525,15 +525,26 @@ static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s,\n \treturn 0;\n }\n \n-int qbman_swp_fill_ring(struct qbman_swp *s,\n-\t\t\tconst struct qbman_eq_desc *d,\n-\t\t\tconst struct qbman_fd *fd,\n-\t\t\t__attribute__((unused)) uint8_t burst_index)\n+int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,\n+\t\t      const struct qbman_fd *fd)\n+{\n+\tif (s->sys.eqcr_mode == qman_eqcr_vb_array)\n+\t\treturn qbman_swp_enqueue_array_mode(s, d, fd);\n+\telse    /* Use ring mode by default */\n+\t\treturn qbman_swp_enqueue_ring_mode(s, d, fd);\n+}\n+\n+int qbman_swp_enqueue_multiple(struct qbman_swp *s,\n+\t\t\t       const struct qbman_eq_desc *d,\n+\t\t\t       const struct qbman_fd *fd,\n+\t\t\t       int num_frames)\n {\n \tuint32_t *p;\n \tconst uint32_t *cl = qb_cl(d);\n-\tuint32_t eqcr_ci;\n+\tuint32_t eqcr_ci, eqcr_pi;\n \tuint8_t diff;\n+\tint i, num_enqueued = 0;\n+\tuint64_t addr_cena;\n \n \tif (!s->eqcr.available) {\n \t\teqcr_ci = s->eqcr.ci;\n@@ -543,62 +554,58 @@ int qbman_swp_fill_ring(struct qbman_swp *s,\n \t\t\t\t   eqcr_ci, s->eqcr.ci);\n \t\ts->eqcr.available += diff;\n \t\tif (!diff)\n-\t\t\treturn -EBUSY;\n+\t\t\treturn 0;\n \t}\n-\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n-\t\tQBMAN_CENA_SWP_EQCR((s->eqcr.pi/* +burst_index */) & 7));\n-\tmemcpy(&p[1], &cl[1], 7 * 4);\n-\tmemcpy(&p[8], fd, sizeof(struct qbman_fd));\n-\n-\t/* lwsync(); */\n-\tp[0] = cl[0] | s->eqcr.pi_vb;\n-\n-\ts->eqcr.pi++;\n-\ts->eqcr.pi &= 0xF;\n-\ts->eqcr.available--;\n-\tif (!(s->eqcr.pi & 7))\n-\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n-\n-\treturn 0;\n-}\n \n-int qbman_swp_flush_ring(struct qbman_swp *s)\n-{\n-\tvoid *ptr = s->sys.addr_cena;\n+\teqcr_pi = s->eqcr.pi;\n+\tnum_enqueued = (s->eqcr.available < num_frames) ?\n+\t\t\ts->eqcr.available : num_frames;\n+\ts->eqcr.available -= num_enqueued;\n+\t/* Fill in the EQCR ring */\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & 7));\n+\t\tmemcpy(&p[1], &cl[1], 28);\n+\t\tmemcpy(&p[8], &fd[i], sizeof(*fd));\n+\t\teqcr_pi++;\n+\t\teqcr_pi &= 0xF;\n+\t}\n \n-\tdcbf((uint64_t)ptr);\n-\tdcbf((uint64_t)ptr + 0x40);\n-\tdcbf((uint64_t)ptr + 0x80);\n-\tdcbf((uint64_t)ptr + 0xc0);\n-\tdcbf((uint64_t)ptr + 0x100);\n-\tdcbf((uint64_t)ptr + 0x140);\n-\tdcbf((uint64_t)ptr + 0x180);\n-\tdcbf((uint64_t)ptr + 0x1c0);\n+\tlwsync();\n \n-\treturn 0;\n-}\n+\t/* Set the verb byte, have to substitute in the valid-bit */\n+\teqcr_pi = s->eqcr.pi;\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & 7));\n+\t\tp[0] = cl[0] | s->eqcr.pi_vb;\n+\t\teqcr_pi++;\n+\t\teqcr_pi &= 0xF;\n+\t\tif (!(eqcr_pi & 7))\n+\t\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n+\t}\n \n-void qbman_sync(void)\n-{\n-\tlwsync();\n-}\n+\t/* Flush all the cacheline without load/store in between */\n+\teqcr_pi = s->eqcr.pi;\n+\taddr_cena = (uint64_t)s->sys.addr_cena;\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tdcbf((uint64_t *)(addr_cena +\n+\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));\n+\t\teqcr_pi++;\n+\t\teqcr_pi &= 0xF;\n+\t}\n+\ts->eqcr.pi = eqcr_pi;\n \n-int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,\n-\t\t      const struct qbman_fd *fd)\n-{\n-\tif (s->sys.eqcr_mode == qman_eqcr_vb_array)\n-\t\treturn qbman_swp_enqueue_array_mode(s, d, fd);\n-\telse    /* Use ring mode by default */\n-\t\treturn qbman_swp_enqueue_ring_mode(s, d, fd);\n+\treturn num_enqueued;\n }\n \n-int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s,\n-\t\t\t       const struct qbman_eq_desc *d,\n-\t\t\t       const struct qbman_fd *fd,\n-\t\t\t       int num_frames)\n+int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,\n+\t\t\t\t    const struct qbman_eq_desc *d,\n+\t\t\t\t    const struct qbman_fd *fd,\n+\t\t\t\t    int num_frames)\n {\n \tuint32_t *p;\n-\tconst uint32_t *cl = qb_cl(d);\n+\tconst uint32_t *cl;\n \tuint32_t eqcr_ci, eqcr_pi;\n \tuint8_t diff;\n \tint i, num_enqueued = 0;\n@@ -623,29 +630,26 @@ int qbman_swp_enqueue_multiple_eqdesc(struct qbman_swp *s,\n \tfor (i = 0; i < num_enqueued; i++) {\n \t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n \t\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & 7));\n+\t\tcl = qb_cl(&d[i]);\n \t\tmemcpy(&p[1], &cl[1], 28);\n \t\tmemcpy(&p[8], &fd[i], sizeof(*fd));\n \t\teqcr_pi++;\n \t\teqcr_pi &= 0xF;\n-\t\t/*Pointing to the next enqueue descriptor*/\n-\t\tcl += (sizeof(struct qbman_eq_desc) / sizeof(uint32_t));\n \t}\n \n \tlwsync();\n \n \t/* Set the verb byte, have to substitute in the valid-bit */\n \teqcr_pi = s->eqcr.pi;\n-\tcl = qb_cl(d);\n \tfor (i = 0; i < num_enqueued; i++) {\n \t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n \t\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & 7));\n+\t\tcl = qb_cl(&d[i]);\n \t\tp[0] = cl[0] | s->eqcr.pi_vb;\n \t\teqcr_pi++;\n \t\teqcr_pi &= 0xF;\n \t\tif (!(eqcr_pi & 7))\n \t\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n-\t\t/*Pointing to the next enqueue descriptor*/\n-\t\tcl += (sizeof(struct qbman_eq_desc) / sizeof(uint32_t));\n \t}\n \n \t/* Flush all the cacheline without load/store in between */\n@@ -1493,87 +1497,3 @@ struct qbman_result *qbman_get_dqrr_from_idx(struct qbman_swp *s, uint8_t idx)\n \tdq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(idx));\n \treturn dq;\n }\n-\n-int qbman_swp_send_multiple(struct qbman_swp *s,\n-\t\t\t    const struct qbman_eq_desc *d,\n-\t\t\t    const struct qbman_fd *fd,\n-\t\t\t    int frames_to_send)\n-{\n-\tuint32_t *p;\n-\tconst uint32_t *cl = qb_cl(d);\n-\tuint32_t eqcr_ci;\n-\tuint8_t diff;\n-\tint sent = 0;\n-\tint i;\n-\tint initial_pi = s->eqcr.pi;\n-\tuint64_t start_pointer;\n-\n-\tif (!s->eqcr.available) {\n-\t\teqcr_ci = s->eqcr.ci;\n-\t\ts->eqcr.ci = qbman_cena_read_reg(&s->sys,\n-\t\t\t\t QBMAN_CENA_SWP_EQCR_CI) & 0xF;\n-\t\tdiff = qm_cyc_diff(QBMAN_EQCR_SIZE,\n-\t\t\t\t   eqcr_ci, s->eqcr.ci);\n-\t\tif (!diff)\n-\t\t\tgoto done;\n-\t\ts->eqcr.available += diff;\n-\t}\n-\n-\t/* we are trying to send frames_to_send,\n-\t * if we have enough space in the ring\n-\t */\n-\twhile (s->eqcr.available && frames_to_send--) {\n-\t\tp = qbman_cena_write_start_wo_shadow_fast(&s->sys,\n-\t\t\t\t\tQBMAN_CENA_SWP_EQCR((initial_pi) & 7));\n-\t\t/* Write command (except of first byte) and FD */\n-\t\tmemcpy(&p[1], &cl[1], 7 * 4);\n-\t\tmemcpy(&p[8], &fd[sent], sizeof(struct qbman_fd));\n-\n-\t\tinitial_pi++;\n-\t\tinitial_pi &= 0xF;\n-\t\ts->eqcr.available--;\n-\t\tsent++;\n-\t}\n-\n-done:\n-\tinitial_pi =  s->eqcr.pi;\n-\tlwsync();\n-\n-\t/* in order for flushes to complete faster:\n-\t * we use a following trick: we record all lines in 32 bit word\n-\t */\n-\n-\tinitial_pi =  s->eqcr.pi;\n-\tfor (i = 0; i < sent; i++) {\n-\t\tp = qbman_cena_write_start_wo_shadow_fast(&s->sys,\n-\t\t\t\t\tQBMAN_CENA_SWP_EQCR((initial_pi) & 7));\n-\n-\t\tp[0] = cl[0] | s->eqcr.pi_vb;\n-\t\tinitial_pi++;\n-\t\tinitial_pi &= 0xF;\n-\n-\t\tif (!(initial_pi & 7))\n-\t\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n-\t}\n-\n-\tinitial_pi = s->eqcr.pi;\n-\n-\t/* We need  to flush all the lines but without\n-\t * load/store operations between them.\n-\t * We assign start_pointer before we start loop so that\n-\t * in loop we do not read it from memory\n-\t */\n-\tstart_pointer = (uint64_t)s->sys.addr_cena;\n-\tfor (i = 0; i < sent; i++) {\n-\t\tp = (uint32_t *)(start_pointer\n-\t\t\t\t + QBMAN_CENA_SWP_EQCR(initial_pi & 7));\n-\t\tdcbf((uint64_t)p);\n-\t\tinitial_pi++;\n-\t\tinitial_pi &= 0xF;\n-\t}\n-\n-\t/* Update producer index for the next call */\n-\ts->eqcr.pi = initial_pi;\n-\n-\treturn sent;\n-}\ndiff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map\nindex 6ac256d..13fb46a 100644\n--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map\n+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map\n@@ -69,7 +69,8 @@ DPDK_17.08 {\n \tqbman_result_SCN_state_in_mem;\n \tqbman_swp_dqrr_consume;\n \tqbman_swp_dqrr_next;\n-\tqbman_swp_enqueue_multiple_eqdesc;\n+\tqbman_swp_enqueue_multiple;\n+\tqbman_swp_enqueue_multiple_desc;\n \tqbman_swp_interrupt_clear_status;\n \tqbman_swp_push_set;\n \trte_dpaa2_alloc_dpci_dev;\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\nindex 95c3951..094cf30 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n@@ -634,7 +634,7 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n \t\t}\n \t\tloop = 0;\n \t\twhile (loop < frames_to_send) {\n-\t\t\tloop += qbman_swp_send_multiple(swp, &eqdesc,\n+\t\t\tloop += qbman_swp_enqueue_multiple(swp, &eqdesc,\n \t\t\t\t\t\t\t&fd_arr[loop],\n \t\t\t\t\t\t\tframes_to_send - loop);\n \t\t}\ndiff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c\nindex cf2d274..81286a8 100644\n--- a/drivers/event/dpaa2/dpaa2_eventdev.c\n+++ b/drivers/event/dpaa2/dpaa2_eventdev.c\n@@ -144,7 +144,7 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],\n \t\t}\n \t\tloop = 0;\n \t\twhile (loop < frames_to_send) {\n-\t\t\tloop += qbman_swp_enqueue_multiple_eqdesc(swp,\n+\t\t\tloop += qbman_swp_enqueue_multiple_desc(swp,\n \t\t\t\t\t&eqdesc[loop], &fd_arr[loop],\n \t\t\t\t\tframes_to_send - loop);\n \t\t}\ndiff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c\nindex 3c057a3..4342c73 100644\n--- a/drivers/net/dpaa2/dpaa2_rxtx.c\n+++ b/drivers/net/dpaa2/dpaa2_rxtx.c\n@@ -622,7 +622,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n \t\t}\n \t\tloop = 0;\n \t\twhile (loop < frames_to_send) {\n-\t\t\tloop += qbman_swp_send_multiple(swp, &eqdesc,\n+\t\t\tloop += qbman_swp_enqueue_multiple(swp, &eqdesc,\n \t\t\t\t\t&fd_arr[loop], frames_to_send - loop);\n \t\t}\n \n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "03/30"
    ]
}