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GET /api/patches/28325/?format=api
{ "id": 28325, "url": "http://patches.dpdk.org/api/patches/28325/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/bf3a648369b1b8d2023819a1372c08c6cc5f0de8.1504525643.git.shacharbe@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<bf3a648369b1b8d2023819a1372c08c6cc5f0de8.1504525643.git.shacharbe@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/bf3a648369b1b8d2023819a1372c08c6cc5f0de8.1504525643.git.shacharbe@mellanox.com", "date": "2017-09-04T11:48:45", "name": "[dpdk-dev,1/3] net/mlx5: replace network to host macros", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "692a02bca03b51e4ff26da58532941fe610674ff", "submitter": { "id": 746, "url": "http://patches.dpdk.org/api/people/746/?format=api", "name": "Shachar Beiser", "email": "shacharbe@mellanox.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/bf3a648369b1b8d2023819a1372c08c6cc5f0de8.1504525643.git.shacharbe@mellanox.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/28325/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/28325/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 3CB287CEC;\n\tMon, 4 Sep 2017 13:49:23 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id A3DB237A0\n\tfor <dev@dpdk.org>; Mon, 4 Sep 2017 13:49:18 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n\tshacharbe@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 4 Sep 2017 14:49:16 +0300", "from pegasus08.mtr.labs.mlnx (pegasus08.mtr.labs.mlnx\n\t[10.210.16.114])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v84BnGxp017938;\n\tMon, 4 Sep 2017 14:49:16 +0300", "from pegasus08.mtr.labs.mlnx (localhost [127.0.0.1])\n\tby pegasus08.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id\n\tv84BnGgR007252; Mon, 4 Sep 2017 11:49:16 GMT", "(from shacharbe@localhost)\n\tby pegasus08.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id v84BnGUC007251; \n\tMon, 4 Sep 2017 11:49:16 GMT" ], "From": "Shachar Beiser <shacharbe@mellanox.com>", "To": "dev@dpdk.org", "Cc": "Shachar Beiser <shacharbe@mellanox.com>,\n\tAdrien Mazarguil <adrien.mazarguil@6wind.com>,\n\tNelio Laranjeiro <nelio.laranjeiro@6wind.com>", "Date": "Mon, 4 Sep 2017 11:48:45 +0000", "Message-Id": "<bf3a648369b1b8d2023819a1372c08c6cc5f0de8.1504525643.git.shacharbe@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "Subject": "[dpdk-dev] [PATCH 1/3] net/mlx5: replace network to host macros", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Fixes: 8bb5119634b7 (\"net/mlx5: replace network byte order macro\")\nCc: shacharbe@mellanox.com\n\nSigned-off-by: Shachar Beiser <shacharbe@mellanox.com>\n---\n drivers/net/mlx5/mlx5_mac.c | 8 ++-\n drivers/net/mlx5/mlx5_mr.c | 2 +-\n drivers/net/mlx5/mlx5_rxmode.c | 8 ++-\n drivers/net/mlx5/mlx5_rxq.c | 9 +--\n drivers/net/mlx5/mlx5_rxtx.c | 131 +++++++++++++++++++----------------\n drivers/net/mlx5/mlx5_rxtx.h | 12 ++--\n drivers/net/mlx5/mlx5_rxtx_vec_sse.c | 12 ++--\n 7 files changed, 102 insertions(+), 80 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_mac.c b/drivers/net/mlx5/mlx5_mac.c\nindex 45d23e4..b3c3fa2 100644\n--- a/drivers/net/mlx5/mlx5_mac.c\n+++ b/drivers/net/mlx5/mlx5_mac.c\n@@ -263,11 +263,15 @@\n \t\t\t\t(*mac)[0], (*mac)[1], (*mac)[2],\n \t\t\t\t(*mac)[3], (*mac)[4], (*mac)[5]\n \t\t\t},\n-\t\t\t.vlan_tag = (vlan_enabled ? htons(vlan_id) : 0),\n+\t\t\t.vlan_tag = (vlan_enabled ?\n+\t\t\t\t rte_cpu_to_be_16(vlan_id)\n+\t\t\t\t : 0),\n \t\t},\n \t\t.mask = {\n \t\t\t.dst_mac = \"\\xff\\xff\\xff\\xff\\xff\\xff\",\n-\t\t\t.vlan_tag = (vlan_enabled ? htons(0xfff) : 0),\n+\t\t\t.vlan_tag = (vlan_enabled ?\n+\t\t\t\t rte_cpu_to_be_16(0xfff) :\n+\t\t\t\t 0),\n \t\t},\n \t};\n \tDEBUG(\"%p: adding MAC address %02x:%02x:%02x:%02x:%02x:%02x index %u\"\ndiff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c\nindex 9593830..9a9f73a 100644\n--- a/drivers/net/mlx5/mlx5_mr.c\n+++ b/drivers/net/mlx5/mlx5_mr.c\n@@ -203,7 +203,7 @@ struct ibv_mr *\n \ttxq_ctrl->txq.mp2mr[idx].start = (uintptr_t)mr->addr;\n \ttxq_ctrl->txq.mp2mr[idx].end = (uintptr_t)mr->addr + mr->length;\n \ttxq_ctrl->txq.mp2mr[idx].mr = mr;\n-\ttxq_ctrl->txq.mp2mr[idx].lkey = htonl(mr->lkey);\n+\ttxq_ctrl->txq.mp2mr[idx].lkey = rte_cpu_to_be_32(mr->lkey);\n \tDEBUG(\"%p: new MR lkey for MP \\\"%s\\\" (%p): 0x%08\" PRIu32,\n \t (void *)txq_ctrl, mp->name, (void *)mp,\n \t txq_ctrl->txq.mp2mr[idx].lkey);\ndiff --git a/drivers/net/mlx5/mlx5_rxmode.c b/drivers/net/mlx5/mlx5_rxmode.c\nindex 4a51e47..db2e05b 100644\n--- a/drivers/net/mlx5/mlx5_rxmode.c\n+++ b/drivers/net/mlx5/mlx5_rxmode.c\n@@ -159,14 +159,18 @@\n \t\t\t\tmac[0], mac[1], mac[2],\n \t\t\t\tmac[3], mac[4], mac[5],\n \t\t\t},\n-\t\t\t.vlan_tag = (vlan_enabled ? htons(vlan_id) : 0),\n+\t\t\t.vlan_tag = (vlan_enabled ?\n+\t\t\t\t rte_cpu_to_be_16(vlan_id) :\n+\t\t\t\t 0),\n \t\t},\n \t\t.mask = {\n \t\t\t.dst_mac = {\n \t\t\t\tmask[0], mask[1], mask[2],\n \t\t\t\tmask[3], mask[4], mask[5],\n \t\t\t},\n-\t\t\t.vlan_tag = (vlan_enabled ? htons(0xfff) : 0),\n+\t\t\t.vlan_tag = (vlan_enabled ?\n+\t\t\t\t rte_cpu_to_be_16(0xfff) :\n+\t\t\t\t 0),\n \t\t},\n \t};\n \ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 35c5cb4..437dc02 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -672,9 +672,10 @@\n \t\t/* scat->addr must be able to store a pointer. */\n \t\tassert(sizeof(scat->addr) >= sizeof(uintptr_t));\n \t\t*scat = (struct mlx5_wqe_data_seg){\n-\t\t\t.addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t)),\n-\t\t\t.byte_count = htonl(DATA_LEN(buf)),\n-\t\t\t.lkey = htonl(rxq_ctrl->mr->lkey),\n+\t\t\t.addr =\n+\t\t\t rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t)),\n+\t\t\t.byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),\n+\t\t\t.lkey = rte_cpu_to_be_32(rxq_ctrl->mr->lkey),\n \t\t};\n \t\t(*rxq_ctrl->rxq.elts)[i] = buf;\n \t}\n@@ -1077,7 +1078,7 @@\n \t/* Update doorbell counter. */\n \trxq_ctrl->rxq.rq_ci = desc >> rxq_ctrl->rxq.sges_n;\n \trte_wmb();\n-\t*rxq_ctrl->rxq.rq_db = htonl(rxq_ctrl->rxq.rq_ci);\n+\t*rxq_ctrl->rxq.rq_db = rte_cpu_to_be_32(rxq_ctrl->rxq.rq_ci);\n \tDEBUG(\"%p: rxq updated with %p\", (void *)rxq_ctrl, (void *)&tmpl);\n \tassert(ret == 0);\n \treturn 0;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex fe9e7ea..e1a35a3 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -306,7 +306,7 @@\n \n \t\top_own = cqe->op_own;\n \t\tif (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)\n-\t\t\tn = ntohl(cqe->byte_cnt);\n+\t\t\tn = rte_be_to_cpu_32(cqe->byte_cnt);\n \t\telse\n \t\t\tn = 1;\n \t\tcq_ci += n;\n@@ -434,7 +434,8 @@\n \t\traw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;\n \t\t/* Replace the Ethernet type by the VLAN if necessary. */\n \t\tif (buf->ol_flags & PKT_TX_VLAN_PKT) {\n-\t\t\tuint32_t vlan = htonl(0x81000000 | buf->vlan_tci);\n+\t\t\tuint32_t vlan = rte_cpu_to_be_32(0x81000000 |\n+\t\t\t\t\t\t\t buf->vlan_tci);\n \t\t\tunsigned int len = 2 * ETHER_ADDR_LEN - 2;\n \n \t\t\taddr += 2;\n@@ -510,8 +511,10 @@\n \t\t\t\t} else {\n \t\t\t\t\t/* NOP WQE. */\n \t\t\t\t\twqe->ctrl = (rte_v128u32_t){\n-\t\t\t\t\t\t htonl(txq->wqe_ci << 8),\n-\t\t\t\t\t\t htonl(txq->qp_num_8s | 1),\n+\t\t\t\t\t\t rte_cpu_to_be_32(\n+\t\t\t\t\t\t\ttxq->wqe_ci << 8),\n+\t\t\t\t\t\t rte_cpu_to_be_32(\n+\t\t\t\t\t\t\ttxq->qp_num_8s | 1),\n \t\t\t\t\t\t 0,\n \t\t\t\t\t\t 0,\n \t\t\t\t\t};\n@@ -550,7 +553,8 @@\n \t\t\t\tmax_wqe -= n;\n \t\t\t\tif (tso) {\n \t\t\t\t\tuint32_t inl =\n-\t\t\t\t\t\thtonl(copy_b | MLX5_INLINE_SEG);\n+\t\t\t\t\trte_cpu_to_be_32(copy_b |\n+\t\t\t\t\t\t\t MLX5_INLINE_SEG);\n \n \t\t\t\t\tpkt_inline_sz =\n \t\t\t\t\t\tMLX5_WQE_DS(tso_header_sz) *\n@@ -603,9 +607,9 @@\n \t\t\tds = 3;\n use_dseg:\n \t\t\t/* Add the remaining packet as a simple ds. */\n-\t\t\tnaddr = htonll(addr);\n+\t\t\tnaddr = rte_cpu_to_be_64(addr);\n \t\t\t*dseg = (rte_v128u32_t){\n-\t\t\t\thtonl(length),\n+\t\t\t\trte_cpu_to_be_32(length),\n \t\t\t\tmlx5_tx_mb2mr(txq, buf),\n \t\t\t\tnaddr,\n \t\t\t\tnaddr >> 32,\n@@ -642,9 +646,9 @@\n \t\ttotal_length += length;\n #endif\n \t\t/* Store segment information. */\n-\t\tnaddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));\n+\t\tnaddr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));\n \t\t*dseg = (rte_v128u32_t){\n-\t\t\thtonl(length),\n+\t\t\trte_cpu_to_be_32(length),\n \t\t\tmlx5_tx_mb2mr(txq, buf),\n \t\t\tnaddr,\n \t\t\tnaddr >> 32,\n@@ -663,21 +667,23 @@\n \t\t/* Initialize known and common part of the WQE structure. */\n \t\tif (tso) {\n \t\t\twqe->ctrl = (rte_v128u32_t){\n-\t\t\t\thtonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),\n-\t\t\t\thtonl(txq->qp_num_8s | ds),\n+\t\t\t\trte_cpu_to_be_32((txq->wqe_ci << 8) |\n+\t\t\t\t\t\t MLX5_OPCODE_TSO),\n+\t\t\t\trte_cpu_to_be_32(txq->qp_num_8s | ds),\n \t\t\t\t0,\n \t\t\t\t0,\n \t\t\t};\n \t\t\twqe->eseg = (rte_v128u32_t){\n \t\t\t\t0,\n-\t\t\t\tcs_flags | (htons(tso_segsz) << 16),\n+\t\t\t\tcs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),\n \t\t\t\t0,\n-\t\t\t\t(ehdr << 16) | htons(tso_header_sz),\n+\t\t\t\t(ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),\n \t\t\t};\n \t\t} else {\n \t\t\twqe->ctrl = (rte_v128u32_t){\n-\t\t\t\thtonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),\n-\t\t\t\thtonl(txq->qp_num_8s | ds),\n+\t\t\t\trte_cpu_to_be_32((txq->wqe_ci << 8) |\n+\t\t\t\t\t\t MLX5_OPCODE_SEND),\n+\t\t\t\trte_cpu_to_be_32(txq->qp_num_8s | ds),\n \t\t\t\t0,\n \t\t\t\t0,\n \t\t\t};\n@@ -685,7 +691,7 @@\n \t\t\t\t0,\n \t\t\t\tcs_flags,\n \t\t\t\t0,\n-\t\t\t\t(ehdr << 16) | htons(pkt_inline_sz),\n+\t\t\t\t(ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),\n \t\t\t};\n \t\t}\n next_wqe:\n@@ -705,7 +711,7 @@\n \tcomp = txq->elts_comp + i + j + k;\n \tif (comp >= MLX5_TX_COMP_THRESH) {\n \t\t/* Request completion on last WQE. */\n-\t\tlast_wqe->ctrl2 = htonl(8);\n+\t\tlast_wqe->ctrl2 = rte_cpu_to_be_32(8);\n \t\t/* Save elts_head in unused \"immediate\" field of WQE. */\n \t\tlast_wqe->ctrl3 = txq->elts_head;\n \t\ttxq->elts_comp = 0;\n@@ -744,13 +750,14 @@\n \tmpw->len = length;\n \tmpw->total_len = 0;\n \tmpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);\n-\tmpw->wqe->eseg.mss = htons(length);\n+\tmpw->wqe->eseg.mss = rte_cpu_to_be_16(length);\n \tmpw->wqe->eseg.inline_hdr_sz = 0;\n \tmpw->wqe->eseg.rsvd0 = 0;\n \tmpw->wqe->eseg.rsvd1 = 0;\n \tmpw->wqe->eseg.rsvd2 = 0;\n-\tmpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |\n-\t\t\t\t (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);\n+\tmpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |\n+\t\t\t\t\t (txq->wqe_ci << 8) |\n+\t\t\t\t\t MLX5_OPCODE_TSO);\n \tmpw->wqe->ctrl[2] = 0;\n \tmpw->wqe->ctrl[3] = 0;\n \tmpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)\n@@ -779,7 +786,7 @@\n \t * Store size in multiple of 16 bytes. Control and Ethernet segments\n \t * count as 2.\n \t */\n-\tmpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));\n+\tmpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));\n \tmpw->state = MLX5_MPW_STATE_CLOSED;\n \tif (num < 3)\n \t\t++txq->wqe_ci;\n@@ -886,9 +893,9 @@\n \t\t\tdseg = mpw.data.dseg[mpw.pkts_n];\n \t\t\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n \t\t\t*dseg = (struct mlx5_wqe_data_seg){\n-\t\t\t\t.byte_count = htonl(DATA_LEN(buf)),\n+\t\t\t\t.byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),\n \t\t\t\t.lkey = mlx5_tx_mb2mr(txq, buf),\n-\t\t\t\t.addr = htonll(addr),\n+\t\t\t\t.addr = rte_cpu_to_be_64(addr),\n \t\t\t};\n #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)\n \t\t\tlength += DATA_LEN(buf);\n@@ -916,7 +923,7 @@\n \t\tvolatile struct mlx5_wqe *wqe = mpw.wqe;\n \n \t\t/* Request completion on last WQE. */\n-\t\twqe->ctrl[2] = htonl(8);\n+\t\twqe->ctrl[2] = rte_cpu_to_be_32(8);\n \t\t/* Save elts_head in unused \"immediate\" field of WQE. */\n \t\twqe->ctrl[3] = elts_head;\n \t\ttxq->elts_comp = 0;\n@@ -956,12 +963,12 @@\n \tmpw->len = length;\n \tmpw->total_len = 0;\n \tmpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);\n-\tmpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |\n-\t\t\t\t (txq->wqe_ci << 8) |\n-\t\t\t\t MLX5_OPCODE_TSO);\n+\tmpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |\n+\t\t\t\t\t (txq->wqe_ci << 8) |\n+\t\t\t\t\t MLX5_OPCODE_TSO);\n \tmpw->wqe->ctrl[2] = 0;\n \tmpw->wqe->ctrl[3] = 0;\n-\tmpw->wqe->eseg.mss = htons(length);\n+\tmpw->wqe->eseg.mss = rte_cpu_to_be_16(length);\n \tmpw->wqe->eseg.inline_hdr_sz = 0;\n \tmpw->wqe->eseg.cs_flags = 0;\n \tmpw->wqe->eseg.rsvd0 = 0;\n@@ -992,9 +999,10 @@\n \t * Store size in multiple of 16 bytes. Control and Ethernet segments\n \t * count as 2.\n \t */\n-\tmpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));\n+\tmpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |\n+\t\t\t\t\t MLX5_WQE_DS(size));\n \tmpw->state = MLX5_MPW_STATE_CLOSED;\n-\tinl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);\n+\tinl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);\n \ttxq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;\n }\n \n@@ -1132,9 +1140,10 @@\n \t\t\t\tdseg = mpw.data.dseg[mpw.pkts_n];\n \t\t\t\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n \t\t\t\t*dseg = (struct mlx5_wqe_data_seg){\n-\t\t\t\t\t.byte_count = htonl(DATA_LEN(buf)),\n+\t\t\t\t\t.byte_count =\n+\t\t\t\t\t rte_cpu_to_be_32(DATA_LEN(buf)),\n \t\t\t\t\t.lkey = mlx5_tx_mb2mr(txq, buf),\n-\t\t\t\t\t.addr = htonll(addr),\n+\t\t\t\t\t.addr = rte_cpu_to_be_64(addr),\n \t\t\t\t};\n #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)\n \t\t\t\tlength += DATA_LEN(buf);\n@@ -1206,7 +1215,7 @@\n \t\tvolatile struct mlx5_wqe *wqe = mpw.wqe;\n \n \t\t/* Request completion on last WQE. */\n-\t\twqe->ctrl[2] = htonl(8);\n+\t\twqe->ctrl[2] = rte_cpu_to_be_32(8);\n \t\t/* Save elts_head in unused \"immediate\" field of WQE. */\n \t\twqe->ctrl[3] = elts_head;\n \t\ttxq->elts_comp = 0;\n@@ -1246,9 +1255,10 @@\n \tmpw->pkts_n = 0;\n \tmpw->total_len = sizeof(struct mlx5_wqe);\n \tmpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);\n-\tmpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |\n-\t\t\t\t (txq->wqe_ci << 8) |\n-\t\t\t\t MLX5_OPCODE_ENHANCED_MPSW);\n+\tmpw->wqe->ctrl[0] =\n+\t\trte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |\n+\t\t\t\t (txq->wqe_ci << 8) |\n+\t\t\t\t MLX5_OPCODE_ENHANCED_MPSW);\n \tmpw->wqe->ctrl[2] = 0;\n \tmpw->wqe->ctrl[3] = 0;\n \tmemset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);\n@@ -1256,9 +1266,9 @@\n \t\tuintptr_t addr = (uintptr_t)(mpw->wqe + 1);\n \n \t\t/* Pad the first 2 DWORDs with zero-length inline header. */\n-\t\t*(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);\n+\t\t*(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);\n \t\t*(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =\n-\t\t\thtonl(MLX5_INLINE_SEG);\n+\t\t\trte_cpu_to_be_32(MLX5_INLINE_SEG);\n \t\tmpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;\n \t\t/* Start from the next WQEBB. */\n \t\tmpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));\n@@ -1286,7 +1296,8 @@\n \t/* Store size in multiple of 16 bytes. Control and Ethernet segments\n \t * count as 2.\n \t */\n-\tmpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));\n+\tmpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |\n+\t\t\t\t\t MLX5_WQE_DS(mpw->total_len));\n \tmpw->state = MLX5_MPW_STATE_CLOSED;\n \tret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;\n \ttxq->wqe_ci += ret;\n@@ -1439,9 +1450,10 @@\n \t\t\t\tdseg = mpw.data.dseg[mpw.pkts_n];\n \t\t\t\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n \t\t\t\t*dseg = (struct mlx5_wqe_data_seg){\n-\t\t\t\t\t.byte_count = htonl(DATA_LEN(buf)),\n+\t\t\t\t\t.byte_count = rte_cpu_to_be_32(\n+\t\t\t\t\t\t\t\tDATA_LEN(buf)),\n \t\t\t\t\t.lkey = mlx5_tx_mb2mr(txq, buf),\n-\t\t\t\t\t.addr = htonll(addr),\n+\t\t\t\t\t.addr = rte_cpu_to_be_64(addr),\n \t\t\t\t};\n #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)\n \t\t\t\tlength += DATA_LEN(buf);\n@@ -1464,7 +1476,7 @@\n \n \t\t\tassert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);\n \t\t\tassert(length == DATA_LEN(buf));\n-\t\t\tinl_hdr = htonl(length | MLX5_INLINE_SEG);\n+\t\t\tinl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);\n \t\t\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n \t\t\tmpw.data.raw = (volatile void *)\n \t\t\t\t((uintptr_t)mpw.data.raw + inl_pad);\n@@ -1520,9 +1532,9 @@\n \t\t\tfor (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)\n \t\t\t\trte_prefetch2((void *)(addr +\n \t\t\t\t\t\tn * RTE_CACHE_LINE_SIZE));\n-\t\t\tnaddr = htonll(addr);\n+\t\t\tnaddr = rte_cpu_to_be_64(addr);\n \t\t\t*dseg = (rte_v128u32_t) {\n-\t\t\t\thtonl(length),\n+\t\t\t\trte_cpu_to_be_32(length),\n \t\t\t\tmlx5_tx_mb2mr(txq, buf),\n \t\t\t\tnaddr,\n \t\t\t\tnaddr >> 32,\n@@ -1550,7 +1562,7 @@\n \t\tvolatile struct mlx5_wqe *wqe = mpw.wqe;\n \n \t\t/* Request completion on last WQE. */\n-\t\twqe->ctrl[2] = htonl(8);\n+\t\twqe->ctrl[2] = rte_cpu_to_be_32(8);\n \t\t/* Save elts_head in unused \"immediate\" field of WQE. */\n \t\twqe->ctrl[3] = elts_head;\n \t\ttxq->elts_comp = 0;\n@@ -1634,8 +1646,8 @@\n \t\t\t(volatile struct mlx5_mini_cqe8 (*)[8])\n \t\t\t(uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);\n \n-\t\tlen = ntohl((*mc)[zip->ai & 7].byte_cnt);\n-\t\t*rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);\n+\t\tlen = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);\n+\t\t*rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);\n \t\tif ((++zip->ai & 7) == 0) {\n \t\t\t/* Invalidate consumed CQEs */\n \t\t\tidx = zip->ca;\n@@ -1683,7 +1695,7 @@\n \t\t\t\t\t\t\t cqe_cnt].pkt_info);\n \n \t\t\t/* Fix endianness. */\n-\t\t\tzip->cqe_cnt = ntohl(cqe->byte_cnt);\n+\t\t\tzip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);\n \t\t\t/*\n \t\t\t * Current mini array position is the one returned by\n \t\t\t * check_cqe64().\n@@ -1698,8 +1710,8 @@\n \t\t\t--rxq->cq_ci;\n \t\t\tzip->cq_ci = rxq->cq_ci + zip->cqe_cnt;\n \t\t\t/* Get packet size to return. */\n-\t\t\tlen = ntohl((*mc)[0].byte_cnt);\n-\t\t\t*rss_hash = ntohl((*mc)[0].rx_hash_result);\n+\t\t\tlen = rte_be_to_cpu_32((*mc)[0].byte_cnt);\n+\t\t\t*rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);\n \t\t\tzip->ai = 1;\n \t\t\t/* Prefetch all the entries to be invalidated */\n \t\t\tidx = zip->ca;\n@@ -1709,8 +1721,8 @@\n \t\t\t\t++idx;\n \t\t\t}\n \t\t} else {\n-\t\t\tlen = ntohl(cqe->byte_cnt);\n-\t\t\t*rss_hash = ntohl(cqe->rx_hash_res);\n+\t\t\tlen = rte_be_to_cpu_32(cqe->byte_cnt);\n+\t\t\t*rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);\n \t\t}\n \t\t/* Error while receiving packet. */\n \t\tif (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))\n@@ -1734,7 +1746,7 @@\n rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)\n {\n \tuint32_t ol_flags = 0;\n-\tuint16_t flags = ntohs(cqe->hdr_type_etc);\n+\tuint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);\n \n \tol_flags =\n \t\tTRANSPOSE(flags,\n@@ -1841,7 +1853,7 @@\n \t\t\t MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {\n \t\t\t\tpkt->ol_flags |= PKT_RX_FDIR;\n \t\t\t\tif (cqe->sop_drop_qpn !=\n-\t\t\t\t htonl(MLX5_FLOW_MARK_DEFAULT)) {\n+\t\t\t\t rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {\n \t\t\t\t\tuint32_t mark = cqe->sop_drop_qpn;\n \n \t\t\t\t\tpkt->ol_flags |= PKT_RX_FDIR_ID;\n@@ -1853,10 +1865,11 @@\n \t\t\t\tpkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);\n \t\t\tif (rxq->vlan_strip &&\n \t\t\t (cqe->hdr_type_etc &\n-\t\t\t htons(MLX5_CQE_VLAN_STRIPPED))) {\n+\t\t\t rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {\n \t\t\t\tpkt->ol_flags |= PKT_RX_VLAN_PKT |\n \t\t\t\t\tPKT_RX_VLAN_STRIPPED;\n-\t\t\t\tpkt->vlan_tci = ntohs(cqe->vlan_info);\n+\t\t\t\tpkt->vlan_tci =\n+\t\t\t\t\trte_be_to_cpu_16(cqe->vlan_info);\n \t\t\t}\n \t\t\tif (rxq->crc_present)\n \t\t\t\tlen -= ETHER_CRC_LEN;\n@@ -1872,7 +1885,7 @@\n \t\t * of the buffers are already known, only the buffer address\n \t\t * changes.\n \t\t */\n-\t\twqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));\n+\t\twqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));\n \t\tif (len > DATA_LEN(seg)) {\n \t\t\tlen -= DATA_LEN(seg);\n \t\t\t++NB_SEGS(pkt);\n@@ -1900,9 +1913,9 @@\n \t/* Update the consumer index. */\n \trxq->rq_ci = rq_ci >> sges_n;\n \trte_wmb();\n-\t*rxq->cq_db = htonl(rxq->cq_ci);\n+\t*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);\n \trte_wmb();\n-\t*rxq->rq_db = htonl(rxq->rq_ci);\n+\t*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);\n #ifdef MLX5_PMD_SOFT_COUNTERS\n \t/* Increment packets counter. */\n \trxq->stats.ipackets += i;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 033e70f..73a4ce8 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -269,7 +269,7 @@ struct txq {\n \t\tuintptr_t start; /* Start address of MR */\n \t\tuintptr_t end; /* End address of MR */\n \t\tstruct ibv_mr *mr; /* Memory Region (for mp). */\n-\t\tuint32_t lkey; /* htonl(mr->lkey) */\n+\t\tuint32_t lkey; /* rte_cpu_to_be_32(mr->lkey) */\n \t} mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */\n \tuint16_t mr_cache_idx; /* Index of last hit entry. */\n \tstruct rte_mbuf *(*elts)[]; /* TX elements. */\n@@ -492,7 +492,7 @@ int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,\n \t}\n #endif /* NDEBUG */\n \t++cq_ci;\n-\ttxq->wqe_pi = ntohs(cqe->wqe_counter);\n+\ttxq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);\n \tctrl = (volatile struct mlx5_wqe_ctrl *)\n \t\ttx_mlx5_wqe(txq, txq->wqe_pi);\n \telts_tail = ctrl->ctrl3;\n@@ -530,7 +530,7 @@ int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,\n \ttxq->elts_tail = elts_tail;\n \t/* Update the consumer index. */\n \trte_wmb();\n-\t*txq->cq_db = htonl(cq_ci);\n+\t*txq->cq_db = rte_cpu_to_be_32(cq_ci);\n }\n \n /**\n@@ -581,7 +581,7 @@ int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,\n \t\tif (txq->mp2mr[i].start <= addr &&\n \t\t txq->mp2mr[i].end >= addr) {\n \t\t\tassert(txq->mp2mr[i].lkey != (uint32_t)-1);\n-\t\t\tassert(htonl(txq->mp2mr[i].mr->lkey) ==\n+\t\t\tassert(rte_cpu_to_be_32(txq->mp2mr[i].mr->lkey) ==\n \t\t\t txq->mp2mr[i].lkey);\n \t\t\ttxq->mr_cache_idx = i;\n \t\t\treturn txq->mp2mr[i].lkey;\n@@ -605,8 +605,8 @@ int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,\n \tuint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);\n \tvolatile uint64_t *src = ((volatile uint64_t *)wqe);\n \n-\trte_io_wmb();\n-\t*txq->qp_db = htonl(txq->wqe_ci);\n+\trte_wmb();\n+\t*txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);\n \t/* Ensure ordering between DB record and BF copy. */\n \trte_wmb();\n \t*dst = *src;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.c b/drivers/net/mlx5/mlx5_rxtx_vec_sse.c\nindex 37854a7..0a5d025 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.c\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.c\n@@ -291,7 +291,7 @@\n \t\t/* Fill ESEG in the header. */\n \t\t_mm_store_si128(t_wqe + 1,\n \t\t\t\t_mm_set_epi16(0, 0, 0, 0,\n-\t\t\t\t\t htons(len), cs_flags,\n+\t\t\t\t\t rte_cpu_to_be_16(len), cs_flags,\n \t\t\t\t\t 0, 0));\n \t\ttxq->wqe_ci = wqe_ci;\n \t}\n@@ -300,7 +300,7 @@\n \ttxq->elts_comp += (uint16_t)(elts_head - txq->elts_head);\n \ttxq->elts_head = elts_head;\n \tif (txq->elts_comp >= MLX5_TX_COMP_THRESH) {\n-\t\twqe->ctrl[2] = htonl(8);\n+\t\twqe->ctrl[2] = rte_cpu_to_be_32(8);\n \t\twqe->ctrl[3] = txq->elts_head;\n \t\ttxq->elts_comp = 0;\n \t\t++txq->cq_pi;\n@@ -561,11 +561,11 @@\n \t\treturn;\n \t}\n \tfor (i = 0; i < n; ++i)\n-\t\twq[i].addr = htonll((uintptr_t)elts[i]->buf_addr +\n-\t\t\t\t RTE_PKTMBUF_HEADROOM);\n+\t\twq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr +\n+\t\t\t\t\t RTE_PKTMBUF_HEADROOM);\n \trxq->rq_ci += n;\n \trte_wmb();\n-\t*rxq->rq_db = htonl(rxq->rq_ci);\n+\t*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);\n }\n \n /**\n@@ -1248,7 +1248,7 @@\n \t\t}\n \t}\n \trte_wmb();\n-\t*rxq->cq_db = htonl(rxq->cq_ci);\n+\t*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);\n \treturn rcvd_pkt;\n }\n \n", "prefixes": [ "dpdk-dev", "1/3" ] }