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Show a patch.
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Update a patch.
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Update a patch.
GET /api/patches/27992/?format=api
{ "id": 27992, "url": "http://patches.dpdk.org/api/patches/27992/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1503675933-13789-1-git-send-email-ravi1.kumar@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1503675933-13789-1-git-send-email-ravi1.kumar@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1503675933-13789-1-git-send-email-ravi1.kumar@amd.com", "date": "2017-08-25T15:45:33", "name": "[dpdk-dev] crypto/ccp: Add support for AMD CCP Crypto poll mode driver", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "3b129d973e8a5cdf7a96ca3a3e9bccc82a5b0ae6", "submitter": { "id": 819, "url": "http://patches.dpdk.org/api/people/819/?format=api", "name": "Kumar, Ravi1", "email": "ravi1.kumar@amd.com" }, "delegate": { "id": 22, "url": "http://patches.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1503675933-13789-1-git-send-email-ravi1.kumar@amd.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/27992/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/27992/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id DE2867D22;\n\tFri, 25 Aug 2017 17:46:14 +0200 (CEST)", "from NAM02-CY1-obe.outbound.protection.outlook.com\n\t(mail-cys01nam02on0054.outbound.protection.outlook.com\n\t[104.47.37.54]) by dpdk.org (Postfix) with ESMTP id DBDEF7D1C\n\tfor <dev@dpdk.org>; Fri, 25 Aug 2017 17:46:12 +0200 (CEST)", "from diesel-25be.amd.com (202.56.249.162) by\n\tCY4PR12MB1126.namprd12.prod.outlook.com (10.168.170.17) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.1.1362.18; Fri, 25 Aug 2017 15:46:06 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amdcloud.onmicrosoft.com; s=selector1-amd-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=p7TaGUAlnerzhKLeSjIUAaobA58MbT/jXzcUXKBtnIs=;\n\tb=nNRkK3M98CtTLuOy4PHeL2G4s4UzRll0ikiUl0GEfyOr4LLJFy//v9dffj0pFZBGuxkibfOzY/xX8Bb8iqP709KJPWupp9c/d98joXP6820ptAxOUtc13h1xBLDzNCbq55sWyr2K4ZykyPMKoakIDelDST1exIZEsJop+MMqaJc=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Ravi1.Kumar@amd.com; ", "From": "Ravi Kumar <ravi1.kumar@amd.com>", "To": "dev@dpdk.org", "Date": "Fri, 25 Aug 2017 21:15:33 +0530", "Message-Id": "<1503675933-13789-1-git-send-email-ravi1.kumar@amd.com>", "X-Mailer": "git-send-email 2.7.4", "MIME-Version": "1.0", "Content-Type": "text/plain; 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SFP:1101; SCL:1; SRVR:CY4PR12MB1126; H:diesel-25be.amd.com;\n\tFPR:; \n\tSPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: amd.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Aug 2017 15:46:06.0904\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1126", "Subject": "[dpdk-dev] [PATCH] crypto/ccp: Add support for AMD CCP Crypto poll\n\tmode driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The CCP poll mode driver library (librte_pmd_ccp) implements support for AMD’s cryptographic co-processor (CCP). The CCP PMD is a virtual crypto poll mode driver which schedules crypto operations to one or more available CCP hardware engines on the platform. The CCP PMD provides poll mode crypto driver support for the following hardware accelerator devices:\n-\tAMD Cryptographic Co-processor (0x1456)\n-\tAMD Cryptographic Co-processor (0x1468)\nThe patchset consists of following algorithms support:\n-\tCipher Algorithm support\no\tRTE_CRYPTO_CIPHER_AES_ECB\no\tRTE_CRYPTO_CIPHER_AES_CBC\no\tRTE_CRYPTO_CIPHER_AES_CTR\no\tRTE_CRYPTO_CIPHER_3DES_CBC\n-\tAuthentication Algorithm support\no\tRTE_CRYPTO_AUTH_SHA1\no\tRTE_CRYPTO_AUTH_SHA1_HMAC\no\tRTE_CRYPTO_AUTH_SHA224\no\tRTE_CRYPTO_AUTH_SHA224_HMAC\no\tRTE_CRYPTO_AUTH_SHA256\no\tRTE_CRYPTO_AUTH_SHA256_HMAC\no\tRTE_CRYPTO_AUTH_SHA384\no\tRTE_CRYPTO_AUTH_SHA384_HMAC\no\tRTE_CRYPTO_AUTH_SHA512\no\tRTE_CRYPTO_AUTH_SHA512_HMAC\no\tRTE_CRYPTO_AUTH_MD5_HMAC\no\tRTE_CRYPTO_AUTH_AES_CMAC\nAddition to crypto Library to support SHA3 authentication algorithm\no\tRTE_CRYPTO_AUTH_SHA3_224\no\tRTE_CRYPTO_AUTH_SHA3_224_HMAC\no\tRTE_CRYPTO_AUTH_SHA3_256\no\tRTE_CRYPTO_AUTH_SHA3_256_HMAC\no\tRTE_CRYPTO_AUTH_SHA3_384\no\tRTE_CRYPTO_AUTH_SHA3_384_HMAC\no\tRTE_CRYPTO_AUTH_SHA3_512\no\tRTE_CRYPTO_AUTH_SHA3_512_HMAC\n-\tAEAD Algorithm Support\no\tRTE_CRYPTO_AEAD_AES_GCM\n\nThe CCP PMD is not enabled by default. Following option can be enabled in DPDK configuration to enable CCP PMD.\nCONFIG_RTE_LIBRTE_PMD_CCP (default n)\n\nSigned-off-by: Ravi Kumar <ravi1.kumar@amd.com>\n---\n MAINTAINERS | 5 +\n config/common_base | 6 +\n doc/guides/cryptodevs/ccp.rst | 126 ++\n doc/guides/cryptodevs/features/ccp.ini | 57 +\n doc/guides/cryptodevs/features/default.ini | 12 +\n doc/guides/cryptodevs/index.rst | 1 +\n drivers/crypto/Makefile | 2 +\n drivers/crypto/ccp/Makefile | 71 +\n drivers/crypto/ccp/ccp_crypto.c | 3008 ++++++++++++++++++++++++++++\n drivers/crypto/ccp/ccp_crypto.h | 411 ++++\n drivers/crypto/ccp/ccp_dev.c | 847 ++++++++\n drivers/crypto/ccp/ccp_dev.h | 533 +++++\n drivers/crypto/ccp/ccp_pci.c | 331 +++\n drivers/crypto/ccp/ccp_pci.h | 58 +\n drivers/crypto/ccp/ccp_pmd_ops.c | 860 ++++++++\n drivers/crypto/ccp/ccp_pmd_private.h | 135 ++\n drivers/crypto/ccp/rte_ccp_pmd.c | 283 +++\n drivers/crypto/ccp/rte_pmd_ccp_version.map | 3 +\n lib/librte_cryptodev/rte_crypto_sym.h | 18 +\n mk/rte.app.mk | 1 +\n 20 files changed, 6768 insertions(+)\n create mode 100644 doc/guides/cryptodevs/ccp.rst\n create mode 100644 doc/guides/cryptodevs/features/ccp.ini\n create mode 100644 drivers/crypto/ccp/Makefile\n create mode 100644 drivers/crypto/ccp/ccp_crypto.c\n create mode 100644 drivers/crypto/ccp/ccp_crypto.h\n create mode 100644 drivers/crypto/ccp/ccp_dev.c\n create mode 100644 drivers/crypto/ccp/ccp_dev.h\n create mode 100644 drivers/crypto/ccp/ccp_pci.c\n create mode 100644 drivers/crypto/ccp/ccp_pci.h\n create mode 100644 drivers/crypto/ccp/ccp_pmd_ops.c\n create mode 100644 drivers/crypto/ccp/ccp_pmd_private.h\n create mode 100644 drivers/crypto/ccp/rte_ccp_pmd.c\n create mode 100644 drivers/crypto/ccp/rte_pmd_ccp_version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex a0cd75e..cce6bce 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -586,6 +586,11 @@ M: Fan Zhang <roy.fan.zhang@intel.com>\n F: drivers/crypto/scheduler/\n F: doc/guides/cryptodevs/scheduler.rst\n \n+AMD CCP Crypto PMD \n+M: Ravi Kumar <Ravi1.Kumar@amd.com>\n+F: drivers/crypto/ccp/\n+F: doc/guides/cryptodevs/ccp.rst\n+F: doc/guides/cryptodevs/features/ccp.ini\n \n Eventdev Drivers\n ----------------\ndiff --git a/config/common_base b/config/common_base\nindex 5e97a08..3353e19 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -514,6 +514,12 @@ CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n\n CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y\n \n #\n+# Compile PMD for AMD CCP crypto device\n+#\n+CONFIG_RTE_LIBRTE_PMD_CCP=n\n+CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=n\n+\n+#\n # Compile generic event device library\n #\n CONFIG_RTE_LIBRTE_EVENTDEV=y\ndiff --git a/doc/guides/cryptodevs/ccp.rst b/doc/guides/cryptodevs/ccp.rst\nnew file mode 100644\nindex 0000000..83343fe\n--- /dev/null\n+++ b/doc/guides/cryptodevs/ccp.rst\n@@ -0,0 +1,126 @@\n+.. BSD LICENSE\n+ Copyright(c) 2017 Advance Micro Devices, Inc.\n+ All rights reserved.\n+\n+ Redistribution and use in source and binary forms, with or without\n+ modification, are permitted provided that the following conditions\n+ are met:\n+\n+ * Redistributions of source code must retain the above copyright\n+ notice, this list of conditions and the following disclaimer.\n+ * Redistributions in binary form must reproduce the above copyright\n+ notice, this list of conditions and the following disclaimer in\n+ the documentation and/or other materials provided with the\n+ distribution.\n+ * Neither the name of Advance Micro Devices, Inc nor the names of\n+ its contributors may be used to endorse or promote products derived\n+ from this software without specific prior written permission.\n+\n+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+AMD CCP Poll Mode Driver\n+========================\n+\n+This code provides the initial implementation of the ccp poll mode driver.\n+The CCP poll mode driver library (librte_pmd_ccp) implements support for\n+AMD’s cryptographic co-processor (CCP). The CCP PMD is a virtual crypto\n+poll mode driver which schedules crypto operations to one or more available\n+CCP hardware engines on the platform. The CCP PMD provides poll mode crypto\n+driver support for the following hardware accelerator devices::\n+\n+\tAMD Cryptographic Co-processor (0x1456)\n+\tAMD Cryptographic Co-processor (0x1468)\n+\n+Features\n+--------\n+\n+CCP PMD has support for:\n+\n+Supported cipher algorithms:\n+* ``RTE_CRYPTO_CIPHER_AES_CBC``\n+* ``RTE_CRYPTO_CIPHER_AES_ECB``\n+* ``RTE_CRYPTO_CIPHER_AES_CTR``\n+* ``RTE_CRYPTO_CIPHER_3DES_CBC``\n+\n+Supported authentication algorithms:\n+* ``RTE_CRYPTO_AUTH_SHA1``\n+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA224``\n+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA256``\n+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA384``\n+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA512``\n+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``\n+* ``RTE_CRYPTO_AUTH_MD5_HMAC``\n+* ``RTE_CRYPTO_AUTH_AES_CMAC``\n+* ``RTE_CRYPTO_AUTH_SHA3_224``\n+* ``RTE_CRYPTO_AUTH_SHA3_224_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA3_256``\n+* ``RTE_CRYPTO_AUTH_SHA3_256_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA3_384``\n+* ``RTE_CRYPTO_AUTH_SHA3_384_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA3_512``\n+* ``RTE_CRYPTO_AUTH_SHA3_512_HMAC``\n+\n+Supported AEAD algorithms:\n+* ``RTE_CRYPTO_AEAD_AES_GCM``\n+\n+Installation\n+------------\n+\n+To compile CCP PMD, it has to be enabled in the config/common_base file.\n+* ``CONFIG_RTE_LIBRTE_PMD_CCP=y``\n+\n+The CCP PMD also supports computing authentication over CPU with cipher offloaded\n+to CCP. To enable this feature, enable following in the configuration.\n+* ``CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y``\n+\n+This code was verified on Ubuntu 16.04.\n+\n+Initialization\n+--------------\n+\n+Bind the CCP devices to DPDK UIO driver module before running the CCP PMD stack.\n+e.g. for the 0x1456 device::\n+\n+\tcd to the top-level DPDK directory\n+\tmodprobe uio\n+\tinsmod ./build/kmod/igb_uio.ko\n+\techo \"1022 1456\" > /sys/bus/pci/drivers/igb_uio/new_id\n+\n+Another way to bind the CCP devices to DPDK UIO driver is by using the ``dpdk-devbind.py`` script.\n+The following command assumes ``BFD`` of ``0000:09:00.2``::\n+\n+\tcd to the top-level DPDK directory\n+\t./usertools/dpdk-devbind.py -b igb_uio 0000:09:00.2\n+\n+To verify real traffic l2fwd-crypto example can be used with following command:\n+\n+.. code-block:: console\n+\n+\tsudo ./build/l2fwd-crypto -l 1 -n 4 --vdev \"crypto_ccp\" -- -p 0x1\n+\t--chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo AES_CBC\n+\t--cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f\n+\t--iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff\n+\t--auth_op GENERATE --auth_algo SHA1_HMAC\n+\t--auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11\n+\t:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11\n+\t:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11\n+\n+Limitations\n+-----------\n+\n+* Chained mbufs are not supported\n+* MD5_HMAC is supported only if ``CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y`` is enabled in configuration\ndiff --git a/doc/guides/cryptodevs/features/ccp.ini b/doc/guides/cryptodevs/features/ccp.ini\nnew file mode 100644\nindex 0000000..6184a67\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/ccp.ini\n@@ -0,0 +1,57 @@\n+;\n+; Supported features of the 'ccp' crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Symmetric crypto = Y\n+Sym operation chaining = Y\n+HW Accelerated = Y\n+\n+;\n+; Supported crypto algorithms of the 'ccp' crypto driver.\n+;\n+[Cipher]\n+AES CBC (128) = Y\n+AES CBC (192) = Y\n+AES CBC (256) = Y\n+AES ECB (128) = Y\n+AES ECB (192) = Y\n+AES ECB (256) = Y\n+AES CTR (128) = Y\n+AES CTR (192) = Y\n+AES CTR (256) = Y\n+3DES CBC = Y\n+\n+;\n+; Supported authentication algorithms of the 'ccp' crypto driver.\n+;\n+[Auth]\n+MD5 HMAC = Y\n+SHA1 = Y\n+SHA1 HMAC = Y\n+SHA224\t = Y\n+SHA224 HMAC = Y\n+SHA256 = Y\n+SHA256 HMAC = Y\n+SHA384 = Y\n+SHA384 HMAC = Y\n+SHA512 = Y\n+SHA512 HMAC = Y\n+AES CMAC = Y\n+SHA3_224 = Y\n+SHA3_224 HMAC = Y\n+SHA3_256 = Y\n+SHA3_256 HMAC = Y\n+SHA3_384 = Y\n+SHA3_384 HMAC = Y\n+SHA3_512 = Y\n+SHA3_512 HMAC = Y\n+\n+;\n+; Supported AEAD algorithms of the 'ccp' crypto driver.\n+;\n+[AEAD]\n+AES GCM (128) = Y\n+AES GCM (192) = Y\n+AES GCM (256) = Y\ndiff --git a/doc/guides/cryptodevs/features/default.ini b/doc/guides/cryptodevs/features/default.ini\nindex 0926887..d09943f 100644\n--- a/doc/guides/cryptodevs/features/default.ini\n+++ b/doc/guides/cryptodevs/features/default.ini\n@@ -26,6 +26,9 @@ NULL =\n AES CBC (128) =\n AES CBC (192) =\n AES CBC (256) =\n+AES ECB (128) =\n+AES ECB (192) =\n+AES ECB (256) =\n AES CTR (128) =\n AES CTR (192) =\n AES CTR (256) =\n@@ -60,6 +63,15 @@ AES GMAC =\n SNOW3G UIA2 =\n KASUMI F9 =\n ZUC EIA3 =\n+AES CMAC =\n+SHA3_224 = \n+SHA3_224 HMAC=\n+SHA3_256 =\n+SHA3_256 HMAC=\n+SHA3_384 =\n+SHA3_384 HMAC=\n+SHA3_512 =\n+SHA3_512 HMAC=\n \n ;\n ; Supported AEAD algorithms of a default crypto driver.\ndiff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst\nindex 361b82d..f31c978 100644\n--- a/doc/guides/cryptodevs/index.rst\n+++ b/doc/guides/cryptodevs/index.rst\n@@ -39,6 +39,7 @@ Crypto Device Drivers\n aesni_mb\n aesni_gcm\n armv8\n+ ccp\n dpaa2_sec\n kasumi\n openssl\ndiff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile\nindex 7a719b9..3505649 100644\n--- a/drivers/crypto/Makefile\n+++ b/drivers/crypto/Makefile\n@@ -55,5 +55,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO) += null\n DEPDIRS-null = $(core-libs)\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC) += dpaa2_sec\n DEPDIRS-dpaa2_sec = $(core-libs)\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp\n+DEPDIRS-ccp = $(core-libs)\n \n include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/crypto/ccp/Makefile b/drivers/crypto/ccp/Makefile\nnew file mode 100644\nindex 0000000..8b6a15a\n--- /dev/null\n+++ b/drivers/crypto/ccp/Makefile\n@@ -0,0 +1,71 @@\n+# BSD LICENSE\n+#\n+# Copyright(c) 2017 Advance Micro Devices, Inc. All rights reserved.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of Advance Micro Devices, Inc nor the names\n+# of its contributors may be used to endorse or promote products\n+# derived from this software without specific prior written\n+#\tpermission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+\n+# library name\n+LIB = librte_pmd_ccp.a\n+\n+# build flags\n+CFLAGS += -O3\n+CFLAGS += -I$(SRCDIR)\n+CFLAGS += $(WERROR_FLAGS)\n+\n+# library version\n+LIBABIVER := 1\n+\n+# external library include paths\n+LDLIBS += -lcrypto\n+LDLIBS += -lpthread\n+LDLIBS += -lcrypto\n+\n+# versioning export map\n+EXPORT_MAP := rte_pmd_ccp_version.map\n+\n+# library source files\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += rte_ccp_pmd.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_crypto.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_dev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_pci.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_pmd_ops.c\n+\n+# export include files\n+SYMLINK-y-include +=\n+\n+# library dependencies\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += lib/librte_eal\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += lib/librte_mbuf\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += lib/librte_mempool\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += lib/librte_ring\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += lib/librte_cryptodev\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/ccp/ccp_crypto.c b/drivers/crypto/ccp/ccp_crypto.c\nnew file mode 100644\nindex 0000000..63da1cd\n--- /dev/null\n+++ b/drivers/crypto/ccp/ccp_crypto.c\n@@ -0,0 +1,3008 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2017 Advance Micro Devices, Inc. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Advance Micro Devices, Inc nor the names\n+ * of its contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written\n+ * permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <dirent.h>\n+#include <fcntl.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <sys/mman.h>\n+#include <sys/queue.h>\n+#include <sys/types.h>\n+#include <unistd.h>\n+\n+#include <rte_hexdump.h>\n+#include <rte_memzone.h>\n+#include <rte_malloc.h>\n+#include <rte_memory.h>\n+#include <rte_spinlock.h>\n+#include <rte_string_fns.h>\n+#include <rte_cryptodev_pmd.h>\n+\n+#include <ccp_dev.h>\n+#include <ccp_crypto.h>\n+#include <ccp_pci.h>\n+#include <ccp_pmd_private.h>\n+\n+#include <openssl/sha.h> /*partial hash apis*/\n+#include <openssl/cmac.h> /*sub key apis*/\n+#include <openssl/evp.h> /*sub key apis*/\n+\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+#include <openssl/conf.h>\n+#include <openssl/err.h>\n+#include <openssl/hmac.h>\n+#endif\n+\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+/* SHA initial context values */\n+static uint32_t ccp_sha1_init[SHA256_DIGEST_SIZE / sizeof(uint32_t)] = {\n+\tSHA1_H4, SHA1_H3,\n+\tSHA1_H2, SHA1_H1,\n+\tSHA1_H0, 0x0U,\n+\t0x0U, 0x0U,\n+};\n+\n+uint32_t ccp_sha224_init[SHA256_DIGEST_SIZE / sizeof(uint32_t)] = {\n+\tSHA224_H7, SHA224_H6,\n+\tSHA224_H5, SHA224_H4,\n+\tSHA224_H3, SHA224_H2,\n+\tSHA224_H1, SHA224_H0,\n+};\n+\n+uint32_t ccp_sha256_init[SHA256_DIGEST_SIZE / sizeof(uint32_t)] = {\n+\tSHA256_H7, SHA256_H6,\n+\tSHA256_H5, SHA256_H4,\n+\tSHA256_H3, SHA256_H2,\n+\tSHA256_H1, SHA256_H0,\n+};\n+\n+uint64_t ccp_sha384_init[SHA512_DIGEST_SIZE / sizeof(uint64_t)] = {\n+\tSHA384_H7, SHA384_H6,\n+\tSHA384_H5, SHA384_H4,\n+\tSHA384_H3, SHA384_H2,\n+\tSHA384_H1, SHA384_H0,\n+};\n+\n+uint64_t ccp_sha512_init[SHA512_DIGEST_SIZE / sizeof(uint64_t)] = {\n+\tSHA512_H7, SHA512_H6,\n+\tSHA512_H5, SHA512_H4,\n+\tSHA512_H3, SHA512_H2,\n+\tSHA512_H1, SHA512_H0,\n+};\n+#endif\n+\n+extern uint8_t cryptodev_driver_id;\n+\n+#if defined(_MSC_VER)\n+#define SHA3_CONST(x) x\n+#else\n+#define SHA3_CONST(x) x##L\n+#endif\n+\n+/** 'Words' here refers to uint64_t */\n+#define SHA3_KECCAK_SPONGE_WORDS \\\n+\t(((1600) / 8) / sizeof(uint64_t))\n+typedef struct sha3_context_ {\n+\tuint64_t saved;\n+\t/**\n+\t * The portion of the input message that we\n+\t * didn't consume yet\n+\t */\n+\tunion {\n+\t\tuint64_t s[SHA3_KECCAK_SPONGE_WORDS];\n+\t\t/* Keccak's state */\n+\t\tuint8_t sb[SHA3_KECCAK_SPONGE_WORDS * 8];\n+\t\t/**total 200 ctx size**/\n+\t};\n+\tunsigned int byteIndex;\n+\t/**\n+\t * 0..7--the next byte after the set one\n+\t * (starts from 0; 0--none are buffered)\n+\t */\n+\tunsigned int wordIndex;\n+\t/**\n+\t * 0..24--the next word to integrate input\n+\t * (starts from 0)\n+\t */\n+\tunsigned int capacityWords;\n+\t/**\n+\t * the double size of the hash output in\n+\t * words (e.g. 16 for Keccak 512)\n+\t */\n+} sha3_context;\n+\n+#ifndef SHA3_ROTL64\n+#define SHA3_ROTL64(x, y) \\\n+\t(((x) << (y)) | ((x) >> ((sizeof(uint64_t)*8) - (y))))\n+#endif\n+\n+static const uint64_t keccakf_rndc[24] = {\n+\tSHA3_CONST(0x0000000000000001UL), SHA3_CONST(0x0000000000008082UL),\n+\tSHA3_CONST(0x800000000000808aUL), SHA3_CONST(0x8000000080008000UL),\n+\tSHA3_CONST(0x000000000000808bUL), SHA3_CONST(0x0000000080000001UL),\n+\tSHA3_CONST(0x8000000080008081UL), SHA3_CONST(0x8000000000008009UL),\n+\tSHA3_CONST(0x000000000000008aUL), SHA3_CONST(0x0000000000000088UL),\n+\tSHA3_CONST(0x0000000080008009UL), SHA3_CONST(0x000000008000000aUL),\n+\tSHA3_CONST(0x000000008000808bUL), SHA3_CONST(0x800000000000008bUL),\n+\tSHA3_CONST(0x8000000000008089UL), SHA3_CONST(0x8000000000008003UL),\n+\tSHA3_CONST(0x8000000000008002UL), SHA3_CONST(0x8000000000000080UL),\n+\tSHA3_CONST(0x000000000000800aUL), SHA3_CONST(0x800000008000000aUL),\n+\tSHA3_CONST(0x8000000080008081UL), SHA3_CONST(0x8000000000008080UL),\n+\tSHA3_CONST(0x0000000080000001UL), SHA3_CONST(0x8000000080008008UL)\n+};\n+\n+static const unsigned int keccakf_rotc[24] = {\n+\t1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 2, 14, 27, 41, 56, 8, 25, 43, 62,\n+\t18, 39, 61, 20, 44\n+};\n+\n+static const unsigned int keccakf_piln[24] = {\n+\t10, 7, 11, 17, 18, 3, 5, 16, 8, 21, 24, 4, 15, 23, 19, 13, 12, 2, 20,\n+\t14, 22, 9, 6, 1\n+};\n+\n+static enum ccp_cmd_order\n+ccp_get_cmd_id(const struct rte_crypto_sym_xform *xform)\n+{\n+\tenum ccp_cmd_order res = CCP_CMD_NOT_SUPPORTED;\n+\n+\tif (xform == NULL)\n+\t\treturn res;\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) {\n+\t\tif (xform->next == NULL)\n+\t\t\treturn CCP_CMD_AUTH;\n+\t\telse if (xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)\n+\t\t\treturn CCP_CMD_HASH_CIPHER;\n+\t}\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {\n+\t\tif (xform->next == NULL)\n+\t\t\treturn CCP_CMD_CIPHER;\n+\t\telse if (xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)\n+\t\t\treturn CCP_CMD_CIPHER_HASH;\n+\t}\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)\n+\t\treturn CCP_CMD_COMBINED;\n+\treturn res;\n+}\n+\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+/**partial hash using openssl*/\n+static int partial_hash_sha1(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tSHA_CTX ctx;\n+\n+\tif (!SHA1_Init(&ctx))\n+\t\treturn -EFAULT;\n+\tSHA1_Transform(&ctx, data_in);\n+\trte_memcpy(data_out, &ctx, SHA_DIGEST_LENGTH);\n+\treturn 0;\n+}\n+\n+static int partial_hash_sha224(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tSHA256_CTX ctx;\n+\n+\tif (!SHA224_Init(&ctx))\n+\t\treturn -EFAULT;\n+\tSHA256_Transform(&ctx, data_in);\n+\trte_memcpy(data_out, &ctx,\n+\t\t SHA256_DIGEST_LENGTH);\n+\treturn 0;\n+}\n+\n+static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tSHA256_CTX ctx;\n+\n+\tif (!SHA256_Init(&ctx))\n+\t\treturn -EFAULT;\n+\tSHA256_Transform(&ctx, data_in);\n+\trte_memcpy(data_out, &ctx,\n+\t\t SHA256_DIGEST_LENGTH);\n+\treturn 0;\n+}\n+\n+static int partial_hash_sha384(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tSHA512_CTX ctx;\n+\n+\tif (!SHA384_Init(&ctx))\n+\t\treturn -EFAULT;\n+\tSHA512_Transform(&ctx, data_in);\n+\trte_memcpy(data_out, &ctx,\n+\t\t SHA512_DIGEST_LENGTH);\n+\treturn 0;\n+}\n+\n+static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tSHA512_CTX ctx;\n+\n+\tif (!SHA512_Init(&ctx))\n+\t\treturn -EFAULT;\n+\tSHA512_Transform(&ctx, data_in);\n+\trte_memcpy(data_out, &ctx,\n+\t\t SHA512_DIGEST_LENGTH);\n+\treturn 0;\n+}\n+#endif\n+\n+static void\n+keccakf(uint64_t s[25])\n+{\n+\tint i, j, round;\n+\tuint64_t t, bc[5];\n+#define KECCAK_ROUNDS 24\n+\n+\tfor (round = 0; round < KECCAK_ROUNDS; round++) {\n+\n+\t\t/* Theta */\n+\t\tfor (i = 0; i < 5; i++)\n+\t\t\tbc[i] = s[i] ^ s[i + 5] ^ s[i + 10] ^ s[i + 15] ^\n+\t\t\t\ts[i + 20];\n+\n+\t\tfor (i = 0; i < 5; i++) {\n+\t\t\tt = bc[(i + 4) % 5] ^ SHA3_ROTL64(bc[(i + 1) % 5], 1);\n+\t\t\tfor (j = 0; j < 25; j += 5)\n+\t\t\t\ts[j + i] ^= t;\n+\t\t}\n+\n+\t\t/* Rho Pi */\n+\t\tt = s[1];\n+\t\tfor (i = 0; i < 24; i++) {\n+\t\t\tj = keccakf_piln[i];\n+\t\t\tbc[0] = s[j];\n+\t\t\ts[j] = SHA3_ROTL64(t, keccakf_rotc[i]);\n+\t\t\tt = bc[0];\n+\t\t}\n+\n+\t\t/* Chi */\n+\t\tfor (j = 0; j < 25; j += 5) {\n+\t\t\tfor (i = 0; i < 5; i++)\n+\t\t\t\tbc[i] = s[j + i];\n+\t\t\tfor (i = 0; i < 5; i++)\n+\t\t\t\ts[j + i] ^= (~bc[(i + 1) % 5]) &\n+\t\t\t\t\t bc[(i + 2) % 5];\n+\t\t}\n+\n+\t\t/* Iota */\n+\t\ts[0] ^= keccakf_rndc[round];\n+\t}\n+}\n+\n+static void\n+sha3_Init224(void *priv)\n+{\n+\tsha3_context *ctx = (sha3_context *) priv;\n+\n+\tmemset(ctx, 0, sizeof(*ctx));\n+\tctx->capacityWords = 2 * 224 / (8 * sizeof(uint64_t));\n+}\n+\n+static void\n+sha3_Init256(void *priv)\n+{\n+\tsha3_context *ctx = (sha3_context *) priv;\n+\n+\tmemset(ctx, 0, sizeof(*ctx));\n+\tctx->capacityWords = 2 * 256 / (8 * sizeof(uint64_t));\n+}\n+\n+static void\n+sha3_Init384(void *priv)\n+{\n+\tsha3_context *ctx = (sha3_context *) priv;\n+\n+\tmemset(ctx, 0, sizeof(*ctx));\n+\tctx->capacityWords = 2 * 384 / (8 * sizeof(uint64_t));\n+}\n+\n+static void\n+sha3_Init512(void *priv)\n+{\n+\tsha3_context *ctx = (sha3_context *) priv;\n+\n+\tmemset(ctx, 0, sizeof(*ctx));\n+\tctx->capacityWords = 2 * 512 / (8 * sizeof(uint64_t));\n+}\n+\n+\n+/* This is simply the 'update' with the padding block.\n+ * The padding block is 0x01 || 0x00* || 0x80. First 0x01 and last 0x80\n+ * bytes are always present, but they can be the same byte.\n+ */\n+static void\n+sha3_Update(void *priv, void const *bufIn, size_t len)\n+{\n+\tsha3_context *ctx = (sha3_context *) priv;\n+\tunsigned int old_tail = (8 - ctx->byteIndex) & 7;\n+\tsize_t words;\n+\tunsigned int tail;\n+\tsize_t i;\n+\tconst uint8_t *buf = bufIn;\n+\n+\tif (len < old_tail) {\n+\t\twhile (len--)\n+\t\t\tctx->saved |= (uint64_t) (*(buf++)) <<\n+\t\t\t\t ((ctx->byteIndex++) * 8);\n+\t\treturn;\n+\t}\n+\n+\tif (old_tail) {\n+\t\tlen -= old_tail;\n+\t\twhile (old_tail--)\n+\t\t\tctx->saved |= (uint64_t) (*(buf++)) <<\n+\t\t\t\t ((ctx->byteIndex++) * 8);\n+\n+\t\tctx->s[ctx->wordIndex] ^= ctx->saved;\n+\t\tctx->byteIndex = 0;\n+\t\tctx->saved = 0;\n+\t\tif (++ctx->wordIndex ==\n+\t\t (SHA3_KECCAK_SPONGE_WORDS - ctx->capacityWords)) {\n+\t\t\tkeccakf(ctx->s);\n+\t\t\tctx->wordIndex = 0;\n+\t\t}\n+\t}\n+\n+\twords = len / sizeof(uint64_t);\n+\ttail = len - words * sizeof(uint64_t);\n+\n+\tfor (i = 0; i < words; i++, buf += sizeof(uint64_t)) {\n+\t\tconst uint64_t t = (uint64_t) (buf[0]) |\n+\t\t\t((uint64_t) (buf[1]) << 8 * 1) |\n+\t\t\t((uint64_t) (buf[2]) << 8 * 2) |\n+\t\t\t((uint64_t) (buf[3]) << 8 * 3) |\n+\t\t\t((uint64_t) (buf[4]) << 8 * 4) |\n+\t\t\t((uint64_t) (buf[5]) << 8 * 5) |\n+\t\t\t((uint64_t) (buf[6]) << 8 * 6) |\n+\t\t\t((uint64_t) (buf[7]) << 8 * 7);\n+\t\tctx->s[ctx->wordIndex] ^= t;\n+\t\tif (++ctx->wordIndex ==\n+\t\t (SHA3_KECCAK_SPONGE_WORDS - ctx->capacityWords)) {\n+\t\t\tkeccakf(ctx->s);\n+\t\t\tctx->wordIndex = 0;\n+\t\t}\n+\t}\n+\n+\twhile (tail--)\n+\t\tctx->saved |= (uint64_t) (*(buf++)) << ((ctx->byteIndex++) * 8);\n+}\n+\n+int partial_hash_sha3_224(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tsha3_context *ctx;\n+\tint i;\n+\n+\tctx = rte_zmalloc(\"sha3-ctx\", sizeof(sha3_context), 0);\n+\tif (!ctx) {\n+\t\tCCP_LOG_ERR(\"sha3-ctx creation failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tsha3_Init224(ctx);\n+\tsha3_Update(ctx, data_in, SHA3_224_BLOCK_SIZE);\n+\tfor (i = 0; i < CCP_SHA3_CTX_SIZE; i++, data_out++)\n+\t\t*data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i - 1];\n+\trte_free(ctx);\n+\n+\treturn 0;\n+}\n+\n+int partial_hash_sha3_256(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tsha3_context *ctx;\n+\tint i;\n+\n+\tctx = rte_zmalloc(\"sha3-ctx\", sizeof(sha3_context), 0);\n+\tif (!ctx) {\n+\t\tCCP_LOG_ERR(\"sha3-ctx creation failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tsha3_Init256(ctx);\n+\tsha3_Update(ctx, data_in, SHA3_256_BLOCK_SIZE);\n+\tfor (i = 0; i < CCP_SHA3_CTX_SIZE; i++, data_out++)\n+\t\t*data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i - 1];\n+\trte_free(ctx);\n+\n+\treturn 0;\n+}\n+\n+int partial_hash_sha3_384(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tsha3_context *ctx;\n+\tint i;\n+\n+\tctx = rte_zmalloc(\"sha3-ctx\", sizeof(sha3_context), 0);\n+\tif (!ctx) {\n+\t\tCCP_LOG_ERR(\"sha3-ctx creation failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tsha3_Init384(ctx);\n+\tsha3_Update(ctx, data_in, SHA3_384_BLOCK_SIZE);\n+\tfor (i = 0; i < CCP_SHA3_CTX_SIZE; i++, data_out++)\n+\t\t*data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i - 1];\n+\trte_free(ctx);\n+\n+\treturn 0;\n+}\n+\n+int partial_hash_sha3_512(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tsha3_context *ctx;\n+\tint i;\n+\n+\tctx = rte_zmalloc(\"sha3-ctx\", sizeof(sha3_context), 0);\n+\tif (!ctx) {\n+\t\tCCP_LOG_ERR(\"sha3-ctx creation failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tsha3_Init512(ctx);\n+\tsha3_Update(ctx, data_in, SHA3_512_BLOCK_SIZE);\n+\tfor (i = 0; i < CCP_SHA3_CTX_SIZE; i++, data_out++)\n+\t\t*data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i - 1];\n+\trte_free(ctx);\n+\n+\treturn 0;\n+}\n+\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+static int generate_partial_hash(struct ccp_session *sess)\n+{\n+\n+\tuint8_t ipad[sess->auth.block_size];\n+\tuint8_t\topad[sess->auth.block_size];\n+\tuint8_t *ipad_t, *opad_t;\n+\tuint32_t *hash_value_be32, hash_temp32[8];\n+\tuint64_t *hash_value_be64, hash_temp64[8];\n+\tint i, count;\n+\tuint8_t *hash_value_sha3;\n+\n+\topad_t = ipad_t = (uint8_t *)sess->auth.key;\n+\n+\thash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute);\n+\thash_value_be64 = (uint64_t *)((uint8_t *)sess->auth.pre_compute);\n+\n+\t/**considering key size is always equal to block size of algorithm*/\n+\tfor (i = 0; i < sess->auth.block_size; i++) {\n+\t\tipad[i] = (ipad_t[i] ^ HMAC_IPAD_VALUE);\n+\t\topad[i] = (opad_t[i] ^ HMAC_OPAD_VALUE);\n+\t}\n+\n+\tswitch (sess->auth.algo) {\n+\tcase CCP_AUTH_ALGO_SHA1_HMAC:\n+\t\tcount = SHA1_DIGEST_SIZE >> 2;\n+\n+\t\tif (partial_hash_sha1(ipad, (uint8_t *)hash_temp32))\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < count; i++, hash_value_be32++)\n+\t\t\t*hash_value_be32 = hash_temp32[count - 1 - i];\n+\n+\t\thash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute\n+\t\t\t\t\t + sess->auth.ctx_len);\n+\t\tif (partial_hash_sha1(opad, (uint8_t *)hash_temp32))\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < count; i++, hash_value_be32++)\n+\t\t\t*hash_value_be32 = hash_temp32[count - 1 - i];\n+\t\treturn 0;\n+\tcase CCP_AUTH_ALGO_SHA224_HMAC:\n+\t\tcount = SHA256_DIGEST_SIZE >> 2;\n+\n+\t\tif (partial_hash_sha224(ipad, (uint8_t *)hash_temp32))\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < count; i++, hash_value_be32++)\n+\t\t\t*hash_value_be32 = hash_temp32[count - 1 - i];\n+\n+\t\thash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute\n+\t\t\t\t\t + sess->auth.ctx_len);\n+\t\tif (partial_hash_sha224(opad, (uint8_t *)hash_temp32))\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < count; i++, hash_value_be32++)\n+\t\t\t*hash_value_be32 = hash_temp32[count - 1 - i];\n+\t\treturn 0;\n+\tcase CCP_AUTH_ALGO_SHA3_224_HMAC:\n+\t\thash_value_sha3 = sess->auth.pre_compute;\n+\t\tif (partial_hash_sha3_224(ipad, hash_value_sha3))\n+\t\t\treturn -1;\n+\n+\t\thash_value_sha3 = (uint8_t *)(sess->auth.pre_compute\n+\t\t\t\t\t + sess->auth.ctx_len);\n+\t\tif (partial_hash_sha3_224(opad, hash_value_sha3))\n+\t\t\treturn -1;\n+\t\treturn 0;\n+\tcase CCP_AUTH_ALGO_SHA256_HMAC:\n+\t\tcount = SHA256_DIGEST_SIZE >> 2;\n+\n+\t\tif (partial_hash_sha256(ipad, (uint8_t *)hash_temp32))\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < count; i++, hash_value_be32++)\n+\t\t\t*hash_value_be32 = hash_temp32[count - 1 - i];\n+\n+\t\thash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute\n+\t\t\t\t\t + sess->auth.ctx_len);\n+\t\tif (partial_hash_sha256(opad, (uint8_t *)hash_temp32))\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < count; i++, hash_value_be32++)\n+\t\t\t*hash_value_be32 = hash_temp32[count - 1 - i];\n+\t\treturn 0;\n+\tcase CCP_AUTH_ALGO_SHA3_256_HMAC:\n+\t\thash_value_sha3 = sess->auth.pre_compute;\n+\t\tif (partial_hash_sha3_256(ipad, hash_value_sha3))\n+\t\t\treturn -1;\n+\n+\t\thash_value_sha3 = (uint8_t *)(sess->auth.pre_compute\n+\t\t\t\t\t + sess->auth.ctx_len);\n+\t\tif (partial_hash_sha3_256(opad, hash_value_sha3))\n+\t\t\treturn -1;\n+\t\treturn 0;\n+\tcase CCP_AUTH_ALGO_SHA384_HMAC:\n+\t\tcount = SHA512_DIGEST_SIZE >> 3;\n+\n+\t\tif (partial_hash_sha384(ipad, (uint8_t *)hash_temp64))\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < count; i++, hash_value_be64++)\n+\t\t\t*hash_value_be64 = hash_temp64[count - 1 - i];\n+\n+\t\thash_value_be64 = (uint64_t *)((uint8_t *)sess->auth.pre_compute\n+\t\t\t\t\t + sess->auth.ctx_len);\n+\t\tif (partial_hash_sha384(opad, (uint8_t *)hash_temp64))\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < count; i++, hash_value_be64++)\n+\t\t\t*hash_value_be64 = hash_temp64[count - 1 - i];\n+\t\treturn 0;\n+\tcase CCP_AUTH_ALGO_SHA3_384_HMAC:\n+\t\thash_value_sha3 = sess->auth.pre_compute;\n+\t\tif (partial_hash_sha3_384(ipad, hash_value_sha3))\n+\t\t\treturn -1;\n+\n+\t\thash_value_sha3 = (uint8_t *)(sess->auth.pre_compute\n+\t\t\t\t\t + sess->auth.ctx_len);\n+\t\tif (partial_hash_sha3_384(opad, hash_value_sha3))\n+\t\t\treturn -1;\n+\t\treturn 0;\n+\tcase CCP_AUTH_ALGO_SHA512_HMAC:\n+\t\tcount = SHA512_DIGEST_SIZE >> 3;\n+\n+\t\tif (partial_hash_sha512(ipad, (uint8_t *)hash_temp64))\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < count; i++, hash_value_be64++)\n+\t\t\t*hash_value_be64 = hash_temp64[count - 1 - i];\n+\n+\t\thash_value_be64 = (uint64_t *)((uint8_t *)sess->auth.pre_compute\n+\t\t\t\t\t + sess->auth.ctx_len);\n+\t\tif (partial_hash_sha512(opad, (uint8_t *)hash_temp64))\n+\t\t\treturn -1;\n+\t\tfor (i = 0; i < count; i++, hash_value_be64++)\n+\t\t\t*hash_value_be64 = hash_temp64[count - 1 - i];\n+\t\treturn 0;\n+\tcase CCP_AUTH_ALGO_SHA3_512_HMAC:\n+\t\thash_value_sha3 = sess->auth.pre_compute;\n+\t\tif (partial_hash_sha3_512(ipad, hash_value_sha3))\n+\t\t\treturn -1;\n+\n+\t\thash_value_sha3 = (uint8_t *)(sess->auth.pre_compute\n+\t\t\t\t\t + sess->auth.ctx_len);\n+\t\tif (partial_hash_sha3_512(opad, hash_value_sha3))\n+\t\t\treturn -1;\n+\t\treturn 0;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Invalid session algo\");\n+\t\treturn -1;\n+\t}\n+}\n+\n+/* prepare temporary keys K1 and K2 */\n+static void prepare_key(unsigned char *k, unsigned char *l, int bl)\n+{\n+\tint i;\n+\t/* Shift block to left, including carry */\n+\tfor (i = 0; i < bl; i++) {\n+\t\tk[i] = l[i] << 1;\n+\t\tif (i < bl - 1 && l[i + 1] & 0x80)\n+\t\t\tk[i] |= 1;\n+\t}\n+\t/* If MSB set fixup with R */\n+\tif (l[0] & 0x80)\n+\t\tk[bl - 1] ^= bl == 16 ? 0x87 : 0x1b;\n+}\n+\n+/**subkeys K1 and K2 generation for CMAC*/\n+static int\n+generate_subkeys(struct ccp_session *sess)\n+{\n+\tconst EVP_CIPHER *algo;\n+\tEVP_CIPHER_CTX *ctx;\n+\tunsigned char *ccp_ctx;\n+\tsize_t i;\n+\tint dstlen, totlen;\n+\tunsigned char zero_iv[AES_BLOCK_SIZE] = {0};\n+\tunsigned char dst[2 * AES_BLOCK_SIZE] = {0};\n+\tunsigned char k1[AES_BLOCK_SIZE] = {0};\n+\tunsigned char k2[AES_BLOCK_SIZE] = {0};\n+\n+\tif (sess->auth.ut.aes_type == CCP_AES_TYPE_128)\n+\t\talgo = EVP_aes_128_cbc();\n+\telse if (sess->auth.ut.aes_type == CCP_AES_TYPE_192)\n+\t\talgo = EVP_aes_192_cbc();\n+\telse if (sess->auth.ut.aes_type == CCP_AES_TYPE_256)\n+\t\talgo = EVP_aes_256_cbc();\n+\telse {\n+\t\tCCP_LOG_ERR(\"Invalid CMAC type length\");\n+\t\treturn -1;\n+\t}\n+\n+\tctx = EVP_CIPHER_CTX_new();\n+\tif (!ctx) {\n+\t\tCCP_LOG_ERR(\"ctx creation failed\");\n+\t\treturn -1;\n+\t}\n+\tif (EVP_EncryptInit(ctx, algo, (unsigned char *)sess->auth.key,\n+\t\t\t (unsigned char *)zero_iv) <= 0)\n+\t\tgoto key_generate_err;\n+\tif (EVP_CIPHER_CTX_set_padding(ctx, 0) <= 0)\n+\t\tgoto key_generate_err;\n+\tif (EVP_EncryptUpdate(ctx, dst, &dstlen, zero_iv,\n+\t\t\t AES_BLOCK_SIZE) <= 0)\n+\t\tgoto key_generate_err;\n+\tif (EVP_EncryptFinal_ex(ctx, dst + dstlen, &totlen) <= 0)\n+\t\tgoto key_generate_err;\n+\n+\tmemset(sess->auth.pre_compute, 0, CCP_SB_BYTES * 2);\n+\n+\tccp_ctx = (unsigned char *)(sess->auth.pre_compute + CCP_SB_BYTES - 1);\n+\tprepare_key(k1, dst, AES_BLOCK_SIZE);\n+\tfor (i = 0; i < AES_BLOCK_SIZE; i++, ccp_ctx--)\n+\t\t*ccp_ctx = k1[i];\n+\n+\tccp_ctx = (unsigned char *)(sess->auth.pre_compute +\n+\t\t\t\t (2 * CCP_SB_BYTES) - 1);\n+\tprepare_key(k2, k1, AES_BLOCK_SIZE);\n+\tfor (i = 0; i < AES_BLOCK_SIZE; i++, ccp_ctx--)\n+\t\t*ccp_ctx = k2[i];\n+\n+\tEVP_CIPHER_CTX_free(ctx);\n+\n+\treturn 0;\n+\n+key_generate_err:\n+\tCCP_LOG_ERR(\"CMAC Init failed\");\n+\t\treturn -1;\n+}\n+#endif\n+\n+/**configure session*/\n+static int\n+ccp_configure_session_cipher(struct ccp_session *sess,\n+\t\t\t const struct rte_crypto_sym_xform *xform)\n+{\n+\tconst struct rte_crypto_cipher_xform *cipher_xform = NULL;\n+\tsize_t i, j, x, ctr_key_len;\n+\n+\tcipher_xform = &xform->cipher;\n+\t/* set cipher direction */\n+\tif (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)\n+\t\tsess->cipher.dir = CCP_CIPHER_DIR_ENCRYPT;\n+\telse\n+\t\tsess->cipher.dir = CCP_CIPHER_DIR_DECRYPT;\n+\n+\t/* set cipher key */\n+\tsess->cipher.key_length = cipher_xform->key.length;\n+\trte_memcpy(sess->cipher.key, cipher_xform->key.data,\n+\t\t cipher_xform->key.length);\n+\n+\t/* set iv parameters */\n+\tsess->iv.offset = cipher_xform->iv.offset;\n+\tsess->iv.length = cipher_xform->iv.length;\n+\n+\tswitch (cipher_xform->algo) {\n+\tcase RTE_CRYPTO_CIPHER_AES_CTR:\n+\t\tsess->cipher.algo = CCP_CIPHER_ALGO_AES_CTR;\n+\t\tsess->cipher.um.aes_mode = CCP_AES_MODE_CTR;\n+\t\tsess->cipher.engine = CCP_ENGINE_AES;\n+\t\tif (sess->cipher.key_length == 16)\n+\t\t\tsess->cipher.ut.aes_type = CCP_AES_TYPE_128;\n+\t\telse if (sess->cipher.key_length == 24)\n+\t\t\tsess->cipher.ut.aes_type = CCP_AES_TYPE_192;\n+\t\telse if (sess->cipher.key_length == 32)\n+\t\t\tsess->cipher.ut.aes_type = CCP_AES_TYPE_256;\n+\t\telse {\n+\t\t\tCCP_LOG_ERR(\"Invalid cipher key length\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tctr_key_len = sess->cipher.key_length;\n+\t\tfor (i = 0; i < ctr_key_len; i++)\n+\t\t\tsess->cipher.key_ccp[ctr_key_len - i - 1] =\n+\t\t\t\tsess->cipher.key[i];\n+\t\tgoto finish;\n+\tcase RTE_CRYPTO_CIPHER_AES_ECB:\n+\t\tsess->cipher.algo = CCP_CIPHER_ALGO_AES_CBC;\n+\t\tsess->cipher.um.aes_mode = CCP_AES_MODE_ECB;\n+\t\tsess->cipher.engine = CCP_ENGINE_AES;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_AES_CBC:\n+\t\tsess->cipher.algo = CCP_CIPHER_ALGO_AES_CBC;\n+\t\tsess->cipher.um.aes_mode = CCP_AES_MODE_CBC;\n+\t\tsess->cipher.engine = CCP_ENGINE_AES;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_3DES_CBC:\n+\t\tsess->cipher.algo = CCP_CIPHER_ALGO_3DES_CBC;\n+\t\tsess->cipher.um.aes_mode = CCP_DES_MODE_CBC;\n+\t\tsess->cipher.engine = CCP_ENGINE_3DES;\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported cipher algo\");\n+\t\treturn -1;\n+\t}\n+\n+\n+\tswitch (sess->cipher.engine) {\n+\tcase CCP_ENGINE_AES:\n+\t\tif (sess->cipher.key_length == 16)\n+\t\t\tsess->cipher.ut.aes_type = CCP_AES_TYPE_128;\n+\t\telse if (sess->cipher.key_length == 24)\n+\t\t\tsess->cipher.ut.aes_type = CCP_AES_TYPE_192;\n+\t\telse if (sess->cipher.key_length == 32)\n+\t\t\tsess->cipher.ut.aes_type = CCP_AES_TYPE_256;\n+\t\telse {\n+\t\t\tCCP_LOG_ERR(\"Invalid cipher key length\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tfor (i = 0; i < sess->cipher.key_length ; i++)\n+\t\t\tsess->cipher.key_ccp[sess->cipher.key_length - i - 1] =\n+\t\t\t\tsess->cipher.key[i];\n+\t\tsess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp);\n+\t\tbreak;\n+\tcase CCP_ENGINE_3DES:\n+\t\tif (sess->cipher.key_length == 16)\n+\t\t\tsess->cipher.ut.des_type = CCP_DES_TYPE_128;\n+\t\telse if (sess->cipher.key_length == 24)\n+\t\t\tsess->cipher.ut.des_type = CCP_DES_TYPE_192;\n+\t\telse {\n+\t\t\tCCP_LOG_ERR(\"Invalid cipher key length\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tfor (j = 0, x = 0; j < sess->cipher.key_length/8; j++, x += 8)\n+\t\t\tfor (i = 0; i < 8; i++)\n+\t\t\t\tsess->cipher.key_ccp[(8 + x) - i - 1] =\n+\t\t\t\t\tsess->cipher.key[i + x];\n+\t\tbreak;\n+\tdefault:\n+\t\t/* should never reach here */\n+\t\tCCP_LOG_ERR(\"Invalid CCP Engine\");\n+\t\treturn -1;\n+\t}\n+finish:\n+\tsess->cipher.nonce_phys = rte_mem_virt2phy(sess->cipher.nonce);\n+\tsess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp);\n+\treturn 0;\n+}\n+\n+static int\n+ccp_configure_session_auth(struct ccp_session *sess,\n+\t\t\t const struct rte_crypto_sym_xform *xform)\n+{\n+\tconst struct rte_crypto_auth_xform *auth_xform = NULL;\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\tsize_t i;\n+#endif\n+\n+\tauth_xform = &xform->auth;\n+\n+\tsess->auth.digest_length = auth_xform->digest_length;\n+\tif (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE)\n+\t\tsess->auth.op = CCP_AUTH_OP_GENERATE;\n+\telse\n+\t\tsess->auth.op = CCP_AUTH_OP_VERIFY;\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\tswitch (auth_xform->algo) {\n+\tcase RTE_CRYPTO_AUTH_SHA1:\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA1;\n+\t\tsess->auth.ut.sha_type = CCP_SHA_TYPE_1;\n+\t\tsess->auth.ctx = (void *)ccp_sha1_init;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES;\n+\t\tsess->auth.offset = CCP_SB_BYTES - SHA1_DIGEST_SIZE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n+\t\tif (auth_xform->key.length > SHA1_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA1_HMAC;\n+\t\tsess->auth.ut.sha_type = CCP_SHA_TYPE_1;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES;\n+\t\tsess->auth.offset = CCP_SB_BYTES - SHA1_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA1_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\tmemset(sess->auth.pre_compute, 0, sess->auth.ctx_len << 1);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tif (generate_partial_hash(sess))\n+\t\t\treturn -1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA224:\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA224;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA_TYPE_224;\n+\t\tsess->auth.ctx = (void *)ccp_sha224_init;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES;\n+\t\tsess->auth.offset = CCP_SB_BYTES - SHA224_DIGEST_SIZE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA224_HMAC:\n+\t\tif (auth_xform->key.length > SHA224_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA224_HMAC;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA_TYPE_224;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES;\n+\t\tsess->auth.offset = CCP_SB_BYTES - SHA224_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA224_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\tmemset(sess->auth.pre_compute, 0, sess->auth.ctx_len << 1);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tif (generate_partial_hash(sess))\n+\t\t\treturn -1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA3_224:\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA3_224;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA3_TYPE_224;\n+\t\tsess->auth.ctx_len = CCP_SHA3_CTX_SIZE;\n+\t\tsess->auth.offset = CCP_SHA3_CTX_SIZE - SHA224_DIGEST_SIZE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA3_224_HMAC:\n+\t\tif (auth_xform->key.length > SHA3_224_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA3_224_HMAC;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA3_TYPE_224;\n+\t\tsess->auth.ctx_len = CCP_SHA3_CTX_SIZE;\n+\t\tsess->auth.offset = CCP_SHA3_CTX_SIZE - SHA224_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA3_224_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\tmemset(sess->auth.pre_compute, 0, 2 * sess->auth.ctx_len);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tif (generate_partial_hash(sess))\n+\t\t\treturn -1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA256:\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA256;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA_TYPE_256;\n+\t\tsess->auth.ctx = (void *)ccp_sha256_init;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES;\n+\t\tsess->auth.offset = CCP_SB_BYTES - SHA256_DIGEST_SIZE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA256_HMAC:\n+\t\tif (auth_xform->key.length > SHA256_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA256_HMAC;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA_TYPE_256;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES;\n+\t\tsess->auth.offset = CCP_SB_BYTES - SHA256_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA256_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\tmemset(sess->auth.pre_compute, 0, sess->auth.ctx_len << 1);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tif (generate_partial_hash(sess))\n+\t\t\treturn -1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA3_256:\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA3_256;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA3_TYPE_256;\n+\t\tsess->auth.ctx_len = CCP_SHA3_CTX_SIZE;\n+\t\tsess->auth.offset = CCP_SHA3_CTX_SIZE - SHA256_DIGEST_SIZE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA3_256_HMAC:\n+\t\tif (auth_xform->key.length > SHA3_256_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA3_256_HMAC;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA3_TYPE_256;\n+\t\tsess->auth.ctx_len = CCP_SHA3_CTX_SIZE;\n+\t\tsess->auth.offset = CCP_SHA3_CTX_SIZE - SHA256_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA3_256_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\tmemset(sess->auth.pre_compute, 0, 2 * sess->auth.ctx_len);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tif (generate_partial_hash(sess))\n+\t\t\treturn -1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA384:\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA384;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA_TYPE_384;\n+\t\tsess->auth.ctx = (void *)ccp_sha384_init;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES << 1;\n+\t\tsess->auth.offset = (CCP_SB_BYTES << 1) - SHA384_DIGEST_SIZE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA384_HMAC:\n+\t\tif (auth_xform->key.length > SHA384_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA384_HMAC;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA_TYPE_384;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES << 1;\n+\t\tsess->auth.offset = (CCP_SB_BYTES << 1) - SHA384_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA384_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\tmemset(sess->auth.pre_compute, 0, sess->auth.ctx_len << 1);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tif (generate_partial_hash(sess))\n+\t\t\treturn -1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA3_384:\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA3_384;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA3_TYPE_384;\n+\t\tsess->auth.ctx_len = CCP_SHA3_CTX_SIZE;\n+\t\tsess->auth.offset = CCP_SHA3_CTX_SIZE - SHA384_DIGEST_SIZE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA3_384_HMAC:\n+\t\tif (auth_xform->key.length > SHA3_384_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA3_384_HMAC;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA3_TYPE_384;\n+\t\tsess->auth.ctx_len = CCP_SHA3_CTX_SIZE;\n+\t\tsess->auth.offset = CCP_SHA3_CTX_SIZE - SHA384_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA3_384_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\tmemset(sess->auth.pre_compute, 0, 2 * sess->auth.ctx_len);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tif (generate_partial_hash(sess))\n+\t\t\treturn -1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA512:\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA512;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA_TYPE_512;\n+\t\tsess->auth.ctx = (void *)ccp_sha512_init;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES << 1;\n+\t\tsess->auth.offset = (CCP_SB_BYTES << 1) - SHA512_DIGEST_SIZE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA512_HMAC:\n+\t\tif (auth_xform->key.length > SHA512_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA512_HMAC;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA_TYPE_512;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES << 1;\n+\t\tsess->auth.offset = (CCP_SB_BYTES << 1) - SHA512_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA512_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\tmemset(sess->auth.pre_compute, 0, sess->auth.ctx_len << 1);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tif (generate_partial_hash(sess))\n+\t\t\treturn -1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA3_512:\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA3_512;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA3_TYPE_512;\n+\t\tsess->auth.ctx_len = CCP_SHA3_CTX_SIZE;\n+\t\tsess->auth.offset = CCP_SHA3_CTX_SIZE - SHA512_DIGEST_SIZE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA3_512_HMAC:\n+\t\tif (auth_xform->key.length > SHA3_512_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA3_512_HMAC;\n+\t\tsess->auth.engine = CCP_ENGINE_SHA;\n+\t\tsess->auth.ut.sha_type = CCP_SHA3_TYPE_512;\n+\t\tsess->auth.ctx_len = CCP_SHA3_CTX_SIZE;\n+\t\tsess->auth.offset = CCP_SHA3_CTX_SIZE - SHA512_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA3_512_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\tmemset(sess->auth.pre_compute, 0, 2 * sess->auth.ctx_len);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tif (generate_partial_hash(sess))\n+\t\t\treturn -1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_AES_CMAC:\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_AES_CMAC;\n+\t\tsess->auth.engine = CCP_ENGINE_AES;\n+\t\tsess->auth.um.aes_mode = CCP_AES_MODE_CMAC;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\t/**<padding and hash result*/\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES << 1;\n+\t\tsess->auth.offset = AES_BLOCK_SIZE;\n+\t\tsess->auth.block_size = AES_BLOCK_SIZE;\n+\t\tif (sess->auth.key_length == 16)\n+\t\t\tsess->auth.ut.aes_type = CCP_AES_TYPE_128;\n+\t\telse if (sess->auth.key_length == 24)\n+\t\t\tsess->auth.ut.aes_type = CCP_AES_TYPE_192;\n+\t\telse if (sess->auth.key_length == 32)\n+\t\t\tsess->auth.ut.aes_type = CCP_AES_TYPE_256;\n+\t\telse {\n+\t\t\tCCP_LOG_ERR(\"Invalid CMAC key length\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t sess->auth.key_length);\n+\t\tfor (i = 0; i < sess->auth.key_length; i++)\n+\t\t\tsess->auth.key_ccp[sess->auth.key_length - i - 1] =\n+\t\t\t\tsess->auth.key[i];\n+\t\tif (generate_subkeys(sess))\n+\t\t\treturn -1;\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported hash algo\");\n+\t\treturn -1;\n+\t}\n+#else\n+\tswitch (auth_xform->algo) {\n+\tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n+\t\tif (auth_xform->key.length > SHA1_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA1_HMAC;\n+\t\tsess->auth.offset = CCP_SB_BYTES - SHA1_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA1_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA224_HMAC:\n+\t\tif (auth_xform->key.length > SHA224_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA224_HMAC;\n+\t\tsess->auth.offset = CCP_SB_BYTES - SHA224_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA224_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA256_HMAC:\n+\t\tif (auth_xform->key.length > SHA256_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA256_HMAC;\n+\t\tsess->auth.offset = CCP_SB_BYTES - SHA256_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA256_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA384_HMAC:\n+\t\tif (auth_xform->key.length > SHA384_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA384_HMAC;\n+\t\tsess->auth.offset = (CCP_SB_BYTES << 1) - SHA384_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA384_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA512_HMAC:\n+\t\tif (auth_xform->key.length > SHA512_BLOCK_SIZE)\n+\t\t\treturn -1;\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_SHA512_HMAC;\n+\t\tsess->auth.offset = (CCP_SB_BYTES << 1) - SHA512_DIGEST_SIZE;\n+\t\tsess->auth.block_size = SHA512_BLOCK_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_MD5_HMAC:\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_MD5_HMAC;\n+\t\tsess->auth.offset = (CCP_SB_BYTES << 1) - MD5_DIGEST_SIZE;\n+\t\tsess->auth.key_length = auth_xform->key.length;\n+\t\tsess->auth.block_size = MD5_BLOCK_SIZE;\n+\t\tmemset(sess->auth.key, 0, sess->auth.block_size);\n+\t\trte_memcpy(sess->auth.key, auth_xform->key.data,\n+\t\t\t auth_xform->key.length);\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported hash algo\");\n+\t\treturn -1;\n+\t}\n+#endif\n+\treturn 0;\n+}\n+\n+static int\n+ccp_configure_session_aead(struct ccp_session *sess,\n+\t\t\t const struct rte_crypto_sym_xform *xform)\n+{\n+\tconst struct rte_crypto_aead_xform *aead_xform = NULL;\n+\tsize_t i, ctr_key_len;\n+\n+\taead_xform = &xform->aead;\n+\n+\t/* set iv parameters */\n+\tsess->iv.offset = aead_xform->iv.offset;\n+\tsess->iv.length = aead_xform->iv.length;\n+\n+\tswitch (aead_xform->algo) {\n+\tcase RTE_CRYPTO_AEAD_AES_GCM:\n+\t\tsess->cipher.algo = CCP_CIPHER_ALGO_AES_GCM;\n+\t\tsess->cipher.um.aes_mode = CCP_AES_MODE_GCTR;\n+\t\tsess->cipher.engine = CCP_ENGINE_AES;\n+\t\tif (sess->cipher.key_length == 16)\n+\t\t\tsess->cipher.ut.aes_type = CCP_AES_TYPE_128;\n+\t\telse if (sess->cipher.key_length == 24)\n+\t\t\tsess->cipher.ut.aes_type = CCP_AES_TYPE_192;\n+\t\telse if (sess->cipher.key_length == 32)\n+\t\t\tsess->cipher.ut.aes_type = CCP_AES_TYPE_256;\n+\t\telse {\n+\t\t\tCCP_LOG_ERR(\"Invalid aead key length\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tctr_key_len = sess->cipher.key_length;\n+\t\tfor (i = 0; i < ctr_key_len; i++)\n+\t\t\tsess->cipher.key_ccp[ctr_key_len - i - 1] =\n+\t\t\t\tsess->cipher.key[i];\n+\t\tsess->auth.algo = CCP_AUTH_ALGO_AES_GCM;\n+\t\tsess->auth.engine = CCP_ENGINE_AES;\n+\t\tsess->auth.um.aes_mode = CCP_AES_MODE_GHASH;\n+\t\tsess->auth.ctx_len = CCP_SB_BYTES;\n+\t\tsess->auth.offset = 0;\n+\t\tsess->auth.block_size = AES_BLOCK_SIZE;\n+\t\tsess->auth.aad_length = aead_xform->aad_length;\n+\t\tsess->cmd_id = CCP_CMD_COMBINED;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -ENOTSUP;\n+\t}\n+\tsess->cipher.nonce_phys = rte_mem_virt2phy(sess->cipher.nonce);\n+\tsess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp);\n+\treturn 0;\n+}\n+\n+int\n+ccp_set_session_parameters(struct ccp_session *sess,\n+\t\t\t const struct rte_crypto_sym_xform *xform)\n+{\n+\tconst struct rte_crypto_sym_xform *cipher_xform = NULL;\n+\tconst struct rte_crypto_sym_xform *auth_xform = NULL;\n+\tconst struct rte_crypto_sym_xform *aead_xform = NULL;\n+\tint ret = 0;\n+\n+\tsess->cmd_id = ccp_get_cmd_id(xform);\n+\n+\tswitch (sess->cmd_id) {\n+\tcase CCP_CMD_CIPHER:\n+\t\tcipher_xform = xform;\n+\t\tbreak;\n+\tcase CCP_CMD_AUTH:\n+\t\tauth_xform = xform;\n+\t\tbreak;\n+\tcase CCP_CMD_CIPHER_HASH:\n+\t\tcipher_xform = xform;\n+\t\tauth_xform = xform->next;\n+\t\tbreak;\n+\tcase CCP_CMD_HASH_CIPHER:\n+\t\tauth_xform = xform;\n+\t\tcipher_xform = xform->next;\n+\t\tbreak;\n+\tcase CCP_CMD_COMBINED:\n+\t\taead_xform = xform;\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported cmd_id\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* Default IV length = 0 */\n+\tsess->iv.length = 0;\n+\tif (cipher_xform) {\n+\t\tret = ccp_configure_session_cipher(sess, cipher_xform);\n+\t\tif (ret != 0) {\n+\t\t\tCCP_LOG_ERR(\"Invalid/unsupported cipher parameters\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\tif (auth_xform) {\n+\t\tret = ccp_configure_session_auth(sess, auth_xform);\n+\t\tif (ret != 0) {\n+\t\t\tCCP_LOG_ERR(\"Invalid/unsupported auth parameters\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\tif (aead_xform) {\n+\t\tret = ccp_configure_session_aead(sess, aead_xform);\n+\t\tif (ret != 0) {\n+\t\t\tCCP_LOG_ERR(\"Invalid/unsupported aead parameters\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\treturn ret;\n+}\n+\n+/* calculate CCP descriptors requirement */\n+static inline int\n+ccp_cipher_slot(struct ccp_session *session)\n+{\n+\tint count = 0;\n+\n+\tswitch (session->cipher.algo) {\n+\tcase CCP_CIPHER_ALGO_AES_CBC:\n+\t\tcount = 2;\n+\t\t/**< op + passthrough for iv*/\n+\t\tbreak;\n+\tcase CCP_CIPHER_ALGO_AES_ECB:\n+\t\tcount = 1;\n+\t\t/**<only op*/\n+\t\tbreak;\n+\tcase CCP_CIPHER_ALGO_AES_CTR:\n+\t\tcount = 2;\n+\t\t/**< op + passthrough for iv*/\n+\t\tbreak;\n+\tcase CCP_CIPHER_ALGO_3DES_CBC:\n+\t\tcount = 2;\n+\t\t/**< op + passthrough for iv*/\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported ALGO %d\", session->cipher.algo);\n+\t}\n+\treturn count;\n+}\n+\n+static inline int\n+ccp_auth_slot(struct ccp_session *session)\n+{\n+\tint count = 0;\n+\n+\tswitch (session->auth.algo) {\n+\tcase CCP_AUTH_ALGO_SHA1:\n+\tcase CCP_AUTH_ALGO_SHA224:\n+\tcase CCP_AUTH_ALGO_SHA256:\n+\tcase CCP_AUTH_ALGO_SHA384:\n+\tcase CCP_AUTH_ALGO_SHA512:\n+\t\tcount = 3;\n+\t\t/**< op + lsb passthrough cpy to/from*/\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA1_HMAC:\n+\tcase CCP_AUTH_ALGO_SHA224_HMAC:\n+\tcase CCP_AUTH_ALGO_SHA256_HMAC:\n+\t\tcount = 6;\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA384_HMAC:\n+\tcase CCP_AUTH_ALGO_SHA512_HMAC:\n+\t\tcount = 7;\n+\t\t/**\n+\t\t * 1. Load PHash1 = H(k ^ ipad); to LSB\n+\t\t * 2. generate IHash = H(hash on meassage with PHash1\n+\t\t * as init values);\n+\t\t * 3. Retrieve IHash 2 slots for 384/512\n+\t\t * 4. Load Phash2 = H(k ^ opad); to LSB\n+\t\t * 5. generate FHash = H(hash on Ihash with Phash2\n+\t\t * as init value);\n+\t\t * 6. Retrieve HMAC output from LSB to host memory\n+\t\t */\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA3_224:\n+\tcase CCP_AUTH_ALGO_SHA3_256:\n+\tcase CCP_AUTH_ALGO_SHA3_384:\n+\tcase CCP_AUTH_ALGO_SHA3_512:\n+\t\tcount = 1;\n+\t\t/**< only op ctx and dst in host memory*/\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA3_224_HMAC:\n+\tcase CCP_AUTH_ALGO_SHA3_256_HMAC:\n+\t\tcount = 3;\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA3_384_HMAC:\n+\tcase CCP_AUTH_ALGO_SHA3_512_HMAC:\n+\t\tcount = 4;\n+\t\t/**\n+\t\t * 1. Op to Perform Ihash\n+\t\t * 2. Retrieve result from LSB to host memory\n+\t\t * 3. Perform final hash\n+\t\t */\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_AES_CMAC:\n+\t\tcount = 4;\n+\t\t/**\n+\t\t * op\n+\t\t * extra descriptor in padding case\n+\t\t * (k1/k2(255:128) with iv(127:0))\n+\t\t * Retrieve result\n+\t\t */\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported ALGO %d\", session->cipher.algo);\n+\t}\n+\n+\treturn count;\n+}\n+\n+static int\n+ccp_combined_mode_slot(struct ccp_session *session)\n+{\n+\tint count = 0;\n+\n+\tswitch (session->cipher.algo) {\n+\tcase CCP_CIPHER_ALGO_AES_GCM:\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported combined cipher ALGO %d\",\n+\t\t\t session->cipher.algo);\n+\t}\n+\tswitch (session->auth.algo) {\n+\tcase CCP_AUTH_ALGO_AES_GCM:\n+\t\tcount = 5;\n+\t\t/**\n+\t\t * 1. Passthru iv\n+\t\t * 2. Hash AAD\n+\t\t * 3. GCTR\n+\t\t * 4. Reload passthru\n+\t\t * 5. Hash Final tag\n+\t\t */\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported combined auth ALGO %d\",\n+\t\t\t session->auth.algo);\n+\t}\n+\treturn count;\n+}\n+\n+int\n+ccp_compute_slot_count(struct ccp_session *session)\n+{\n+\tint count = 0;\n+\n+\tswitch (session->cmd_id) {\n+\tcase CCP_CMD_CIPHER:\n+\t\tcount = ccp_cipher_slot(session);\n+\t\tbreak;\n+\tcase CCP_CMD_AUTH:\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\t\tcount = ccp_auth_slot(session);\n+#endif\n+\t\tbreak;\n+\tcase CCP_CMD_CIPHER_HASH:\n+\tcase CCP_CMD_HASH_CIPHER:\n+\t\tcount = ccp_cipher_slot(session);\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\t\tcount += ccp_auth_slot(session);\n+#endif\n+\t\tbreak;\n+\tcase CCP_CMD_COMBINED:\n+\t\tcount = ccp_combined_mode_slot(session);\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported cmd_id\");\n+\n+\t}\n+\n+\treturn count;\n+}\n+\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+static uint8_t\n+algo_select(int sessalgo,\n+\t const EVP_MD **algo)\n+{\n+\tint res = 0;\n+\n+\tswitch (sessalgo) {\n+\tcase CCP_AUTH_ALGO_MD5_HMAC:\n+\t\t*algo = EVP_md5();\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA1_HMAC:\n+\t\t*algo = EVP_sha1();\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA224_HMAC:\n+\t\t*algo = EVP_sha224();\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA256_HMAC:\n+\t\t*algo = EVP_sha256();\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA384_HMAC:\n+\t\t*algo = EVP_sha384();\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA512_HMAC:\n+\t\t*algo = EVP_sha512();\n+\t\tbreak;\n+\tdefault:\n+\t\tres = -EINVAL;\n+\t\tbreak;\n+\t}\n+\treturn res;\n+}\n+\n+\n+static int\n+process_cpu_auth_hmac(uint8_t *src, uint8_t *dst,\n+\t\t __rte_unused uint8_t *iv,\n+\t\t EVP_PKEY *pkey,\n+\t\t int srclen,\n+\t\t EVP_MD_CTX *ctx,\n+\t\t const EVP_MD *algo,\n+\t\t uint16_t d_len)\n+{\n+\tsize_t dstlen;\n+\tunsigned char temp_dst[64];\n+\n+\tif (EVP_DigestSignInit(ctx, NULL, algo, NULL, pkey) <= 0)\n+\t\tgoto process_auth_err;\n+\n+\tif (EVP_DigestSignUpdate(ctx, (char *)src, srclen) <= 0)\n+\t\tgoto process_auth_err;\n+\n+\tif (EVP_DigestSignFinal(ctx, temp_dst, &dstlen) <= 0)\n+\t\tgoto process_auth_err;\n+\n+\trte_memcpy(dst, temp_dst, d_len);\n+\treturn 0;\n+process_auth_err:\n+\tCCP_LOG_ERR(\"Process cpu auth failed\");\n+\treturn -EINVAL;\n+}\n+\n+\n+static int cpu_auth_verify(struct rte_crypto_op *op)\n+{\n+\tint offset;\n+\tuint8_t *addr;\n+\tstruct ccp_session *session;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\taddr = (uint8_t *)((char *)op->sym->m_src->buf_addr +\n+\t\t\t op->sym->m_src->data_off +\n+\t\t\t op->sym->m_src->data_len -\n+\t\t\t session->auth.digest_length);\n+\toffset = session->auth.offset;\n+\n+\treturn memcmp(addr + offset,\n+\t\t op->sym->auth.digest.data,\n+\t\t session->auth.digest_length);\n+}\n+\n+static int cpu_crypto_auth(struct rte_crypto_op *op, struct ccp_session *sess,\n+\t\t\t EVP_MD_CTX *ctx)\n+{\n+\tuint8_t *src, *dst;\n+\tint srclen, status;\n+\tstruct rte_mbuf *mbuf_src, *mbuf_dst;\n+\tconst EVP_MD *algo = NULL;\n+\tEVP_PKEY *pkey;\n+\n+\talgo_select(sess->auth.algo, &algo);\n+\tpkey = EVP_PKEY_new_mac_key(EVP_PKEY_HMAC, NULL, sess->auth.key,\n+\t\t\t\t sess->auth.key_length);\n+\tmbuf_src = op->sym->m_src;\n+\tmbuf_dst = op->sym->m_dst ? op->sym->m_dst : op->sym->m_src;\n+\tsrclen = op->sym->auth.data.length;\n+\tsrc = rte_pktmbuf_mtod_offset(mbuf_src, uint8_t *,\n+\t\t\t\t op->sym->auth.data.offset);\n+\n+\tif (sess->auth.op == CCP_AUTH_OP_VERIFY) {\n+\t\tdst = (uint8_t *)rte_pktmbuf_append(mbuf_src,\n+\t\t\t\t\t\t sess->auth.digest_length);\n+\t} else {\n+\t\tdst = op->sym->auth.digest.data;\n+\t\tif (dst == NULL) {\n+\t\t\tdst = rte_pktmbuf_mtod_offset(mbuf_dst, uint8_t *,\n+\t\t\t\t\t\t op->sym->auth.data.offset +\n+\t\t\t\t\t\t sess->auth.digest_length);\n+\t\t}\n+\t}\n+\tstatus = process_cpu_auth_hmac(src, dst, NULL,\n+\t\t\t\t pkey, srclen,\n+\t\t\t\t ctx,\n+\t\t\t\t algo,\n+\t\t\t\t sess->auth.digest_length);\n+\tif (status) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\treturn status;\n+\t}\n+\n+\tif (sess->auth.op == CCP_AUTH_OP_VERIFY) {\n+\t\tif (memcmp(dst, op->sym->auth.digest.data,\n+\t\t\t sess->auth.digest_length) != 0) {\n+\t\t\top->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\t\t} else {\n+\t\t\top->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t}\n+\t} else {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t}\n+\n+\tif (sess->auth.op == CCP_AUTH_OP_VERIFY) {\n+\t\trte_pktmbuf_trim(mbuf_src,\n+\t\t\t\t sess->auth.digest_length);\n+\t}\n+\n+\treturn 0;\n+}\n+#endif\n+\n+static void\n+ccp_perform_passthru(struct ccp_passthru *pst,\n+\t\t struct ccp_queue *cmd_q)\n+{\n+\tstruct ccp_desc *desc;\n+\tunion ccp_function function;\n+\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_PASSTHRU;\n+\n+\tCCP_CMD_SOC(desc) = 0;\n+\tCCP_CMD_IOC(desc) = 0;\n+\tCCP_CMD_INIT(desc) = 0;\n+\tCCP_CMD_EOM(desc) = 0;\n+\tCCP_CMD_PROT(desc) = 0;\n+\n+\tfunction.raw = 0;\n+\tCCP_PT_BYTESWAP(&function) = pst->byte_swap;\n+\tCCP_PT_BITWISE(&function) = pst->bit_mod;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\tCCP_CMD_LEN(desc) = pst->len;\n+\n+\tif (pst->dir) {\n+\t\tCCP_CMD_SRC_LO(desc) = (uint32_t)(pst->src_addr);\n+\t\tCCP_CMD_SRC_HI(desc) = high32_value(pst->src_addr);\n+\t\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\t\tCCP_CMD_DST_LO(desc) = (uint32_t)(pst->dest_addr);\n+\t\tCCP_CMD_DST_HI(desc) = 0;\n+\t\tCCP_CMD_DST_MEM(desc) = CCP_MEMTYPE_SB;\n+\n+\t\tif (pst->bit_mod != CCP_PASSTHRU_BITWISE_NOOP)\n+\t\t\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_key;\n+\t} else {\n+\n+\t\tCCP_CMD_SRC_LO(desc) = (uint32_t)(pst->src_addr);\n+\t\tCCP_CMD_SRC_HI(desc) = 0;\n+\t\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SB;\n+\n+\t\tCCP_CMD_DST_LO(desc) = (uint32_t)(pst->dest_addr);\n+\t\tCCP_CMD_DST_HI(desc) = high32_value(pst->dest_addr);\n+\t\tCCP_CMD_DST_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\t}\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+}\n+\n+static int\n+ccp_perform_hmac(struct rte_crypto_op *op,\n+\t\t struct ccp_queue *cmd_q)\n+{\n+\n+\tstruct ccp_session *session;\n+\tunion ccp_function function;\n+\tstruct ccp_desc *desc;\n+\tuint32_t tail;\n+\tphys_addr_t src_addr, dest_addr, dest_addr_t;\n+\tstruct ccp_passthru pst;\n+\tuint64_t auth_msg_bits;\n+\tvoid *append_ptr;\n+\tuint8_t *addr;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\taddr = session->auth.pre_compute;\n+\n+\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\t\t\t\t\t op->sym->auth.data.offset);\n+\tappend_ptr = (void *)rte_pktmbuf_append(op->sym->m_src,\n+\t\t\t\t\t\tsession->auth.ctx_len);\n+\tdest_addr = (phys_addr_t)rte_mem_virt2phy(append_ptr);\n+\tdest_addr_t = dest_addr;\n+\n+\t/** Load PHash1 to LSB*/\n+\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)addr);\n+\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n+\tpst.len = session->auth.ctx_len;\n+\tpst.dir = 1;\n+\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;\n+\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t/**sha engine command descriptor for IntermediateHash*/\n+\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_SHA;\n+\n+\tCCP_CMD_SOC(desc) = 0;\n+\tCCP_CMD_IOC(desc) = 0;\n+\tCCP_CMD_INIT(desc) = 1;\n+\tCCP_CMD_EOM(desc) = 1;\n+\tCCP_CMD_PROT(desc) = 0;\n+\n+\tfunction.raw = 0;\n+\tCCP_SHA_TYPE(&function) = session->auth.ut.sha_type;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\tCCP_CMD_LEN(desc) = op->sym->auth.data.length;\n+\tauth_msg_bits = (op->sym->auth.data.length +\n+\t\t\t session->auth.block_size) * 8;\n+\n+\tCCP_CMD_SRC_LO(desc) = ((uint32_t)src_addr);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(src_addr);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_sha;\n+\tCCP_CMD_SHA_LO(desc) = ((uint32_t)auth_msg_bits);\n+\tCCP_CMD_SHA_HI(desc) = high32_value(auth_msg_bits);\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\n+\trte_wmb();\n+\n+\ttail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\t/* Intermediate Hash value retrieve */\n+\tif ((session->auth.ut.sha_type == CCP_SHA_TYPE_384) ||\n+\t (session->auth.ut.sha_type == CCP_SHA_TYPE_512)) {\n+\n+\t\tpst.src_addr =\n+\t\t\t(phys_addr_t)((cmd_q->sb_sha + 1) * CCP_SB_BYTES);\n+\t\tpst.dest_addr = dest_addr_t;\n+\t\tpst.len = CCP_SB_BYTES;\n+\t\tpst.dir = 0;\n+\t\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\t\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t\tpst.src_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n+\t\tpst.dest_addr = dest_addr_t + CCP_SB_BYTES;\n+\t\tpst.len = CCP_SB_BYTES;\n+\t\tpst.dir = 0;\n+\t\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\t\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t} else {\n+\t\tpst.src_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n+\t\tpst.dest_addr = dest_addr_t;\n+\t\tpst.len = session->auth.ctx_len;\n+\t\tpst.dir = 0;\n+\t\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\t\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t}\n+\n+\t/** Load PHash2 to LSB*/\n+\taddr += session->auth.ctx_len;\n+\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)addr);\n+\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n+\tpst.len = session->auth.ctx_len;\n+\tpst.dir = 1;\n+\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;\n+\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t/**sha engine command descriptor for FinalHash*/\n+\tdest_addr_t += session->auth.offset;\n+\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_SHA;\n+\n+\tCCP_CMD_SOC(desc) = 0;\n+\tCCP_CMD_IOC(desc) = 0;\n+\tCCP_CMD_INIT(desc) = 1;\n+\tCCP_CMD_EOM(desc) = 1;\n+\tCCP_CMD_PROT(desc) = 0;\n+\n+\tfunction.raw = 0;\n+\tCCP_SHA_TYPE(&function) = session->auth.ut.sha_type;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\tCCP_CMD_LEN(desc) = (session->auth.ctx_len -\n+\t\t\t session->auth.offset);\n+\tauth_msg_bits = (session->auth.block_size +\n+\t\t\t session->auth.ctx_len -\n+\t\t\t session->auth.offset) * 8;\n+\n+\tCCP_CMD_SRC_LO(desc) = (uint32_t)(dest_addr_t);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(dest_addr_t);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_sha;\n+\tCCP_CMD_SHA_LO(desc) = ((uint32_t)auth_msg_bits);\n+\tCCP_CMD_SHA_HI(desc) = high32_value(auth_msg_bits);\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\n+\trte_wmb();\n+\n+\ttail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\t/* Retrieve hmac output */\n+\tpst.src_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n+\tpst.dest_addr = dest_addr;\n+\tpst.len = session->auth.ctx_len;\n+\tpst.dir = 0;\n+\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\tif ((session->auth.ut.sha_type == CCP_SHA_TYPE_384) ||\n+\t (session->auth.ut.sha_type == CCP_SHA_TYPE_512))\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;\n+\telse\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\tccp_perform_passthru(&pst, cmd_q);\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\treturn 0;\n+\n+}\n+\n+static int\n+ccp_perform_sha(struct rte_crypto_op *op,\n+\t\tstruct ccp_queue *cmd_q)\n+{\n+\tstruct ccp_session *session;\n+\tunion ccp_function function;\n+\tstruct ccp_desc *desc;\n+\tuint32_t tail;\n+\tphys_addr_t src_addr, dest_addr;\n+\tstruct ccp_passthru pst;\n+\tvoid *append_ptr;\n+\tuint64_t auth_msg_bits;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\n+\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\t\t\t\t\t op->sym->auth.data.offset);\n+\n+\tappend_ptr = (void *)rte_pktmbuf_append(op->sym->m_src,\n+\t\t\t\t\t\tsession->auth.ctx_len);\n+\tdest_addr = (phys_addr_t)rte_mem_virt2phy(append_ptr);\n+\n+\t/** Passthru sha context*/\n+\n+\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)\n+\t\t\t\t\t\t session->auth.ctx);\n+\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n+\tpst.len = session->auth.ctx_len;\n+\tpst.dir = 1;\n+\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;\n+\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t/**prepare sha command descriptor*/\n+\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_SHA;\n+\n+\tCCP_CMD_SOC(desc) = 0;\n+\tCCP_CMD_IOC(desc) = 0;\n+\tCCP_CMD_INIT(desc) = 1;\n+\tCCP_CMD_EOM(desc) = 1;\n+\tCCP_CMD_PROT(desc) = 0;\n+\n+\tfunction.raw = 0;\n+\tCCP_SHA_TYPE(&function) = session->auth.ut.sha_type;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\tCCP_CMD_LEN(desc) = op->sym->auth.data.length;\n+\tauth_msg_bits = op->sym->auth.data.length * 8;\n+\n+\tCCP_CMD_SRC_LO(desc) = ((uint32_t)src_addr);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(src_addr);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_sha;\n+\tCCP_CMD_SHA_LO(desc) = ((uint32_t)auth_msg_bits);\n+\tCCP_CMD_SHA_HI(desc) = high32_value(auth_msg_bits);\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\n+\trte_wmb();\n+\n+\ttail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\t/* Hash value retrieve */\n+\tpst.src_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n+\tpst.dest_addr = dest_addr;\n+\tpst.len = session->auth.ctx_len;\n+\tpst.dir = 0;\n+\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\tif ((session->auth.ut.sha_type == CCP_SHA_TYPE_384) ||\n+\t (session->auth.ut.sha_type == CCP_SHA_TYPE_512))\n+\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;\n+\telse\n+\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\tccp_perform_passthru(&pst, cmd_q);\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\treturn 0;\n+\n+}\n+\n+static int\n+ccp_perform_sha3_hmac(struct rte_crypto_op *op,\n+\t\t struct ccp_queue *cmd_q)\n+{\n+\tstruct ccp_session *session;\n+\tstruct ccp_passthru pst;\n+\tunion ccp_function function;\n+\tstruct ccp_desc *desc;\n+\tuint8_t *append_ptr;\n+\tuint32_t tail;\n+\tphys_addr_t src_addr, dest_addr, ctx_paddr, dest_addr_t;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\n+\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\t\t\t\t\t op->sym->auth.data.offset);\n+\tappend_ptr = (uint8_t *)rte_pktmbuf_append(op->sym->m_src,\n+\t\t\t\t\t\tsession->auth.ctx_len);\n+\tif (!append_ptr) {\n+\t\tCCP_LOG_ERR(\"CCP MBUF append failed\\n\");\n+\t\treturn -1;\n+\t}\n+\tdest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr);\n+\tdest_addr_t = dest_addr + (session->auth.ctx_len / 2);\n+\tctx_paddr = (phys_addr_t)rte_mem_virt2phy((void\n+\t\t\t\t\t\t *)session->auth.pre_compute);\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\t/*desc1 for SHA3-Ihash operation */\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_SHA;\n+\tCCP_CMD_INIT(desc) = 1;\n+\tCCP_CMD_EOM(desc) = 1;\n+\n+\tfunction.raw = 0;\n+\tCCP_SHA_TYPE(&function) = session->auth.ut.sha_type;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\tCCP_CMD_LEN(desc) = op->sym->auth.data.length;\n+\n+\tCCP_CMD_SRC_LO(desc) = ((uint32_t)src_addr);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(src_addr);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_DST_LO(desc) = (cmd_q->sb_sha * CCP_SB_BYTES);\n+\tCCP_CMD_DST_HI(desc) = 0;\n+\tCCP_CMD_DST_MEM(desc) = CCP_MEMTYPE_SB;\n+\n+\tCCP_CMD_KEY_LO(desc) = ((uint32_t)ctx_paddr);\n+\tCCP_CMD_KEY_HI(desc) = high32_value(ctx_paddr);\n+\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\n+\trte_wmb();\n+\ttail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\t/* Intermediate Hash value retrieve */\n+\tif ((session->auth.ut.sha_type == CCP_SHA3_TYPE_384) ||\n+\t (session->auth.ut.sha_type == CCP_SHA3_TYPE_512)) {\n+\n+\t\tpst.src_addr =\n+\t\t\t(phys_addr_t)((cmd_q->sb_sha + 1) * CCP_SB_BYTES);\n+\t\tpst.dest_addr = dest_addr_t;\n+\t\tpst.len = CCP_SB_BYTES;\n+\t\tpst.dir = 0;\n+\t\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\t\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t\tpst.src_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n+\t\tpst.dest_addr = dest_addr_t + CCP_SB_BYTES;\n+\t\tpst.len = CCP_SB_BYTES;\n+\t\tpst.dir = 0;\n+\t\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\t\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t} else {\n+\t\tpst.src_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n+\t\tpst.dest_addr = dest_addr_t;\n+\t\tpst.len = CCP_SB_BYTES;\n+\t\tpst.dir = 0;\n+\t\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\t\tccp_perform_passthru(&pst, cmd_q);\n+\t}\n+\n+\t/**sha engine command descriptor for FinalHash*/\n+\tctx_paddr += CCP_SHA3_CTX_SIZE;\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_SHA;\n+\tCCP_CMD_INIT(desc) = 1;\n+\tCCP_CMD_EOM(desc) = 1;\n+\n+\tfunction.raw = 0;\n+\tCCP_SHA_TYPE(&function) = session->auth.ut.sha_type;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\tif (session->auth.ut.sha_type == CCP_SHA3_TYPE_224) {\n+\t\tdest_addr_t += (CCP_SB_BYTES - SHA224_DIGEST_SIZE);\n+\t\tCCP_CMD_LEN(desc) = SHA224_DIGEST_SIZE;\n+\t} else if (session->auth.ut.sha_type == CCP_SHA3_TYPE_256) {\n+\t\tCCP_CMD_LEN(desc) = SHA256_DIGEST_SIZE;\n+\t} else if (session->auth.ut.sha_type == CCP_SHA3_TYPE_384) {\n+\t\tdest_addr_t += (2 * CCP_SB_BYTES - SHA384_DIGEST_SIZE);\n+\t\tCCP_CMD_LEN(desc) = SHA384_DIGEST_SIZE;\n+\t} else {\n+\t\tCCP_CMD_LEN(desc) = SHA512_DIGEST_SIZE;\n+\t}\n+\n+\tCCP_CMD_SRC_LO(desc) = ((uint32_t)dest_addr_t);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(dest_addr_t);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_DST_LO(desc) = (uint32_t)dest_addr;\n+\tCCP_CMD_DST_HI(desc) = high32_value(dest_addr);\n+\tCCP_CMD_DST_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_KEY_LO(desc) = ((uint32_t)ctx_paddr);\n+\tCCP_CMD_KEY_HI(desc) = high32_value(ctx_paddr);\n+\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\n+\trte_wmb();\n+\ttail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\treturn 0;\n+}\n+\n+static int\n+ccp_perform_sha3(struct rte_crypto_op *op,\n+\t\t struct ccp_queue *cmd_q)\n+{\n+\tstruct ccp_session *session;\n+\tunion ccp_function function;\n+\tstruct ccp_desc *desc;\n+\tuint8_t *ctx_addr, *append_ptr;\n+\tuint32_t tail;\n+\tphys_addr_t src_addr, dest_addr, ctx_paddr;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\n+\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\t\t\t\t\t op->sym->auth.data.offset);\n+\tappend_ptr = (uint8_t *)rte_pktmbuf_append(op->sym->m_src,\n+\t\t\t\t\t\tsession->auth.ctx_len);\n+\tif (!append_ptr) {\n+\t\tCCP_LOG_ERR(\"CCP MBUF append failed\\n\");\n+\t\treturn -1;\n+\t}\n+\tdest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr);\n+\tctx_addr = session->auth.sha3_ctx;\n+\tctx_paddr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr);\n+\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\t/* prepare desc for SHA3 operation */\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_SHA;\n+\tCCP_CMD_INIT(desc) = 1;\n+\tCCP_CMD_EOM(desc) = 1;\n+\n+\tfunction.raw = 0;\n+\tCCP_SHA_TYPE(&function) = session->auth.ut.sha_type;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\tCCP_CMD_LEN(desc) = op->sym->auth.data.length;\n+\n+\tCCP_CMD_SRC_LO(desc) = ((uint32_t)src_addr);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(src_addr);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_DST_LO(desc) = ((uint32_t)dest_addr);\n+\tCCP_CMD_DST_HI(desc) = high32_value(dest_addr);\n+\tCCP_CMD_DST_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_KEY_LO(desc) = ((uint32_t)ctx_paddr);\n+\tCCP_CMD_KEY_HI(desc) = high32_value(ctx_paddr);\n+\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\n+\trte_wmb();\n+\n+\ttail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\treturn 0;\n+}\n+\n+static int\n+ccp_perform_aes_cmac(struct rte_crypto_op *op,\n+\t\t struct ccp_queue *cmd_q)\n+{\n+\tstruct ccp_session *session;\n+\tunion ccp_function function;\n+\tstruct ccp_passthru pst;\n+\tstruct ccp_desc *desc;\n+\tuint32_t tail;\n+\tuint8_t *src_tb, *append_ptr, *ctx_addr;\n+\tphys_addr_t src_addr, dest_addr, key_addr;\n+\tint length, non_align_len;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\tkey_addr = rte_mem_virt2phy(session->auth.key_ccp);\n+\n+\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\t\t\t\t\t op->sym->auth.data.offset);\n+\tappend_ptr = (uint8_t *)rte_pktmbuf_append(op->sym->m_src,\n+\t\t\t\t\t\tsession->auth.ctx_len);\n+\tdest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr);\n+\n+\tfunction.raw = 0;\n+\tCCP_AES_ENCRYPT(&function) = CCP_CIPHER_DIR_ENCRYPT;\n+\tCCP_AES_MODE(&function) = session->auth.um.aes_mode;\n+\tCCP_AES_TYPE(&function) = session->auth.ut.aes_type;\n+\n+\tif (op->sym->auth.data.length % session->auth.block_size == 0) {\n+\n+\t\tctx_addr = session->auth.pre_compute;\n+\t\tmemset(ctx_addr, 0, AES_BLOCK_SIZE);\n+\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr);\n+\t\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES);\n+\t\tpst.len = CCP_SB_BYTES;\n+\t\tpst.dir = 1;\n+\t\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;\n+\t\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\t\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\t\t/* prepare desc for aes-cmac command */\n+\t\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_AES;\n+\t\tCCP_CMD_EOM(desc) = 1;\n+\t\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\t\tCCP_CMD_LEN(desc) = op->sym->auth.data.length;\n+\t\tCCP_CMD_SRC_LO(desc) = ((uint32_t)src_addr);\n+\t\tCCP_CMD_SRC_HI(desc) = high32_value(src_addr);\n+\t\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\t\tCCP_CMD_KEY_LO(desc) = ((uint32_t)key_addr);\n+\t\tCCP_CMD_KEY_HI(desc) = high32_value(key_addr);\n+\t\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\t\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_iv;\n+\n+\t\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\n+\t\trte_wmb();\n+\n+\t\ttail =\n+\t\t(uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\t\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\t\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\t} else {\n+\t\tctx_addr = session->auth.pre_compute + CCP_SB_BYTES;\n+\t\tmemset(ctx_addr, 0, AES_BLOCK_SIZE);\n+\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr);\n+\t\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES);\n+\t\tpst.len = CCP_SB_BYTES;\n+\t\tpst.dir = 1;\n+\t\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;\n+\t\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t\tlength = (op->sym->auth.data.length / AES_BLOCK_SIZE);\n+\t\tlength *= AES_BLOCK_SIZE;\n+\t\tnon_align_len = op->sym->auth.data.length - length;\n+\t\t/* prepare desc for aes-cmac command */\n+\t\t/*Command 1*/\n+\t\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\t\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\t\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_AES;\n+\t\tCCP_CMD_INIT(desc) = 1;\n+\t\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\t\tCCP_CMD_LEN(desc) = length;\n+\t\tCCP_CMD_SRC_LO(desc) = ((uint32_t)src_addr);\n+\t\tCCP_CMD_SRC_HI(desc) = high32_value(src_addr);\n+\t\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\t\tCCP_CMD_KEY_LO(desc) = ((uint32_t)key_addr);\n+\t\tCCP_CMD_KEY_HI(desc) = high32_value(key_addr);\n+\t\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\t\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_iv;\n+\n+\t\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\n+\t\t/*Command 2*/\n+\t\tappend_ptr = append_ptr + CCP_SB_BYTES;\n+\t\tmemset(append_ptr, 0, AES_BLOCK_SIZE);\n+\t\tsrc_tb = rte_pktmbuf_mtod_offset(op->sym->m_src,\n+\t\t\t\t\t\t uint8_t *,\n+\t\t\t\t\t\t op->sym->auth.data.offset +\n+\t\t\t\t\t\t length);\n+\t\trte_memcpy(append_ptr, src_tb, non_align_len);\n+\t\tappend_ptr[non_align_len] = CMAC_PAD_VALUE;\n+\n+\t\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\t\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\t\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_AES;\n+\t\tCCP_CMD_EOM(desc) = 1;\n+\t\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\t\tCCP_CMD_LEN(desc) = AES_BLOCK_SIZE;\n+\n+\t\tCCP_CMD_SRC_LO(desc) = ((uint32_t)(dest_addr + CCP_SB_BYTES));\n+\t\tCCP_CMD_SRC_HI(desc) = high32_value(dest_addr + CCP_SB_BYTES);\n+\t\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\t\tCCP_CMD_KEY_LO(desc) = ((uint32_t)key_addr);\n+\t\tCCP_CMD_KEY_HI(desc) = high32_value(key_addr);\n+\t\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\t\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_iv;\n+\n+\t\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\n+\t\trte_wmb();\n+\t\ttail =\n+\t\t(uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\t\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\t\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\t}\n+\t/* Retrieve result */\n+\tpst.dest_addr = dest_addr;\n+\tpst.src_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES);\n+\tpst.len = CCP_SB_BYTES;\n+\tpst.dir = 0;\n+\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\tccp_perform_passthru(&pst, cmd_q);\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\treturn 0;\n+}\n+\n+static int\n+ccp_perform_aes(struct rte_crypto_op *op,\n+\t\tstruct ccp_queue *cmd_q,\n+\t\tstruct ccp_batch_info *b_info)\n+{\n+\tstruct ccp_session *session;\n+\tunion ccp_function function;\n+\tuint8_t *lsb_buf;\n+\tstruct ccp_passthru pst = {0};\n+\tstruct ccp_desc *desc;\n+\tphys_addr_t src_addr, dest_addr, key_addr;\n+\tuint8_t *iv;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\tfunction.raw = 0;\n+\n+\tiv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset);\n+\tif (session->cipher.um.aes_mode != CCP_AES_MODE_ECB) {\n+\t\tif (session->cipher.um.aes_mode == CCP_AES_MODE_CTR) {\n+\t\t\trte_memcpy(session->cipher.nonce + AES_BLOCK_SIZE +\n+\t\t\t\t CTR_NONCE_SIZE, iv, CTR_IV_SIZE);\n+\t\t\tpst.src_addr = (phys_addr_t)session->cipher.nonce_phys;\n+\t\t\tCCP_AES_SIZE(&function) = 0x1F;\n+\t\t} else {\n+\t\t\tlsb_buf =\n+\t\t\t&(b_info->lsb_buf[b_info->lsb_buf_idx*CCP_SB_BYTES]);\n+\t\t\trte_memcpy(lsb_buf +\n+\t\t\t\t (CCP_SB_BYTES - session->iv.length),\n+\t\t\t\t iv, session->iv.length);\n+\t\t\tpst.src_addr = b_info->lsb_buf_phys +\n+\t\t\t\t(b_info->lsb_buf_idx * CCP_SB_BYTES);\n+\t\t\tb_info->lsb_buf_idx++;\n+\t\t}\n+\n+\t\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES);\n+\t\tpst.len = CCP_SB_BYTES;\n+\t\tpst.dir = 1;\n+\t\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\t\tccp_perform_passthru(&pst, cmd_q);\n+\t}\n+\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\n+\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\t\t\t\t\t op->sym->cipher.data.offset);\n+\tif (likely(op->sym->m_dst != NULL))\n+\t\tdest_addr = rte_pktmbuf_mtophys_offset(op->sym->m_dst,\n+\t\t\t\t\t\top->sym->cipher.data.offset);\n+\telse\n+\t\tdest_addr = src_addr;\n+\tkey_addr = session->cipher.key_phys;\n+\n+\t/* prepare desc for aes command */\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_AES;\n+\tCCP_CMD_INIT(desc) = 1;\n+\tCCP_CMD_EOM(desc) = 1;\n+\n+\tCCP_AES_ENCRYPT(&function) = session->cipher.dir;\n+\tCCP_AES_MODE(&function) = session->cipher.um.aes_mode;\n+\tCCP_AES_TYPE(&function) = session->cipher.ut.aes_type;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\tCCP_CMD_LEN(desc) = op->sym->cipher.data.length;\n+\n+\tCCP_CMD_SRC_LO(desc) = ((uint32_t)src_addr);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(src_addr);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_DST_LO(desc) = ((uint32_t)dest_addr);\n+\tCCP_CMD_DST_HI(desc) = high32_value(dest_addr);\n+\tCCP_CMD_DST_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_KEY_LO(desc) = ((uint32_t)key_addr);\n+\tCCP_CMD_KEY_HI(desc) = high32_value(key_addr);\n+\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tif (session->cipher.um.aes_mode != CCP_AES_MODE_ECB)\n+\t\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_iv;\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\top->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\treturn 0;\n+}\n+\n+static int\n+ccp_perform_3des(struct rte_crypto_op *op,\n+\t\tstruct ccp_queue *cmd_q,\n+\t\tstruct ccp_batch_info *b_info)\n+{\n+\tstruct ccp_session *session;\n+\tunion ccp_function function;\n+\tunsigned char *lsb_buf;\n+\tstruct ccp_passthru pst;\n+\tstruct ccp_desc *desc;\n+\tuint32_t tail;\n+\tuint8_t *iv;\n+\tphys_addr_t src_addr, dest_addr, key_addr;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\n+\tiv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset);\n+\tswitch (session->cipher.um.des_mode) {\n+\tcase CCP_DES_MODE_CBC:\n+\t\tlsb_buf = &(b_info->lsb_buf[b_info->lsb_buf_idx*CCP_SB_BYTES]);\n+\t\tb_info->lsb_buf_idx++;\n+\n+\t\trte_memcpy(lsb_buf + (CCP_SB_BYTES - session->iv.length),\n+\t\t\t iv, session->iv.length);\n+\n+\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *) lsb_buf);\n+\t\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES);\n+\t\tpst.len = CCP_SB_BYTES;\n+\t\tpst.dir = 1;\n+\t\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\t\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_256BIT;\n+\t\tccp_perform_passthru(&pst, cmd_q);\n+\t\tbreak;\n+\tcase CCP_DES_MODE_CFB:\n+\tcase CCP_DES_MODE_ECB:\n+\t\tCCP_LOG_ERR(\"Unsupported DES cipher mode\");\n+\t\treturn -1;\n+\t}\n+\n+\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\t\t\t\t\t op->sym->cipher.data.offset);\n+\tif (unlikely(op->sym->m_dst != NULL))\n+\t\tdest_addr =\n+\t\t\trte_pktmbuf_mtophys_offset(op->sym->m_dst,\n+\t\t\t\t\t\t op->sym->cipher.data.offset);\n+\telse\n+\t\tdest_addr = src_addr;\n+\n+\tkey_addr = rte_mem_virt2phy(session->cipher.key_ccp);\n+\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\n+\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\t/* prepare desc for des command */\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_3DES;\n+\n+\tCCP_CMD_SOC(desc) = 0;\n+\tCCP_CMD_IOC(desc) = 0;\n+\tCCP_CMD_INIT(desc) = 1;\n+\tCCP_CMD_EOM(desc) = 1;\n+\tCCP_CMD_PROT(desc) = 0;\n+\n+\tfunction.raw = 0;\n+\tCCP_DES_ENCRYPT(&function) = session->cipher.dir;\n+\tCCP_DES_MODE(&function) = session->cipher.um.des_mode;\n+\tCCP_DES_TYPE(&function) = session->cipher.ut.des_type;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\tCCP_CMD_LEN(desc) = op->sym->cipher.data.length;\n+\n+\tCCP_CMD_SRC_LO(desc) = ((uint32_t)src_addr);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(src_addr);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_DST_LO(desc) = ((uint32_t)dest_addr);\n+\tCCP_CMD_DST_HI(desc) = high32_value(dest_addr);\n+\tCCP_CMD_DST_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_KEY_LO(desc) = ((uint32_t)key_addr);\n+\tCCP_CMD_KEY_HI(desc) = high32_value(key_addr);\n+\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tif (session->cipher.um.des_mode)\n+\t\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_iv;\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\n+\trte_wmb();\n+\n+\t/* Write the new tail address back to the queue register */\n+\ttail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\t/* Turn the queue back on using our cached control register */\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\treturn 0;\n+}\n+\n+static int\n+ccp_perform_aes_gcm(struct rte_crypto_op *op, struct ccp_queue *cmd_q)\n+{\n+\tstruct ccp_session *session;\n+\tunion ccp_function function;\n+\tuint8_t *lsb_buf, *append_ptr, *iv;\n+\tstruct ccp_passthru pst;\n+\tstruct ccp_desc *desc;\n+\tuint32_t tail;\n+\tuint64_t *temp;\n+\tphys_addr_t src_addr, dest_addr, key_addr, aad_addr;\n+\tphys_addr_t digest_dest_addr;\n+\tint length, non_align_len, i;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\tiv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset);\n+\tkey_addr = rte_mem_virt2phy(session->cipher.key_ccp);\n+\n+\tsrc_addr = rte_pktmbuf_mtophys_offset(op->sym->m_src,\n+\t\t\t\t\t op->sym->cipher.data.offset);\n+\tif (unlikely(op->sym->m_dst != NULL))\n+\t\tdest_addr = rte_pktmbuf_mtophys_offset(op->sym->m_dst,\n+\t\t\t\t\t\top->sym->cipher.data.offset);\n+\telse\n+\t\tdest_addr = src_addr;\n+\tappend_ptr = (uint8_t *)rte_pktmbuf_append(op->sym->m_src,\n+\t\t\t\t\t\t session->auth.ctx_len);\n+\tdigest_dest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr);\n+\tappend_ptr += AES_BLOCK_SIZE;\n+\ttemp = (uint64_t *)append_ptr;\n+\t*temp++ = rte_bswap64(session->auth.aad_length << 3);\n+\t*temp = rte_bswap64(op->sym->cipher.data.length << 3);\n+\n+\tnon_align_len = op->sym->cipher.data.length % AES_BLOCK_SIZE;\n+\tlength = CCP_ALIGN(op->sym->cipher.data.length, AES_BLOCK_SIZE);\n+\n+\taad_addr = rte_mem_virt2phy((void *)op->sym->aead.aad.data);\n+\n+\t/* CMD1 IV Passthru */\n+\tfor (i = 0; i < CTR_IV_SIZE; i++)\n+\t\tsession->cipher.nonce[CTR_NONCE_SIZE + CTR_IV_SIZE - 1 - i] =\n+\t\t\tiv[i];\n+\tlsb_buf = session->cipher.nonce;\n+\n+\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *) lsb_buf);\n+\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES);\n+\tpst.len = CCP_SB_BYTES;\n+\tpst.dir = 1;\n+\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;\n+\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t/* CMD2 GHASH-AAD */\n+\tfunction.raw = 0;\n+\tCCP_AES_ENCRYPT(&function) = CCP_AES_MODE_GHASH_AAD;\n+\tCCP_AES_MODE(&function) = CCP_AES_MODE_GHASH;\n+\tCCP_AES_TYPE(&function) = session->cipher.ut.aes_type;\n+\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_AES;\n+\tCCP_CMD_INIT(desc) = 1;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\tCCP_CMD_LEN(desc) = session->auth.aad_length;\n+\n+\tCCP_CMD_SRC_LO(desc) = ((uint32_t)aad_addr);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(aad_addr);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_KEY_LO(desc) = ((uint32_t)key_addr);\n+\tCCP_CMD_KEY_HI(desc) = high32_value(key_addr);\n+\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_iv;\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\trte_wmb();\n+\n+\ttail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\t/* CMD3 : GCTR Plain text */\n+\tfunction.raw = 0;\n+\tCCP_AES_ENCRYPT(&function) = session->cipher.dir;\n+\tCCP_AES_MODE(&function) = CCP_AES_MODE_GCTR;\n+\tCCP_AES_TYPE(&function) = session->cipher.ut.aes_type;\n+\tif (non_align_len == 0)\n+\t\tCCP_AES_SIZE(&function) = (AES_BLOCK_SIZE << 3) - 1;\n+\telse\n+\t\tCCP_AES_SIZE(&function) = (non_align_len << 3) - 1;\n+\n+\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_AES;\n+\tCCP_CMD_EOM(desc) = 1;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\n+\tCCP_CMD_LEN(desc) = length;\n+\n+\tCCP_CMD_SRC_LO(desc) = ((uint32_t)src_addr);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(src_addr);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_DST_LO(desc) = ((uint32_t)dest_addr);\n+\tCCP_CMD_DST_HI(desc) = high32_value(dest_addr);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_KEY_LO(desc) = ((uint32_t)key_addr);\n+\tCCP_CMD_KEY_HI(desc) = high32_value(key_addr);\n+\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_iv;\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\trte_wmb();\n+\n+\ttail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\t/* CMD4 : PT to copy IV */\n+\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *) lsb_buf);\n+\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES);\n+\tpst.len = AES_BLOCK_SIZE;\n+\tpst.dir = 1;\n+\tpst.bit_mod = CCP_PASSTHRU_BITWISE_NOOP;\n+\tpst.byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;\n+\tccp_perform_passthru(&pst, cmd_q);\n+\n+\t/* CMD5 : GHASH-Final */\n+\tfunction.raw = 0;\n+\tCCP_AES_ENCRYPT(&function) = CCP_AES_MODE_GHASH_FINAL;\n+\tCCP_AES_MODE(&function) = CCP_AES_MODE_GHASH;\n+\tCCP_AES_TYPE(&function) = session->cipher.ut.aes_type;\n+\n+\tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n+\tmemset(desc, 0, Q_DESC_SIZE);\n+\n+\tCCP_CMD_ENGINE(desc) = CCP_ENGINE_AES;\n+\tCCP_CMD_FUNCTION(desc) = function.raw;\n+\t/* Last block (AAD_len || PT_len)*/\n+\tCCP_CMD_LEN(desc) = AES_BLOCK_SIZE;\n+\n+\tCCP_CMD_SRC_LO(desc) = ((uint32_t)digest_dest_addr + AES_BLOCK_SIZE);\n+\tCCP_CMD_SRC_HI(desc) = high32_value(digest_dest_addr + AES_BLOCK_SIZE);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_DST_LO(desc) = ((uint32_t)digest_dest_addr);\n+\tCCP_CMD_DST_HI(desc) = high32_value(digest_dest_addr);\n+\tCCP_CMD_SRC_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_KEY_LO(desc) = ((uint32_t)key_addr);\n+\tCCP_CMD_KEY_HI(desc) = high32_value(key_addr);\n+\tCCP_CMD_KEY_MEM(desc) = CCP_MEMTYPE_SYSTEM;\n+\n+\tCCP_CMD_LSB_ID(desc) = cmd_q->sb_iv;\n+\n+\tcmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;\n+\trte_wmb();\n+\n+\ttail = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx * Q_DESC_SIZE);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, tail);\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\treturn 0;\n+}\n+\n+static inline int\n+ccp_crypto_cipher(struct rte_crypto_op *op,\n+\t\t struct ccp_queue *cmd_q,\n+\t\t struct ccp_batch_info *b_info)\n+{\n+\tint result;\n+\tstruct ccp_session *session;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\n+\tswitch (session->cipher.algo) {\n+\tcase CCP_CIPHER_ALGO_AES_CBC:\n+\t\tresult = ccp_perform_aes(op, cmd_q, b_info);\n+\t\tb_info->desccnt += 2;\n+\t\tbreak;\n+\tcase CCP_CIPHER_ALGO_AES_CTR:\n+\t\tresult = ccp_perform_aes(op, cmd_q, b_info);\n+\t\tb_info->desccnt += 2;\n+\t\tbreak;\n+\tcase CCP_CIPHER_ALGO_AES_ECB:\n+\t\tresult = ccp_perform_aes(op, cmd_q, b_info);\n+\t\tb_info->desccnt += 1;\n+\t\tbreak;\n+\tcase CCP_CIPHER_ALGO_3DES_CBC:\n+\t\tresult = ccp_perform_3des(op, cmd_q, b_info);\n+\t\tb_info->desccnt += 2;\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported Cipher algo\");\n+\t\tresult = -1;\n+\t}\n+\treturn result;\n+}\n+\n+static inline int\n+ccp_crypto_auth(struct rte_crypto_op *op,\n+\t\tstruct ccp_queue *cmd_q,\n+\t\tstruct ccp_batch_info *b_info)\n+{\n+\n+\tint result = 0;\n+\tstruct ccp_session *session;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\n+\tswitch (session->auth.algo) {\n+\tcase CCP_AUTH_ALGO_SHA1:\n+\tcase CCP_AUTH_ALGO_SHA224:\n+\tcase CCP_AUTH_ALGO_SHA256:\n+\tcase CCP_AUTH_ALGO_SHA384:\n+\tcase CCP_AUTH_ALGO_SHA512:\n+\t\tresult = ccp_perform_sha(op, cmd_q);\n+\t\tb_info->desccnt += 3;\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA1_HMAC:\n+\tcase CCP_AUTH_ALGO_SHA224_HMAC:\n+\tcase CCP_AUTH_ALGO_SHA256_HMAC:\n+\t\tresult = ccp_perform_hmac(op, cmd_q);\n+\t\tb_info->desccnt += 6;\n+\t\tbreak;\n+\n+\tcase CCP_AUTH_ALGO_SHA384_HMAC:\n+\tcase CCP_AUTH_ALGO_SHA512_HMAC:\n+\t\tresult = ccp_perform_hmac(op, cmd_q);\n+\t\tb_info->desccnt += 7;\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA3_224:\n+\tcase CCP_AUTH_ALGO_SHA3_256:\n+\tcase CCP_AUTH_ALGO_SHA3_384:\n+\tcase CCP_AUTH_ALGO_SHA3_512:\n+\t\tresult = ccp_perform_sha3(op, cmd_q);\n+\t\tb_info->desccnt += 1;\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA3_224_HMAC:\n+\tcase CCP_AUTH_ALGO_SHA3_256_HMAC:\n+\t\tresult = ccp_perform_sha3_hmac(op, cmd_q);\n+\t\tb_info->desccnt += 3;\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_SHA3_384_HMAC:\n+\tcase CCP_AUTH_ALGO_SHA3_512_HMAC:\n+\t\tresult = ccp_perform_sha3_hmac(op, cmd_q);\n+\t\tb_info->desccnt += 4;\n+\t\tbreak;\n+\tcase CCP_AUTH_ALGO_AES_CMAC:\n+\t\tresult = ccp_perform_aes_cmac(op, cmd_q);\n+\t\tb_info->desccnt += 4;\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported Cipher algo\");\n+\t\tresult = -1;\n+\t}\n+\n+\treturn result;\n+}\n+\n+static inline int\n+ccp_crypto_combined(struct rte_crypto_op *op,\n+\t\t struct ccp_queue *cmd_q __rte_unused,\n+\t\t struct ccp_batch_info *b_info __rte_unused)\n+{\n+\tint result = 0;\n+\tstruct ccp_session *session;\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\n+\tswitch (session->auth.algo) {\n+\tcase CCP_AUTH_ALGO_AES_GCM:\n+\t\tif (session->cipher.algo != CCP_CIPHER_ALGO_AES_GCM) {\n+\t\t\tCCP_LOG_ERR(\"Incorrect chain order\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tresult = ccp_perform_aes_gcm(op, cmd_q);\n+\t\tb_info->desccnt += 5;\n+\t\tbreak;\n+\tdefault:\n+\t\tCCP_LOG_ERR(\"Unsupported combined algo\");\n+\t\treturn -1;\n+\t}\n+\treturn result;\n+}\n+\n+int\n+process_ops_to_enqueue(const struct ccp_qp *qp,\n+\t\t struct rte_crypto_op **op,\n+\t\t struct ccp_queue *cmd_q,\n+\t\t uint16_t nb_ops,\n+\t\t int slots_req)\n+{\n+\tint i, result = 0;\n+\tstruct ccp_batch_info *b_info;\n+\tstruct ccp_session *session;\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\tEVP_MD_CTX *auth_ctx = NULL;\n+#endif\n+\n+\tif (rte_mempool_get(qp->batch_mp, (void **)&b_info)) {\n+\t\tCCP_LOG_ERR(\"batch info allocation failed\");\n+\t\treturn 0;\n+\t}\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\tauth_ctx = EVP_MD_CTX_create();\n+\tif (unlikely(!auth_ctx)) {\n+\t\tCCP_LOG_ERR(\"Unable to create auth ctx\");\n+\t\treturn 0;\n+\t}\n+\tb_info->auth_only = 1;\n+#endif\n+\t/* populate batch info necessary for dequeue */\n+\tb_info->op_idx = 0;\n+\tb_info->lsb_buf_idx = 0;\n+\tb_info->desccnt = 0;\n+\tb_info->cmd_q = cmd_q;\n+\tb_info->lsb_buf_phys =\n+\t\t(phys_addr_t)rte_mem_virt2phy((void *)b_info->lsb_buf);\n+\trte_atomic64_sub(&b_info->cmd_q->free_slots, slots_req);\n+\n+\tb_info->head_offset = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx *\n+\t\t\t\t\t Q_DESC_SIZE);\n+\tfor (i = 0; i < nb_ops; i++) {\n+\t\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t\t op[i]->sym->session,\n+\t\t\t\t\t\t cryptodev_driver_id);\n+\t\tswitch (session->cmd_id) {\n+\t\tcase CCP_CMD_CIPHER:\n+\t\t\tresult = ccp_crypto_cipher(op[i], cmd_q, b_info);\n+\t\t\tbreak;\n+\t\tcase CCP_CMD_AUTH:\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\t\t\tresult = ccp_crypto_auth(op[i], cmd_q, b_info);\n+#else\n+\t\t\tresult = cpu_crypto_auth(op[i], session, auth_ctx);\n+#endif\n+\t\t\tbreak;\n+\t\tcase CCP_CMD_CIPHER_HASH:\n+\t\t\tresult = ccp_crypto_cipher(op[i], cmd_q, b_info);\n+\t\t\tif (result)\n+\t\t\t\tbreak;\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\t\t\tresult = ccp_crypto_auth(op[i], cmd_q, b_info);\n+#else\n+\t\t\tb_info->auth_only = 0;\n+#endif\n+\t\t\tbreak;\n+\t\tcase CCP_CMD_HASH_CIPHER:\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\t\t\tresult = ccp_crypto_auth(op[i], cmd_q, b_info);\n+#else\n+\t\t\tresult = cpu_crypto_auth(op[i], session, auth_ctx);\n+\t\t\tb_info->auth_only = 0;\n+#endif\n+\t\t\tif (result)\n+\t\t\t\tbreak;\n+\t\t\tresult = ccp_crypto_cipher(op[i], cmd_q, b_info);\n+\t\t\tbreak;\n+\t\tcase CCP_CMD_COMBINED:\n+\t\t\tresult = ccp_crypto_combined(op[i], cmd_q, b_info);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tCCP_LOG_ERR(\"Unsupported cmd_id\");\n+\t\t\tresult = -1;\n+\t\t}\n+\t\tif (unlikely(result < 0)) {\n+\t\t\trte_atomic64_add(&b_info->cmd_q->free_slots,\n+\t\t\t\t\t (slots_req - b_info->desccnt));\n+\t\t\tbreak;\n+\t\t}\n+\t\tb_info->op[i] = op[i];\n+\t}\n+\n+\tb_info->opcnt = i;\n+\tb_info->tail_offset = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx *\n+\t\t\t\t\t Q_DESC_SIZE);\n+\n+\trte_wmb();\n+\t/* Write the new tail address back to the queue register */\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE,\n+\t\t\t b_info->tail_offset);\n+\t/* Turn the queue back on using our cached control register */\n+\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t\t cmd_q->qcontrol | CMD_Q_RUN);\n+\n+\trte_ring_enqueue(qp->processed_pkts, (void *)b_info);\n+\n+\treturn i;\n+}\n+\n+static inline void ccp_auth_dq_prepare(struct rte_crypto_op *op)\n+{\n+\tstruct ccp_session *session;\n+\tuint8_t *digest_addr, *addr;\n+\tstruct rte_mbuf *m_last;\n+\tint offset;\n+\tuint8_t digest_le[64];\n+\n+\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t op->sym->session,\n+\t\t\t\t\t cryptodev_driver_id);\n+\n+\tm_last = rte_pktmbuf_lastseg(op->sym->m_src);\n+\taddr = (uint8_t *)((char *)m_last->buf_addr + m_last->data_off +\n+\t\t\t m_last->data_len - session->auth.ctx_len);\n+\n+\trte_mb();\n+\toffset = session->auth.offset;\n+\tif (session->auth.engine == CCP_ENGINE_SHA)\n+\t\tif ((session->auth.ut.sha_type != CCP_SHA_TYPE_1) &&\n+\t\t (session->auth.ut.sha_type != CCP_SHA_TYPE_224) &&\n+\t\t (session->auth.ut.sha_type != CCP_SHA_TYPE_256)) {\n+\t\t\t/* All other algorithms require byte\n+\t\t\t * swap done by host\n+\t\t\t */\n+\t\t\tunsigned int i;\n+\n+\t\t\toffset = session->auth.ctx_len -\n+\t\t\t\tsession->auth.offset - 1;\n+\t\t\tfor (i = 0; i < session->auth.digest_length; i++)\n+\t\t\t\tdigest_le[i] = addr[offset - i];\n+\t\t\toffset = 0;\n+\t\t\taddr = digest_le;\n+\t\t}\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\tif (session->auth.op == CCP_AUTH_OP_VERIFY) {\n+\t\tif (memcmp(addr + offset,\n+\t\t\t op->sym->auth.digest.data,\n+\t\t\t session->auth.digest_length)\n+\t\t != 0)\n+\t\t\top->status =\n+\t\t\t\tRTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\n+\t} else {\n+\t\tdigest_addr = op->sym->auth.digest.data;\n+\t\tif (unlikely(digest_addr == 0))\n+\t\t\tdigest_addr = rte_pktmbuf_mtod_offset(\n+\t\t\t\t\top->sym->m_dst,\n+\t\t\t\t\tuint8_t *,\n+\t\t\t\t\t(op->sym->auth.data.offset +\n+\t\t\t\t\t op->sym->auth.data.length));\n+\t\trte_memcpy(digest_addr, addr + offset,\n+\t\t\t session->auth.digest_length);\n+\t}\n+\t/* Trim area used for digest from mbuf. */\n+\trte_pktmbuf_trim(op->sym->m_src,\n+\t\t\t session->auth.ctx_len);\n+}\n+\n+static int\n+ccp_prepare_ops(struct rte_crypto_op **op_d,\n+\t\tstruct ccp_batch_info *b_info,\n+\t\tuint16_t nb_ops)\n+{\n+\tint i, min_ops;\n+\tstruct ccp_session *session;\n+\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\tEVP_MD_CTX *auth_ctx = NULL;\n+\n+\tauth_ctx = EVP_MD_CTX_create();\n+\tif (unlikely(!auth_ctx)) {\n+\t\tCCP_LOG_ERR(\"Unable to create auth ctx\");\n+\t\treturn 0;\n+\t}\n+#endif\n+\tmin_ops = RTE_MIN(nb_ops, b_info->opcnt);\n+\n+\tfor (i = 0; i < min_ops; i++) {\n+\t\top_d[i] = b_info->op[b_info->op_idx++];\n+\t\tsession = (struct ccp_session *)get_session_private_data(\n+\t\t\t\t\t\t op_d[i]->sym->session,\n+\t\t\t\t\t\t cryptodev_driver_id);\n+\t\tswitch (session->cmd_id) {\n+\t\tcase CCP_CMD_CIPHER:\n+\t\t\top_d[i]->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t\tbreak;\n+\t\tcase CCP_CMD_AUTH:\n+#ifndef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\t\t\tccp_auth_dq_prepare(op_d[i]);\n+#endif\n+\t\t\tbreak;\n+\t\tcase CCP_CMD_CIPHER_HASH:\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\t\t\tcpu_crypto_auth(op_d[i], session, auth_ctx);\n+#else\n+\t\t\tccp_auth_dq_prepare(op_d[i]);\n+#endif\n+\t\t\tbreak;\n+\t\tcase CCP_CMD_HASH_CIPHER:\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\t\t\tif (!cpu_auth_verify(op_d[i]))\n+\t\t\t\top_d[i]->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t\telse\n+\t\t\t\top_d[i]->status =\n+\t\t\t\t\tRTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+#else\n+\t\t\tccp_auth_dq_prepare(op_d[i]);\n+#endif\n+\t\t\tbreak;\n+\t\tcase CCP_CMD_COMBINED:\n+\t\t\tccp_auth_dq_prepare(op_d[i]);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tCCP_LOG_ERR(\"Unsupported cmd_id\");\n+\t\t}\n+\t}\n+\n+\tb_info->opcnt -= min_ops;\n+\treturn min_ops;\n+}\n+\n+int\n+process_ops_to_dequeue(struct ccp_qp *qp,\n+\t\t struct rte_crypto_op **op,\n+\t\t uint16_t nb_ops)\n+{\n+\tstruct ccp_batch_info *b_info;\n+\tuint32_t cur_head_offset;\n+\n+\tif (qp->b_info != NULL) {\n+\t\tb_info = qp->b_info;\n+\t\tif (unlikely(b_info->op_idx > 0))\n+\t\t\tgoto success;\n+\t} else if (rte_ring_dequeue(qp->processed_pkts,\n+\t\t\t\t (void **)&b_info))\n+\t\treturn 0;\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\tif (b_info->auth_only == 1)\n+\t\tgoto success;\n+#endif\n+\tcur_head_offset = CCP_READ_REG(b_info->cmd_q->reg_base,\n+\t\t\t\t CMD_Q_HEAD_LO_BASE);\n+\n+\tif (b_info->head_offset < b_info->tail_offset) {\n+\t\tif ((cur_head_offset >= b_info->head_offset) &&\n+\t\t (cur_head_offset < b_info->tail_offset)) {\n+\t\t\tqp->b_info = b_info;\n+\t\t\treturn 0;\n+\t\t}\n+\t} else {\n+\t\tif ((cur_head_offset >= b_info->head_offset) ||\n+\t\t (cur_head_offset < b_info->tail_offset)) {\n+\t\t\tqp->b_info = b_info;\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\n+success:\n+\tnb_ops = ccp_prepare_ops(op, b_info, nb_ops);\n+\trte_atomic64_add(&b_info->cmd_q->free_slots, b_info->desccnt);\n+\tb_info->desccnt = 0;\n+\tif (b_info->opcnt > 0) {\n+\t\tqp->b_info = b_info;\n+\t} else {\n+\t\trte_mempool_put(qp->batch_mp, (void *)b_info);\n+\t\tqp->b_info = NULL;\n+\t}\n+\n+\treturn nb_ops;\n+}\ndiff --git a/drivers/crypto/ccp/ccp_crypto.h b/drivers/crypto/ccp/ccp_crypto.h\nnew file mode 100644\nindex 0000000..b74cbe0\n--- /dev/null\n+++ b/drivers/crypto/ccp/ccp_crypto.h\n@@ -0,0 +1,411 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2017 Advance Micro Devices, Inc. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Advance Micro Devices, Inc nor the names\n+ * of its contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written\n+ * permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _CCP_CRYPTO_H_\n+#define _CCP_CRYPTO_H_\n+\n+#include <limits.h>\n+#include <stdbool.h>\n+#include <stdint.h>\n+#include <string.h>\n+\n+#include <rte_atomic.h>\n+#include <rte_byteorder.h>\n+#include <rte_io.h>\n+#include <rte_pci.h>\n+#include <rte_spinlock.h>\n+#include <rte_crypto_sym.h>\n+#include <rte_cryptodev.h>\n+\n+#include <ccp_dev.h>\n+\n+#define AES_BLOCK_SIZE 16\n+#define CMAC_PAD_VALUE 0x80\n+#define CTR_NONCE_SIZE 4\n+#define CTR_IV_SIZE 8\n+#define CCP_SHA3_CTX_SIZE 200\n+\n+/**Macro helpers for CCP command creation*/\n+#define\tCCP_AES_SIZE(p)\t\t((p)->aes.size)\n+#define\tCCP_AES_ENCRYPT(p)\t((p)->aes.encrypt)\n+#define\tCCP_AES_MODE(p)\t\t((p)->aes.mode)\n+#define\tCCP_AES_TYPE(p)\t\t((p)->aes.type)\n+#define\tCCP_DES_ENCRYPT(p)\t((p)->des.encrypt)\n+#define\tCCP_DES_MODE(p)\t\t((p)->des.mode)\n+#define\tCCP_DES_TYPE(p)\t\t((p)->des.type)\n+#define\tCCP_SHA_TYPE(p)\t\t((p)->sha.type)\n+#define\tCCP_PT_BYTESWAP(p)\t((p)->pt.byteswap)\n+#define\tCCP_PT_BITWISE(p)\t((p)->pt.bitwise)\n+\n+/**HMAC*/\n+#define HMAC_IPAD_VALUE 0x36\n+#define HMAC_OPAD_VALUE 0x5c\n+\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+#define MD5_DIGEST_SIZE 16\n+#define MD5_BLOCK_SIZE 64\n+#endif\n+\n+/**SHA */\n+#define SHA1_DIGEST_SIZE 20\n+#define SHA1_BLOCK_SIZE 64\n+\n+#define SHA224_DIGEST_SIZE 28\n+#define SHA224_BLOCK_SIZE 64\n+#define SHA3_224_BLOCK_SIZE 144\n+\n+#define SHA256_DIGEST_SIZE 32\n+#define SHA256_BLOCK_SIZE 64\n+#define SHA3_256_BLOCK_SIZE 136\n+\n+#define SHA384_DIGEST_SIZE 48\n+#define SHA384_BLOCK_SIZE 128\n+#define SHA3_384_BLOCK_SIZE\t104\n+\n+#define SHA512_DIGEST_SIZE 64\n+#define SHA512_BLOCK_SIZE 128\n+#define SHA3_512_BLOCK_SIZE 72\n+\n+/**SHA LSB intialiazation values*/\n+\n+#define SHA1_H0\t\t0x67452301UL\n+#define SHA1_H1\t\t0xefcdab89UL\n+#define SHA1_H2\t\t0x98badcfeUL\n+#define SHA1_H3\t\t0x10325476UL\n+#define SHA1_H4\t\t0xc3d2e1f0UL\n+\n+#define SHA224_H0\t0xc1059ed8UL\n+#define SHA224_H1\t0x367cd507UL\n+#define SHA224_H2\t0x3070dd17UL\n+#define SHA224_H3\t0xf70e5939UL\n+#define SHA224_H4\t0xffc00b31UL\n+#define SHA224_H5\t0x68581511UL\n+#define SHA224_H6\t0x64f98fa7UL\n+#define SHA224_H7\t0xbefa4fa4UL\n+\n+#define SHA256_H0\t0x6a09e667UL\n+#define SHA256_H1\t0xbb67ae85UL\n+#define SHA256_H2\t0x3c6ef372UL\n+#define SHA256_H3\t0xa54ff53aUL\n+#define SHA256_H4\t0x510e527fUL\n+#define SHA256_H5\t0x9b05688cUL\n+#define SHA256_H6\t0x1f83d9abUL\n+#define SHA256_H7\t0x5be0cd19UL\n+\n+#define SHA384_H0\t0xcbbb9d5dc1059ed8ULL\n+#define SHA384_H1\t0x629a292a367cd507ULL\n+#define SHA384_H2\t0x9159015a3070dd17ULL\n+#define SHA384_H3\t0x152fecd8f70e5939ULL\n+#define SHA384_H4\t0x67332667ffc00b31ULL\n+#define SHA384_H5\t0x8eb44a8768581511ULL\n+#define SHA384_H6\t0xdb0c2e0d64f98fa7ULL\n+#define SHA384_H7\t0x47b5481dbefa4fa4ULL\n+\n+#define SHA512_H0\t0x6a09e667f3bcc908ULL\n+#define SHA512_H1\t0xbb67ae8584caa73bULL\n+#define SHA512_H2\t0x3c6ef372fe94f82bULL\n+#define SHA512_H3\t0xa54ff53a5f1d36f1ULL\n+#define SHA512_H4\t0x510e527fade682d1ULL\n+#define SHA512_H5\t0x9b05688c2b3e6c1fULL\n+#define SHA512_H6\t0x1f83d9abfb41bd6bULL\n+#define SHA512_H7\t0x5be0cd19137e2179ULL\n+\n+/**\n+ * CCP supported AES modes\n+ */\n+enum ccp_aes_mode {\n+\tCCP_AES_MODE_ECB = 0,\n+\tCCP_AES_MODE_CBC,\n+\tCCP_AES_MODE_OFB,\n+\tCCP_AES_MODE_CFB,\n+\tCCP_AES_MODE_CTR,\n+\tCCP_AES_MODE_CMAC,\n+\tCCP_AES_MODE_GHASH,\n+\tCCP_AES_MODE_GCTR,\n+\tCCP_AES_MODE__LAST,\n+};\n+\n+/**\n+ * CCP AES GHASH mode\n+ */\n+enum ccp_aes_ghash_mode {\n+\tCCP_AES_MODE_GHASH_AAD = 0,\n+\tCCP_AES_MODE_GHASH_FINAL\n+};\n+\n+/**\n+ * CCP supported AES types\n+ */\n+enum ccp_aes_type {\n+\tCCP_AES_TYPE_128 = 0,\n+\tCCP_AES_TYPE_192,\n+\tCCP_AES_TYPE_256,\n+\tCCP_AES_TYPE__LAST,\n+};\n+\n+/***** 3DES engine *****/\n+\n+/**\n+ * CCP supported DES/3DES modes\n+ */\n+enum ccp_des_mode {\n+\tCCP_DES_MODE_ECB = 0, /* Not supported */\n+\tCCP_DES_MODE_CBC,\n+\tCCP_DES_MODE_CFB,\n+};\n+\n+/**\n+ * CCP supported DES types\n+ */\n+enum ccp_des_type {\n+\tCCP_DES_TYPE_128 = 0,\t/* 112 + 16 parity */\n+\tCCP_DES_TYPE_192,\t/* 168 + 24 parity */\n+\tCCP_DES_TYPE__LAST,\n+};\n+\n+/***** SHA engine *****/\n+\n+/**\n+ * ccp_sha_type - type of SHA operation\n+ *\n+ * @CCP_SHA_TYPE_1: SHA-1 operation\n+ * @CCP_SHA_TYPE_224: SHA-224 operation\n+ * @CCP_SHA_TYPE_256: SHA-256 operation\n+ */\n+enum ccp_sha_type {\n+\tCCP_SHA_TYPE_1 = 1,\n+\tCCP_SHA_TYPE_224,\n+\tCCP_SHA_TYPE_256,\n+\tCCP_SHA_TYPE_384,\n+\tCCP_SHA_TYPE_512,\n+\tCCP_SHA_TYPE_RSVD1,\n+\tCCP_SHA_TYPE_RSVD2,\n+\tCCP_SHA3_TYPE_224,\n+\tCCP_SHA3_TYPE_256,\n+\tCCP_SHA3_TYPE_384,\n+\tCCP_SHA3_TYPE_512,\n+\tCCP_SHA_TYPE__LAST,\n+};\n+\n+/**\n+ * CCP supported cipher algorithms\n+ */\n+enum ccp_cipher_algo {\n+\tCCP_CIPHER_ALGO_AES_CBC = 0,\n+\tCCP_CIPHER_ALGO_AES_ECB,\n+\tCCP_CIPHER_ALGO_AES_CTR,\n+\tCCP_CIPHER_ALGO_AES_GCM,\n+\tCCP_CIPHER_ALGO_3DES_CBC,\n+};\n+\n+/**\n+ * CCP cipher operation type\n+ */\n+enum ccp_cipher_dir {\n+\tCCP_CIPHER_DIR_DECRYPT = 0,\n+\tCCP_CIPHER_DIR_ENCRYPT = 1,\n+};\n+\n+/**\n+ * CCP supported hash algorithms\n+ */\n+enum ccp_hash_algo {\n+\tCCP_AUTH_ALGO_SHA1 = 0,\n+\tCCP_AUTH_ALGO_SHA1_HMAC,\n+\tCCP_AUTH_ALGO_SHA224,\n+\tCCP_AUTH_ALGO_SHA224_HMAC,\n+\tCCP_AUTH_ALGO_SHA3_224,\n+\tCCP_AUTH_ALGO_SHA3_224_HMAC,\n+\tCCP_AUTH_ALGO_SHA256,\n+\tCCP_AUTH_ALGO_SHA256_HMAC,\n+\tCCP_AUTH_ALGO_SHA3_256,\n+\tCCP_AUTH_ALGO_SHA3_256_HMAC,\n+\tCCP_AUTH_ALGO_SHA384,\n+\tCCP_AUTH_ALGO_SHA384_HMAC,\n+\tCCP_AUTH_ALGO_SHA3_384,\n+\tCCP_AUTH_ALGO_SHA3_384_HMAC,\n+\tCCP_AUTH_ALGO_SHA512,\n+\tCCP_AUTH_ALGO_SHA512_HMAC,\n+\tCCP_AUTH_ALGO_SHA3_512,\n+\tCCP_AUTH_ALGO_SHA3_512_HMAC,\n+\tCCP_AUTH_ALGO_AES_CMAC,\n+\tCCP_AUTH_ALGO_AES_GCM,\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\tCCP_AUTH_ALGO_MD5_HMAC,\n+#endif\n+};\n+\n+/**\n+ * CCP hash operation type\n+ */\n+enum ccp_hash_op {\n+\tCCP_AUTH_OP_GENERATE = 0,\n+\tCCP_AUTH_OP_VERIFY = 1,\n+};\n+\n+/* CCP crypto private session structure */\n+struct ccp_session {\n+\tenum ccp_cmd_order cmd_id;\n+\t/**< chain order mode */\n+\tstruct {\n+\t\tuint16_t length;\n+\t\tuint16_t offset;\n+\t} iv;\n+\t/**< IV parameters */\n+\tstruct {\n+\t\tenum ccp_cipher_algo algo;\n+\t\tenum ccp_engine engine;\n+\t\tunion {\n+\t\t\tenum ccp_aes_mode aes_mode;\n+\t\t\tenum ccp_des_mode des_mode;\n+\t\t} um;\n+\t\tunion {\n+\t\t\tenum ccp_aes_type aes_type;\n+\t\t\tenum ccp_des_type des_type;\n+\t\t} ut;\n+\t\tenum ccp_cipher_dir dir;\n+\t\tuint64_t key_length;\n+\t\t/**< max cipher key size 256 bits */\n+\t\tuint8_t key[32];\n+\t\t/**ccp key format*/\n+\t\tuint8_t key_ccp[32];\n+\t\tphys_addr_t key_phys;\n+\t\t/**AES-ctr nonce(4) iv(8) ctr*/\n+\t\tuint8_t nonce[32];\n+\t\tphys_addr_t nonce_phys;\n+\t} cipher;\n+\t/**< Cipher Parameters */\n+\n+\tstruct {\n+\t\tenum ccp_hash_algo algo;\n+\t\tenum ccp_engine engine;\n+\t\tunion {\n+\t\t\tenum ccp_aes_mode aes_mode;\n+\t\t} um;\n+\t\tunion {\n+\t\t\tenum ccp_sha_type sha_type;\n+\t\t\tenum ccp_aes_type aes_type;\n+\t\t} ut;\n+\t\tenum ccp_hash_op op;\n+\t\tuint64_t key_length;\n+\t\t/**< max hash key size 144 bytes (struct capabilties) */\n+\t\tuint8_t key[144];\n+\t\t/**< max be key size of AES-CMAC is 32*/\n+\t\tuint8_t key_ccp[32];\n+\t\tphys_addr_t key_phys;\n+\t\tuint64_t digest_length;\n+\t\tvoid *ctx;\n+\t\tint ctx_len;\n+\t\tint offset;\n+\t\tint block_size;\n+\t\t/**<Buffer to store Software generated precomute values*/\n+\t\t/**< For HMAC H(ipad ^ key) and H(opad ^ key) */\n+\t\t/**< For CMAC K1 IV and K2 IV*/\n+\t\tuint8_t pre_compute[2 * CCP_SHA3_CTX_SIZE];\n+\t\t/**<SHA3 initial ctx all zeros*/\n+\t\tuint8_t sha3_ctx[200];\n+\t\tint aad_length;\n+\t} auth;\n+\t/**< Authentication Parameters */\n+\tenum rte_crypto_aead_algorithm aead_algo;\n+\t/**< AEAD Algorithm */\n+\n+\tuint32_t reserved;\n+} __rte_cache_aligned;\n+\n+\n+struct ccp_qp;\n+\n+/**\n+ * Set and validate CCP crypto session parameters\n+ *\n+ * @param sess ccp private session\n+ * @param xform crypto xform for this session\n+ * @return 0 on success otherwise -1\n+ */\n+int ccp_set_session_parameters(struct ccp_session *sess,\n+\t\t\t const struct rte_crypto_sym_xform *xform);\n+\n+/**\n+ * Find count of slots\n+ *\n+ * @param session CCP private session\n+ * @return count of free slots available\n+ */\n+int ccp_compute_slot_count(struct ccp_session *session);\n+\n+/**\n+ * process crypto ops to be enqueued\n+ *\n+ * @param qp CCP crypto queue-pair\n+ * @param op crypto ops table\n+ * @param cmd_q CCP cmd queue\n+ * @param nb_ops No. of ops to be submitted\n+ * @return 0 on success otherwise -1\n+ */\n+int process_ops_to_enqueue(const struct ccp_qp *qp,\n+\t\t\t struct rte_crypto_op **op,\n+\t\t\t struct ccp_queue *cmd_q,\n+\t\t\t uint16_t nb_ops,\n+\t\t\t int slots_req);\n+\n+/**\n+ * process crypto ops to be dequeued\n+ *\n+ * @param qp CCP crypto queue-pair\n+ * @param op crypto ops table\n+ * @param nb_ops requested no. of ops\n+ * @return 0 on success otherwise -1\n+ */\n+int process_ops_to_dequeue(struct ccp_qp *qp,\n+\t\t\t struct rte_crypto_op **op,\n+\t\t\t uint16_t nb_ops);\n+\n+\n+/**\n+ * Apis for SHA3 partial hash generation\n+ * @param data_in buffer pointer on which phash is applied\n+ * @param data_out phash result in ccp be format is written\n+ */\n+int partial_hash_sha3_224(uint8_t *data_in,\n+\t\t\t uint8_t *data_out);\n+\n+int partial_hash_sha3_256(uint8_t *data_in,\n+\t\t\t uint8_t *data_out);\n+\n+int partial_hash_sha3_384(uint8_t *data_in,\n+\t\t\t uint8_t *data_out);\n+\n+int partial_hash_sha3_512(uint8_t *data_in,\n+\t\t\t uint8_t *data_out);\n+#endif /* _CCP_CRYPTO_H_ */\ndiff --git a/drivers/crypto/ccp/ccp_dev.c b/drivers/crypto/ccp/ccp_dev.c\nnew file mode 100644\nindex 0000000..2bf7e22\n--- /dev/null\n+++ b/drivers/crypto/ccp/ccp_dev.c\n@@ -0,0 +1,847 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2017 Advance Micro Devices, Inc. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Advance Micro Devices, Inc nor the names\n+ * of its contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written\n+ * permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <dirent.h>\n+#include <fcntl.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <sys/mman.h>\n+#include <sys/queue.h>\n+#include <sys/types.h>\n+#include <unistd.h>\n+\n+#include <rte_hexdump.h>\n+#include <rte_memzone.h>\n+#include <rte_malloc.h>\n+#include <rte_memory.h>\n+#include <rte_spinlock.h>\n+#include <rte_string_fns.h>\n+\n+#include <ccp_dev.h>\n+#include <ccp_pci.h>\n+#include <ccp_pmd_private.h>\n+\n+#include <openssl/sha.h> /*partial hash apis*/\n+#include <openssl/cmac.h> /*sub key apis*/\n+#include <openssl/evp.h> /*sub key apis*/\n+\n+struct ccp_list ccp_list = TAILQ_HEAD_INITIALIZER(ccp_list);\n+static int ccp_dev_id;\n+\n+int\n+ccp_dev_start(struct rte_cryptodev *dev)\n+{\n+\tstruct ccp_private *priv = dev->data->dev_private;\n+\n+\tpriv->last_dev = TAILQ_FIRST(&ccp_list);\n+\treturn 0;\n+}\n+\n+struct ccp_queue *\n+ccp_allot_queue(struct rte_cryptodev *cdev, int slot_req)\n+{\n+\tint i, ret = 0;\n+\tstruct ccp_device *dev;\n+\tstruct ccp_private *priv = cdev->data->dev_private;\n+\n+\tdev = TAILQ_NEXT(priv->last_dev, next);\n+\tif (unlikely(dev == NULL))\n+\t\tdev = TAILQ_FIRST(&ccp_list);\n+\tpriv->last_dev = dev;\n+\tif (dev->qidx >= dev->cmd_q_count)\n+\t\tdev->qidx = 0;\n+\tret = rte_atomic64_read(&dev->cmd_q[dev->qidx].free_slots);\n+\tif (ret >= slot_req)\n+\t\treturn &dev->cmd_q[dev->qidx];\n+\tfor (i = 0; i < dev->cmd_q_count; i++) {\n+\t\tdev->qidx++;\n+\t\tif (dev->qidx >= dev->cmd_q_count)\n+\t\t\tdev->qidx = 0;\n+\t\tret = rte_atomic64_read(&dev->cmd_q[dev->qidx].free_slots);\n+\t\tif (ret >= slot_req)\n+\t\t\treturn &dev->cmd_q[dev->qidx];\n+\t}\n+\treturn NULL;\n+}\n+\n+int\n+ccp_read_hwrng(uint32_t *value)\n+{\n+\tstruct ccp_device *dev;\n+\n+\tTAILQ_FOREACH(dev, &ccp_list, next) {\n+\t\tvoid *vaddr = (void *)(dev->pci.mem_resource[2].addr);\n+\n+\t\twhile (dev->hwrng_retries++ < TRNG_RETRIES) {\n+\t\t\t*value = CCP_READ_REG(vaddr, TRNG_OUT_REG);\n+\t\t\tif (*value) {\n+\t\t\t\tdev->hwrng_retries = 0;\n+\t\t\t\treturn 0;\n+\t\t\t}\n+\t\t}\n+\t\tdev->hwrng_retries = 0;\n+\t}\n+\treturn -1;\n+}\n+\n+static const struct rte_memzone *\n+ccp_queue_dma_zone_reserve(const char *queue_name,\n+\t\t\t uint32_t queue_size,\n+\t\t\t int socket_id)\n+{\n+\tconst struct rte_memzone *mz;\n+\tunsigned int memzone_flags = 0;\n+\tconst struct rte_memseg *ms;\n+\n+\tmz = rte_memzone_lookup(queue_name);\n+\tif (mz != 0)\n+\t\treturn mz;\n+\n+\tms = rte_eal_get_physmem_layout();\n+\tswitch (ms[0].hugepage_sz) {\n+\tcase(RTE_PGSIZE_2M):\n+\t\tmemzone_flags = RTE_MEMZONE_2MB;\n+\t\tbreak;\n+\tcase(RTE_PGSIZE_1G):\n+\t\tmemzone_flags = RTE_MEMZONE_1GB;\n+\t\tbreak;\n+\tcase(RTE_PGSIZE_16M):\n+\t\tmemzone_flags = RTE_MEMZONE_16MB;\n+\t\tbreak;\n+\tcase(RTE_PGSIZE_16G):\n+\t\tmemzone_flags = RTE_MEMZONE_16GB;\n+\t\tbreak;\n+\tdefault:\n+\t\tmemzone_flags = RTE_MEMZONE_SIZE_HINT_ONLY;\n+\t}\n+\n+\treturn rte_memzone_reserve_aligned(queue_name,\n+\t\t\t\t\t queue_size,\n+\t\t\t\t\t socket_id,\n+\t\t\t\t\t memzone_flags,\n+\t\t\t\t\t queue_size);\n+}\n+\n+/*---bitmap support apis---*/\n+static inline void\n+ccp_set_bit(unsigned long *bitmap, int n)\n+{\n+\t__sync_fetch_and_or(&bitmap[WORD_OFFSET(n)], (1UL << BIT_OFFSET(n)));\n+}\n+\n+static inline void\n+ccp_clear_bit(unsigned long *bitmap, int n)\n+{\n+\t__sync_fetch_and_and(&bitmap[WORD_OFFSET(n)], ~(1UL << BIT_OFFSET(n)));\n+}\n+\n+static inline uint32_t\n+ccp_get_bit(unsigned long *bitmap, int n)\n+{\n+\treturn ((bitmap[WORD_OFFSET(n)] & (1 << BIT_OFFSET(n))) != 0);\n+}\n+\n+\n+static inline uint32_t\n+ccp_ffz(unsigned long word)\n+{\n+\tunsigned long first_zero;\n+\n+\tfirst_zero = __builtin_ffsl(~word);\n+\treturn first_zero ? (first_zero - 1) :\n+\t\tBITS_PER_WORD;\n+}\n+\n+static inline uint32_t\n+ccp_find_first_zero_bit(unsigned long *addr, uint32_t limit)\n+{\n+\tuint32_t i;\n+\tuint32_t nwords = 0;\n+\n+\tnwords = (limit - 1) / BITS_PER_WORD + 1;\n+\tfor (i = 0; i < nwords; i++) {\n+\t\tif (addr[i] == 0UL)\n+\t\t\treturn i * BITS_PER_WORD;\n+\t\tif (addr[i] < ~(0UL))\n+\t\t\tbreak;\n+\t}\n+\treturn (i == nwords) ? limit : i * BITS_PER_WORD + ccp_ffz(addr[i]);\n+}\n+\n+static void\n+ccp_bitmap_set(unsigned long *map, unsigned int start, int len)\n+{\n+\tunsigned long *p = map + WORD_OFFSET(start);\n+\tconst unsigned int size = start + len;\n+\tint bits_to_set = BITS_PER_WORD - (start % BITS_PER_WORD);\n+\tunsigned long mask_to_set = CCP_BITMAP_FIRST_WORD_MASK(start);\n+\n+\twhile (len - bits_to_set >= 0) {\n+\t\t*p |= mask_to_set;\n+\t\tlen -= bits_to_set;\n+\t\tbits_to_set = BITS_PER_WORD;\n+\t\tmask_to_set = ~0UL;\n+\t\tp++;\n+\t}\n+\tif (len) {\n+\t\tmask_to_set &= CCP_BITMAP_LAST_WORD_MASK(size);\n+\t\t*p |= mask_to_set;\n+\t}\n+}\n+\n+static void\n+ccp_bitmap_clear(unsigned long *map, unsigned int start, int len)\n+{\n+\tunsigned long *p = map + WORD_OFFSET(start);\n+\tconst unsigned int size = start + len;\n+\tint bits_to_clear = BITS_PER_WORD - (start % BITS_PER_WORD);\n+\tunsigned long mask_to_clear = CCP_BITMAP_FIRST_WORD_MASK(start);\n+\n+\twhile (len - bits_to_clear >= 0) {\n+\t\t*p &= ~mask_to_clear;\n+\t\tlen -= bits_to_clear;\n+\t\tbits_to_clear = BITS_PER_WORD;\n+\t\tmask_to_clear = ~0UL;\n+\t\tp++;\n+\t}\n+\tif (len) {\n+\t\tmask_to_clear &= CCP_BITMAP_LAST_WORD_MASK(size);\n+\t\t*p &= ~mask_to_clear;\n+\t}\n+}\n+\n+\n+static unsigned long\n+_ccp_find_next_bit(const unsigned long *addr,\n+\t\t unsigned long nbits,\n+\t\t unsigned long start,\n+\t\t unsigned long invert)\n+{\n+\tunsigned long tmp;\n+\n+\tif (!nbits || start >= nbits)\n+\t\treturn nbits;\n+\n+\ttmp = addr[start / BITS_PER_WORD] ^ invert;\n+\n+\t/* Handle 1st word. */\n+\ttmp &= CCP_BITMAP_FIRST_WORD_MASK(start);\n+\tstart = ccp_round_down(start, BITS_PER_WORD);\n+\n+\twhile (!tmp) {\n+\t\tstart += BITS_PER_WORD;\n+\t\tif (start >= nbits)\n+\t\t\treturn nbits;\n+\n+\t\ttmp = addr[start / BITS_PER_WORD] ^ invert;\n+\t}\n+\n+\treturn RTE_MIN(start + (ffs(tmp) - 1), nbits);\n+}\n+\n+static unsigned long\n+ccp_find_next_bit(const unsigned long *addr,\n+\t\t unsigned long size,\n+\t\t unsigned long offset)\n+{\n+\treturn _ccp_find_next_bit(addr, size, offset, 0UL);\n+}\n+\n+static unsigned long\n+ccp_find_next_zero_bit(const unsigned long *addr,\n+\t\t unsigned long size,\n+\t\t unsigned long offset)\n+{\n+\treturn _ccp_find_next_bit(addr, size, offset, ~0UL);\n+}\n+\n+/**\n+ * bitmap_find_next_zero_area - find a contiguous aligned zero area\n+ * @map: The address to base the search on\n+ * @size: The bitmap size in bits\n+ * @start: The bitnumber to start searching at\n+ * @nr: The number of zeroed bits we're looking for\n+ */\n+static unsigned long\n+ccp_bitmap_find_next_zero_area(unsigned long *map,\n+\t\t\t unsigned long size,\n+\t\t\t unsigned long start,\n+\t\t\t unsigned int nr)\n+{\n+\tunsigned long index, end, i;\n+\n+again:\n+\tindex = ccp_find_next_zero_bit(map, size, start);\n+\n+\tend = index + nr;\n+\tif (end > size)\n+\t\treturn end;\n+\ti = ccp_find_next_bit(map, end, index);\n+\tif (i < end) {\n+\t\tstart = i + 1;\n+\t\tgoto again;\n+\t}\n+\treturn index;\n+}\n+\n+static uint32_t\n+ccp_lsb_alloc(struct ccp_queue *cmd_q, unsigned int count)\n+{\n+\tstruct ccp_device *ccp;\n+\tint start;\n+\n+\t/* First look at the map for the queue */\n+\tif (cmd_q->lsb >= 0) {\n+\t\tstart = (uint32_t)ccp_bitmap_find_next_zero_area(cmd_q->lsbmap,\n+\t\t\t\t\t\t\t\t LSB_SIZE, 0,\n+\t\t\t\t\t\t\t\t count);\n+\t\tif (start < LSB_SIZE) {\n+\t\t\tccp_bitmap_set(cmd_q->lsbmap, start, count);\n+\t\t\treturn start + cmd_q->lsb * LSB_SIZE;\n+\t\t}\n+\t}\n+\n+\t/* try to get an entry from the shared blocks */\n+\tccp = cmd_q->dev;\n+\n+\trte_spinlock_lock(&ccp->lsb_lock);\n+\n+\tstart = (uint32_t)ccp_bitmap_find_next_zero_area(ccp->lsbmap,\n+\t\t\t\t\t\t MAX_LSB_CNT * LSB_SIZE,\n+\t\t\t\t\t\t 0, count);\n+\tif (start <= MAX_LSB_CNT * LSB_SIZE) {\n+\t\tccp_bitmap_set(ccp->lsbmap, start, count);\n+\t\trte_spinlock_unlock(&ccp->lsb_lock);\n+\t\treturn start * LSB_ITEM_SIZE;\n+\t}\n+\tCCP_LOG_ERR(\"NO LSBs available\");\n+\n+\trte_spinlock_unlock(&ccp->lsb_lock);\n+\n+\treturn 0;\n+}\n+\n+static void __rte_unused\n+ccp_lsb_free(struct ccp_queue *cmd_q,\n+\t unsigned int start,\n+\t unsigned int count)\n+{\n+\tint lsbno = start / LSB_SIZE;\n+\n+\tif (!start)\n+\t\treturn;\n+\n+\tif (cmd_q->lsb == lsbno) {\n+\t\t/* An entry from the private LSB */\n+\t\tccp_bitmap_clear(cmd_q->lsbmap, start % LSB_SIZE, count);\n+\t} else {\n+\t\t/* From the shared LSBs */\n+\t\tstruct ccp_device *ccp = cmd_q->dev;\n+\n+\t\trte_spinlock_lock(&ccp->lsb_lock);\n+\t\tccp_bitmap_clear(ccp->lsbmap, start, count);\n+\t\trte_spinlock_unlock(&ccp->lsb_lock);\n+\t}\n+}\n+\n+static int\n+ccp_find_lsb_regions(struct ccp_queue *cmd_q, uint64_t status)\n+{\n+\tint q_mask = 1 << cmd_q->id;\n+\tint weight = 0;\n+\tint j;\n+\n+\t/* Build a bit mask to know which LSBs\n+\t * this queue has access to.\n+\t * Don't bother with segment 0\n+\t * as it has special\n+\t * privileges.\n+\t */\n+\tcmd_q->lsbmask = 0;\n+\tstatus >>= LSB_REGION_WIDTH;\n+\tfor (j = 1; j < MAX_LSB_CNT; j++) {\n+\t\tif (status & q_mask)\n+\t\t\tccp_set_bit(&cmd_q->lsbmask, j);\n+\n+\t\tstatus >>= LSB_REGION_WIDTH;\n+\t}\n+\n+\tfor (j = 0; j < MAX_LSB_CNT; j++)\n+\t\tif (ccp_get_bit(&cmd_q->lsbmask, j))\n+\t\t\tweight++;\n+\n+\tprintf(\"Queue %d can access %d LSB regions of mask %lu\\n\",\n+\t (int)cmd_q->id, weight, cmd_q->lsbmask);\n+\n+\treturn weight ? 0 : -EINVAL;\n+}\n+\n+static int\n+ccp_find_and_assign_lsb_to_q(struct ccp_device *ccp,\n+\t\t\t int lsb_cnt, int n_lsbs,\n+\t\t\t unsigned long *lsb_pub)\n+{\n+\tunsigned long qlsb = 0;\n+\tint bitno = 0;\n+\tint qlsb_wgt = 0;\n+\tint i, j;\n+\n+\t/* For each queue:\n+\t * If the count of potential LSBs available to a queue matches the\n+\t * ordinal given to us in lsb_cnt:\n+\t * Copy the mask of possible LSBs for this queue into \"qlsb\";\n+\t * For each bit in qlsb, see if the corresponding bit in the\n+\t * aggregation mask is set; if so, we have a match.\n+\t * If we have a match, clear the bit in the aggregation to\n+\t * mark it as no longer available.\n+\t * If there is no match, clear the bit in qlsb and keep looking.\n+\t */\n+\tfor (i = 0; i < ccp->cmd_q_count; i++) {\n+\t\tstruct ccp_queue *cmd_q = &ccp->cmd_q[i];\n+\n+\t\tqlsb_wgt = 0;\n+\t\tfor (j = 0; j < MAX_LSB_CNT; j++)\n+\t\t\tif (ccp_get_bit(&cmd_q->lsbmask, j))\n+\t\t\t\tqlsb_wgt++;\n+\n+\t\tif (qlsb_wgt == lsb_cnt) {\n+\t\t\tqlsb = cmd_q->lsbmask;\n+\n+\t\t\tbitno = ffs(qlsb) - 1;\n+\t\t\twhile (bitno < MAX_LSB_CNT) {\n+\t\t\t\tif (ccp_get_bit(lsb_pub, bitno)) {\n+\t\t\t\t\t/* We found an available LSB\n+\t\t\t\t\t * that this queue can access\n+\t\t\t\t\t */\n+\t\t\t\t\tcmd_q->lsb = bitno;\n+\t\t\t\t\tccp_clear_bit(lsb_pub, bitno);\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tccp_clear_bit(&qlsb, bitno);\n+\t\t\t\tbitno = ffs(qlsb) - 1;\n+\t\t\t}\n+\t\t\tif (bitno >= MAX_LSB_CNT)\n+\t\t\t\treturn -EINVAL;\n+\t\t\tn_lsbs--;\n+\t\t}\n+\t}\n+\treturn n_lsbs;\n+}\n+\n+/* For each queue, from the most- to least-constrained:\n+ * find an LSB that can be assigned to the queue. If there are N queues that\n+ * can only use M LSBs, where N > M, fail; otherwise, every queue will get a\n+ * dedicated LSB. Remaining LSB regions become a shared resource.\n+ * If we have fewer LSBs than queues, all LSB regions become shared\n+ * resources.\n+ */\n+static int\n+ccp_assign_lsbs(struct ccp_device *ccp)\n+{\n+\tunsigned long lsb_pub = 0, qlsb = 0;\n+\tint n_lsbs = 0;\n+\tint bitno;\n+\tint i, lsb_cnt;\n+\tint rc = 0;\n+\n+\trte_spinlock_init(&ccp->lsb_lock);\n+\n+\t/* Create an aggregate bitmap to get a total count of available LSBs */\n+\tfor (i = 0; i < ccp->cmd_q_count; i++)\n+\t\tlsb_pub |= ccp->cmd_q[i].lsbmask;\n+\n+\tfor (i = 0; i < MAX_LSB_CNT; i++)\n+\t\tif (ccp_get_bit(&lsb_pub, i))\n+\t\t\tn_lsbs++;\n+\n+\tif (n_lsbs >= ccp->cmd_q_count) {\n+\t\t/* We have enough LSBS to give every queue a private LSB.\n+\t\t * Brute force search to start with the queues that are more\n+\t\t * constrained in LSB choice. When an LSB is privately\n+\t\t * assigned, it is removed from the public mask.\n+\t\t * This is an ugly N squared algorithm with some optimization.\n+\t\t */\n+\t\tfor (lsb_cnt = 1; n_lsbs && (lsb_cnt <= MAX_LSB_CNT);\n+\t\t lsb_cnt++) {\n+\t\t\trc = ccp_find_and_assign_lsb_to_q(ccp, lsb_cnt, n_lsbs,\n+\t\t\t\t\t\t\t &lsb_pub);\n+\t\t\tif (rc < 0)\n+\t\t\t\treturn -EINVAL;\n+\t\t\tn_lsbs = rc;\n+\t\t}\n+\t}\n+\n+\trc = 0;\n+\t/* What's left of the LSBs, according to the public mask, now become\n+\t * shared. Any zero bits in the lsb_pub mask represent an LSB region\n+\t * that can't be used as a shared resource, so mark the LSB slots for\n+\t * them as \"in use\".\n+\t */\n+\tqlsb = lsb_pub;\n+\tbitno = ccp_find_first_zero_bit(&qlsb, MAX_LSB_CNT);\n+\twhile (bitno < MAX_LSB_CNT) {\n+\t\tccp_bitmap_set(ccp->lsbmap, bitno * LSB_SIZE, LSB_SIZE);\n+\t\tccp_set_bit(&qlsb, bitno);\n+\t\tbitno = ccp_find_first_zero_bit(&qlsb, MAX_LSB_CNT);\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static int\n+ccp_add_device(struct ccp_device *dev, int type)\n+{\n+\tint i;\n+\tuint32_t qmr, status_lo, status_hi, dma_addr_lo, dma_addr_hi;\n+\tuint64_t status;\n+\tstruct ccp_queue *cmd_q;\n+\tconst struct rte_memzone *q_mz;\n+\tvoid *vaddr;\n+\n+\tif (dev == NULL)\n+\t\treturn -1;\n+\n+\tdev->id = ccp_dev_id++;\n+\tdev->qidx = 0;\n+\tvaddr = (void *)(dev->pci.mem_resource[2].addr);\n+\n+\tif (type == CCP_VERSION_5B) {\n+\t\tCCP_WRITE_REG(vaddr, CMD_TRNG_CTL_OFFSET, 0x00012D57);\n+\t\tCCP_WRITE_REG(vaddr, CMD_CONFIG_0_OFFSET, 0x00000003);\n+\t\tfor (i = 0; i < 12; i++) {\n+\t\t\tCCP_WRITE_REG(vaddr, CMD_AES_MASK_OFFSET,\n+\t\t\t\t CCP_READ_REG(vaddr, TRNG_OUT_REG));\n+\t\t}\n+\t\tCCP_WRITE_REG(vaddr, CMD_QUEUE_MASK_OFFSET, 0x0000001F);\n+\t\tCCP_WRITE_REG(vaddr, CMD_QUEUE_PRIO_OFFSET, 0x00005B6D);\n+\t\tCCP_WRITE_REG(vaddr, CMD_CMD_TIMEOUT_OFFSET, 0x00000000);\n+\n+\t\tCCP_WRITE_REG(vaddr, LSB_PRIVATE_MASK_LO_OFFSET, 0x3FFFFFFF);\n+\t\tCCP_WRITE_REG(vaddr, LSB_PRIVATE_MASK_HI_OFFSET, 0x000003FF);\n+\n+\t\tCCP_WRITE_REG(vaddr, CMD_CLK_GATE_CTL_OFFSET, 0x00108823);\n+\t}\n+\tCCP_WRITE_REG(vaddr, CMD_REQID_CONFIG_OFFSET, 0x00001249);\n+\n+\t/* Copy the private LSB mask to the public registers */\n+\tstatus_lo = CCP_READ_REG(vaddr, LSB_PRIVATE_MASK_LO_OFFSET);\n+\tstatus_hi = CCP_READ_REG(vaddr, LSB_PRIVATE_MASK_HI_OFFSET);\n+\tCCP_WRITE_REG(vaddr, LSB_PUBLIC_MASK_LO_OFFSET, status_lo);\n+\tCCP_WRITE_REG(vaddr, LSB_PUBLIC_MASK_HI_OFFSET, status_hi);\n+\tstatus = ((uint64_t)status_hi<<30) | ((uint64_t)status_lo);\n+\n+\tdev->cmd_q_count = 0;\n+\t/* Find available queues */\n+\tqmr = CCP_READ_REG(vaddr, Q_MASK_REG);\n+\tfor (i = 0; i < MAX_HW_QUEUES; i++) {\n+\t\tif (!(qmr & (1 << i)))\n+\t\t\tcontinue;\n+\t\tcmd_q = &dev->cmd_q[dev->cmd_q_count++];\n+\t\tcmd_q->dev = dev;\n+\t\tcmd_q->id = i;\n+\t\tcmd_q->qidx = 0;\n+\t\tcmd_q->qsize = Q_SIZE(Q_DESC_SIZE);\n+\n+\t\tcmd_q->reg_base = (uint8_t *)vaddr +\n+\t\t\tCMD_Q_STATUS_INCR * (i + 1);\n+\n+\t\t/* CCP queue memory */\n+\t\tsnprintf(cmd_q->memz_name, sizeof(cmd_q->memz_name),\n+\t\t\t \"%s_%d_%s_%d_%s\",\n+\t\t\t \"ccp_dev\",\n+\t\t\t (int)dev->id, \"queue\",\n+\t\t\t (int)cmd_q->id, \"mem\");\n+\t\tq_mz = ccp_queue_dma_zone_reserve(cmd_q->memz_name,\n+\t\t\t\t\t\t cmd_q->qsize, SOCKET_ID_ANY);\n+\t\tcmd_q->qbase_addr = (void *)q_mz->addr;\n+\t\tcmd_q->qbase_desc = (void *)q_mz->addr;\n+\t\tcmd_q->qbase_phys_addr = q_mz->phys_addr;\n+\n+\t\tcmd_q->qcontrol = 0;\n+\t\t/* init control reg to zero */\n+\t\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t\t cmd_q->qcontrol);\n+\n+\t\t/* Disable the interrupts */\n+\t\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_INT_ENABLE_BASE, 0x00);\n+\t\tCCP_READ_REG(cmd_q->reg_base, CMD_Q_INT_STATUS_BASE);\n+\t\tCCP_READ_REG(cmd_q->reg_base, CMD_Q_STATUS_BASE);\n+\n+\t\t/* Clear the interrupts */\n+\t\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_INTERRUPT_STATUS_BASE,\n+\t\t\t ALL_INTERRUPTS);\n+\n+\t\t/* Configure size of each virtual queue accessible to host */\n+\t\tcmd_q->qcontrol &= ~(CMD_Q_SIZE << CMD_Q_SHIFT);\n+\t\tcmd_q->qcontrol |= QUEUE_SIZE_VAL << CMD_Q_SHIFT;\n+\n+\t\tdma_addr_lo = low32_value(cmd_q->qbase_phys_addr);\n+\t\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE,\n+\t\t\t (uint32_t)dma_addr_lo);\n+\t\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_HEAD_LO_BASE,\n+\t\t\t (uint32_t)dma_addr_lo);\n+\n+\t\tdma_addr_hi = high32_value(cmd_q->qbase_phys_addr);\n+\t\tcmd_q->qcontrol |= (dma_addr_hi << 16);\n+\t\tCCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,\n+\t\t\t cmd_q->qcontrol);\n+\n+\t\t/* create LSB Mask map */\n+\t\tif (ccp_find_lsb_regions(cmd_q, status))\n+\t\t\tCCP_LOG_ERR(\"queue doesn't have lsb regions\");\n+\t\tcmd_q->lsb = -1;\n+\n+\t\trte_atomic64_init(&cmd_q->free_slots);\n+\t\trte_atomic64_set(&cmd_q->free_slots, (COMMANDS_PER_QUEUE - 1));\n+\t\t/* unused slot barrier b/w H&T */\n+\t}\n+\n+\tif (ccp_assign_lsbs(dev))\n+\t\tCCP_LOG_ERR(\"Unable to assign lsb region\");\n+\n+\t/* pre-allocate LSB slots */\n+\tfor (i = 0; i < dev->cmd_q_count; i++) {\n+\t\tdev->cmd_q[i].sb_key =\n+\t\t\tccp_lsb_alloc(&dev->cmd_q[i], 1);\n+\t\tdev->cmd_q[i].sb_iv =\n+\t\t\tccp_lsb_alloc(&dev->cmd_q[i], 1);\n+\t\tdev->cmd_q[i].sb_sha =\n+\t\t\tccp_lsb_alloc(&dev->cmd_q[i], 2);\n+\t\tdev->cmd_q[i].sb_hmac =\n+\t\t\tccp_lsb_alloc(&dev->cmd_q[i], 2);\n+\t}\n+\n+\tTAILQ_INSERT_TAIL(&ccp_list, dev, next);\n+\treturn 0;\n+}\n+\n+static void\n+ccp_remove_device(struct ccp_device *dev)\n+{\n+\tif (dev == NULL)\n+\t\treturn;\n+\n+\tTAILQ_REMOVE(&ccp_list, dev, next);\n+}\n+\n+static int\n+is_ccp_device(const char *dirname,\n+\t const struct rte_pci_id *ccp_id,\n+\t int *type)\n+{\n+\tchar filename[PATH_MAX];\n+\tconst struct rte_pci_id *id;\n+\tuint16_t vendor, device_id;\n+\tint i;\n+\tunsigned long tmp;\n+\n+\t/* get vendor id */\n+\tsnprintf(filename, sizeof(filename), \"%s/vendor\", dirname);\n+\tif (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)\n+\t\treturn 0;\n+\tvendor = (uint16_t)tmp;\n+\n+\t/* get device id */\n+\tsnprintf(filename, sizeof(filename), \"%s/device\", dirname);\n+\tif (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)\n+\t\treturn 0;\n+\tdevice_id = (uint16_t)tmp;\n+\n+\tfor (id = ccp_id, i = 0; id->vendor_id != 0; id++, i++) {\n+\t\tif (vendor == id->vendor_id &&\n+\t\t device_id == id->device_id) {\n+\t\t\t*type = i;\n+\t\t\treturn 1; /* Matched device */\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+ccp_probe_device(const char *dirname, uint16_t domain,\n+\t\t uint8_t bus, uint8_t devid,\n+\t\t uint8_t function, int ccp_type)\n+{\n+\tstruct ccp_device *ccp_dev = NULL;\n+\tstruct rte_pci_device *pci;\n+\tchar filename[PATH_MAX];\n+\tunsigned long tmp;\n+\tint uio_fd = -1, i, uio_num;\n+\tchar uio_devname[PATH_MAX];\n+\tvoid *map_addr;\n+\n+\tccp_dev = rte_zmalloc(\"ccp_device\", sizeof(*ccp_dev),\n+\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (ccp_dev == NULL)\n+\t\tgoto fail;\n+\tpci = &(ccp_dev->pci);\n+\n+\tpci->addr.domain = domain;\n+\tpci->addr.bus = bus;\n+\tpci->addr.devid = devid;\n+\tpci->addr.function = function;\n+\n+\t/* get vendor id */\n+\tsnprintf(filename, sizeof(filename), \"%s/vendor\", dirname);\n+\tif (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)\n+\t\tgoto fail;\n+\tpci->id.vendor_id = (uint16_t)tmp;\n+\n+\t/* get device id */\n+\tsnprintf(filename, sizeof(filename), \"%s/device\", dirname);\n+\tif (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)\n+\t\tgoto fail;\n+\tpci->id.device_id = (uint16_t)tmp;\n+\n+\t/* get subsystem_vendor id */\n+\tsnprintf(filename, sizeof(filename), \"%s/subsystem_vendor\",\n+\t\t\tdirname);\n+\tif (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)\n+\t\tgoto fail;\n+\tpci->id.subsystem_vendor_id = (uint16_t)tmp;\n+\n+\t/* get subsystem_device id */\n+\tsnprintf(filename, sizeof(filename), \"%s/subsystem_device\",\n+\t\t\tdirname);\n+\tif (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)\n+\t\tgoto fail;\n+\tpci->id.subsystem_device_id = (uint16_t)tmp;\n+\n+\t/* get class_id */\n+\tsnprintf(filename, sizeof(filename), \"%s/class\",\n+\t\t\tdirname);\n+\tif (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)\n+\t\tgoto fail;\n+\t/* the least 24 bits are valid: class, subclass, program interface */\n+\tpci->id.class_id = (uint32_t)tmp & RTE_CLASS_ANY_ID;\n+\n+\t/* parse resources */\n+\tsnprintf(filename, sizeof(filename), \"%s/resource\", dirname);\n+\tif (ccp_pci_parse_sysfs_resource(filename, pci) < 0)\n+\t\tgoto fail;\n+\n+\tuio_num = ccp_find_uio_devname(dirname);\n+\tif (uio_num < 0) {\n+\t\t/*\n+\t\t * It may take time for uio device to appear,\n+\t\t * wait here and try again\n+\t\t */\n+\t\tusleep(100000);\n+\t\tuio_num = ccp_find_uio_devname(dirname);\n+\t\tif (uio_num < 0)\n+\t\t\tgoto fail;\n+\t}\n+\tsnprintf(uio_devname, sizeof(uio_devname), \"/dev/uio%u\", uio_num);\n+\n+\tuio_fd = open(uio_devname, O_RDWR);\n+\tif (uio_fd < 0)\n+\t\tgoto fail;\n+\n+\t/* Map the PCI memory resource of device */\n+\tfor (i = 0; i < PCI_MAX_RESOURCE; i++) {\n+\n+\t\tchar devname[PATH_MAX];\n+\t\tint res_fd;\n+\n+\t\tif (pci->mem_resource[i].phys_addr == 0)\n+\t\t\tcontinue;\n+\t\tsnprintf(devname, sizeof(devname), \"%s/resource%d\", dirname, i);\n+\t\tres_fd = open(devname, O_RDWR);\n+\t\tif (res_fd < 0)\n+\t\t\tgoto fail;\n+\t\tmap_addr = mmap(NULL, pci->mem_resource[i].len,\n+\t\t\t\tPROT_READ | PROT_WRITE,\n+\t\t\t\tMAP_SHARED, res_fd, 0);\n+\t\tif (map_addr == MAP_FAILED)\n+\t\t\tgoto fail;\n+\n+\t\tpci->mem_resource[i].addr = map_addr;\n+\t}\n+\n+\t/* device is valid, add in list */\n+\tif (ccp_add_device(ccp_dev, ccp_type)) {\n+\t\tccp_remove_device(ccp_dev);\n+\t\tgoto fail;\n+\t}\n+\n+\treturn 0;\n+fail:\n+\tCCP_LOG_ERR(\"CCP Device probe failed\");\n+\tif (uio_fd > 0)\n+\t\tclose(uio_fd);\n+\tif (ccp_dev)\n+\t\trte_free(ccp_dev);\n+\treturn -1;\n+}\n+\n+int\n+ccp_probe_devices(const struct rte_pci_id *ccp_id)\n+{\n+\tint dev_cnt = 0;\n+\tint ccp_type = 0;\n+\tstruct dirent *d;\n+\tDIR *dir;\n+\tint ret = 0;\n+\tint module_idx = 0;\n+\tuint16_t domain;\n+\tuint8_t bus, devid, function;\n+\tchar dirname[PATH_MAX];\n+\n+\tmodule_idx = ccp_check_pci_uio_module();\n+\tif (module_idx < 0)\n+\t\treturn -1;\n+\n+\tTAILQ_INIT(&ccp_list);\n+\tdir = opendir(SYSFS_PCI_DEVICES);\n+\tif (dir == NULL)\n+\t\treturn -1;\n+\twhile ((d = readdir(dir)) != NULL) {\n+\t\tif (d->d_name[0] == '.')\n+\t\t\tcontinue;\n+\t\tif (ccp_parse_pci_addr_format(d->d_name, sizeof(d->d_name),\n+\t\t\t\t\t&domain, &bus, &devid, &function) != 0)\n+\t\t\tcontinue;\n+\t\tsnprintf(dirname, sizeof(dirname), \"%s/%s\",\n+\t\t\t SYSFS_PCI_DEVICES, d->d_name);\n+\t\tif (is_ccp_device(dirname, ccp_id, &ccp_type)) {\n+\t\t\tprintf(\"CCP : Detected CCP device with ID = 0x%x\\n\",\n+\t\t\t ccp_id[ccp_type].device_id);\n+\t\t\tret = ccp_probe_device(dirname, domain, bus, devid,\n+\t\t\t\t\t function, ccp_type);\n+\t\t\tif (ret == 0)\n+\t\t\t\tdev_cnt++;\n+\t\t}\n+\t}\n+\tclosedir(dir);\n+\treturn dev_cnt;\n+}\ndiff --git a/drivers/crypto/ccp/ccp_dev.h b/drivers/crypto/ccp/ccp_dev.h\nnew file mode 100644\nindex 0000000..536ab94\n--- /dev/null\n+++ b/drivers/crypto/ccp/ccp_dev.h\n@@ -0,0 +1,533 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2017 Advance Micro Devices, Inc. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Advance Micro Devices, Inc nor the names\n+ * of its contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written\n+ * permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _CCP_DEV_H_\n+#define _CCP_DEV_H_\n+\n+#include <limits.h>\n+#include <stdbool.h>\n+#include <stdint.h>\n+#include <string.h>\n+\n+#include <rte_atomic.h>\n+#include <rte_byteorder.h>\n+#include <rte_io.h>\n+#include <rte_pci.h>\n+#include <rte_spinlock.h>\n+#include <rte_crypto_sym.h>\n+#include <rte_cryptodev.h>\n+\n+/**CCP sspecific*/\n+#define MAX_HW_QUEUES 5\n+#define TRNG_RETRIES 10\n+#define CCP_ALIGN(x, y) ((((x) + (y - 1)) / y) * y)\n+\n+/****** Register Mappings ******/\n+#define Q_MASK_REG 0x000\n+#define TRNG_OUT_REG 0x00c\n+\n+/* ----------- CCP Version 5 Specifics ------------ */\n+#define CMD_QUEUE_MASK_OFFSET\t\t0x00\n+#define\tCMD_QUEUE_PRIO_OFFSET\t\t0x04\n+#define CMD_REQID_CONFIG_OFFSET\t\t0x08\n+#define\tCMD_CMD_TIMEOUT_OFFSET\t\t0x10\n+#define LSB_PUBLIC_MASK_LO_OFFSET\t0x18\n+#define LSB_PUBLIC_MASK_HI_OFFSET\t0x1C\n+#define LSB_PRIVATE_MASK_LO_OFFSET\t0x20\n+#define LSB_PRIVATE_MASK_HI_OFFSET\t0x24\n+\n+#define CMD_Q_CONTROL_BASE\t\t0x0000\n+#define CMD_Q_TAIL_LO_BASE\t\t0x0004\n+#define CMD_Q_HEAD_LO_BASE\t\t0x0008\n+#define CMD_Q_INT_ENABLE_BASE\t\t0x000C\n+#define CMD_Q_INTERRUPT_STATUS_BASE\t0x0010\n+\n+#define CMD_Q_STATUS_BASE\t\t0x0100\n+#define CMD_Q_INT_STATUS_BASE\t\t0x0104\n+\n+#define\tCMD_CONFIG_0_OFFSET\t\t0x6000\n+#define\tCMD_TRNG_CTL_OFFSET\t\t0x6008\n+#define\tCMD_AES_MASK_OFFSET\t\t0x6010\n+#define\tCMD_CLK_GATE_CTL_OFFSET\t\t0x603C\n+\n+/* Address offset between two virtual queue registers */\n+#define CMD_Q_STATUS_INCR 0x1000\n+\n+/* Bit masks */\n+#define CMD_Q_RUN 0x1\n+\n+#define CMD_Q_SIZE 0x1F\n+#define CMD_Q_SHIFT 3\n+#define COMMANDS_PER_QUEUE 2048\n+\n+#define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \\\n+\t\t\t\t\t CMD_Q_SIZE)\n+#define Q_DESC_SIZE sizeof(struct ccp_desc)\n+#define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n))\n+\n+#define INT_COMPLETION 0x1\n+#define INT_ERROR 0x2\n+#define INT_QUEUE_STOPPED 0x4\n+#define ALL_INTERRUPTS (INT_COMPLETION| \\\n+\t\t\t\t\t INT_ERROR| \\\n+\t\t\t\t\t INT_QUEUE_STOPPED)\n+\n+#define LSB_REGION_WIDTH 5\n+#define MAX_LSB_CNT 8\n+\n+#define LSB_SIZE 16\n+#define LSB_ITEM_SIZE 32\n+#define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE)\n+#define LSB_ENTRY_NUMBER(LSB_ADDR) (LSB_ADDR / LSB_ITEM_SIZE)\n+\n+/* ------------------------ General CCP Defines ------------------------ */\n+\n+#define CCP_SB_BYTES 32\n+/* Word 0 */\n+#define CCP_CMD_DW0(p)\t\t((p)->dw0)\n+#define CCP_CMD_SOC(p)\t\t(CCP_CMD_DW0(p).soc)\n+#define CCP_CMD_IOC(p)\t\t(CCP_CMD_DW0(p).ioc)\n+#define CCP_CMD_INIT(p)\t (CCP_CMD_DW0(p).init)\n+#define CCP_CMD_EOM(p)\t\t(CCP_CMD_DW0(p).eom)\n+#define CCP_CMD_FUNCTION(p)\t(CCP_CMD_DW0(p).function)\n+#define CCP_CMD_ENGINE(p)\t(CCP_CMD_DW0(p).engine)\n+#define CCP_CMD_PROT(p)\t (CCP_CMD_DW0(p).prot)\n+\n+/* Word 1 */\n+#define CCP_CMD_DW1(p)\t\t((p)->length)\n+#define CCP_CMD_LEN(p)\t\t(CCP_CMD_DW1(p))\n+\n+/* Word 2 */\n+#define CCP_CMD_DW2(p)\t\t((p)->src_lo)\n+#define CCP_CMD_SRC_LO(p)\t(CCP_CMD_DW2(p))\n+\n+/* Word 3 */\n+#define CCP_CMD_DW3(p)\t\t((p)->dw3)\n+#define CCP_CMD_SRC_MEM(p)\t((p)->dw3.src_mem)\n+#define CCP_CMD_SRC_HI(p)\t((p)->dw3.src_hi)\n+#define CCP_CMD_LSB_ID(p)\t((p)->dw3.lsb_cxt_id)\n+#define CCP_CMD_FIX_SRC(p)\t((p)->dw3.fixed)\n+\n+/* Words 4/5 */\n+#define CCP_CMD_DW4(p)\t\t((p)->dw4)\n+#define CCP_CMD_DST_LO(p)\t(CCP_CMD_DW4(p).dst_lo)\n+#define CCP_CMD_DW5(p)\t\t((p)->dw5.fields.dst_hi)\n+#define CCP_CMD_DST_HI(p)\t(CCP_CMD_DW5(p))\n+#define CCP_CMD_DST_MEM(p)\t((p)->dw5.fields.dst_mem)\n+#define CCP_CMD_FIX_DST(p)\t((p)->dw5.fields.fixed)\n+#define CCP_CMD_SHA_LO(p)\t((p)->dw4.sha_len_lo)\n+#define CCP_CMD_SHA_HI(p)\t((p)->dw5.sha_len_hi)\n+\n+/* Word 6/7 */\n+#define CCP_CMD_DW6(p)\t\t((p)->key_lo)\n+#define CCP_CMD_KEY_LO(p)\t(CCP_CMD_DW6(p))\n+#define CCP_CMD_DW7(p)\t\t((p)->dw7)\n+#define CCP_CMD_KEY_HI(p)\t((p)->dw7.key_hi)\n+#define CCP_CMD_KEY_MEM(p)\t((p)->dw7.key_mem)\n+/* bitmap */\n+enum {\n+\tBITS_PER_WORD = sizeof(unsigned long) * CHAR_BIT\n+};\n+\n+#define WORD_OFFSET(b) ((b) / BITS_PER_WORD)\n+#define BIT_OFFSET(b) ((b) % BITS_PER_WORD)\n+\n+#define CCP_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n+#define CCP_BITMAP_SIZE(nr) \\\n+\tCCP_DIV_ROUND_UP(nr, CHAR_BIT * sizeof(unsigned long))\n+\n+#define CCP_BITMAP_FIRST_WORD_MASK(start) \\\n+\t(~0UL << ((start) & (BITS_PER_WORD - 1)))\n+#define CCP_BITMAP_LAST_WORD_MASK(nbits) \\\n+\t(~0UL >> (-(nbits) & (BITS_PER_WORD - 1)))\n+\n+#define __ccp_round_mask(x, y) ((typeof(x))((y)-1))\n+#define ccp_round_down(x, y) ((x) & ~__ccp_round_mask(x, y))\n+\n+/** CCP registers Write/Read */\n+\n+static inline void ccp_pci_reg_write(void *base, int offset,\n+\t\t\t\t uint32_t value)\n+{\n+\tvolatile void *reg_addr = ((uint8_t *)base + offset);\n+\n+\trte_write32((rte_cpu_to_le_32(value)), reg_addr);\n+}\n+\n+static inline uint32_t ccp_pci_reg_read(void *base, int offset)\n+{\n+\tvolatile void *reg_addr = ((uint8_t *)base + offset);\n+\n+\treturn rte_le_to_cpu_32(rte_read32(reg_addr));\n+}\n+\n+#define CCP_READ_REG(hw_addr, reg_offset) \\\n+\tccp_pci_reg_read(hw_addr, reg_offset)\n+\n+#define CCP_WRITE_REG(hw_addr, reg_offset, value) \\\n+\tccp_pci_reg_write(hw_addr, reg_offset, value)\n+\n+TAILQ_HEAD(ccp_list, ccp_device);\n+\n+extern struct ccp_list ccp_list;\n+\n+/**\n+ * CCP device version\n+ */\n+enum ccp_device_version {\n+\tCCP_VERSION_5A = 0,\n+\tCCP_VERSION_5B,\n+};\n+\n+/**\n+ * A structure describing statictics.\n+ */\n+\n+struct stats {\n+\tuint64_t enq_cnt;\n+\tuint64_t deq_cnt;\n+\tuint64_t err_cnt;\n+};\n+\n+/**\n+ * A structure describing a CCP command queue.\n+ */\n+struct ccp_queue {\n+\tstruct ccp_device *dev;\n+\tchar memz_name[RTE_MEMZONE_NAMESIZE];\n+\tstruct stats stat;\n+\n+\trte_atomic64_t free_slots;\n+\t/**<available free slots updated from enq/deq calls */\n+\n+\t/* Queue identifier */\n+\tuint64_t id;\t/**< queue id */\n+\tuint64_t qidx;\t/**< queue index */\n+\tuint64_t qsize;\t/**< queue size */\n+\n+\t/* Queue address */\n+\tstruct ccp_desc *qbase_desc;\n+\tvoid *qbase_addr;\n+\tphys_addr_t qbase_phys_addr;\n+\t/**< queue-page registers addr */\n+\tvoid *reg_base;\n+\n+\tuint32_t qcontrol;\n+\t/**< queue ctrl reg*/\n+\n+\tint lsb;\n+\t/**<lsb region assigned to queue*/\n+\tunsigned long lsbmask;\n+\t/**<lsb regions queue can access*/\n+\tunsigned long lsbmap[CCP_BITMAP_SIZE(LSB_SIZE)];\n+\t/**<All lsb resources which queue is using*/\n+\tuint32_t sb_key;\n+\t/**<lsb assigned for queue*/\n+\tuint32_t sb_iv;\n+\t/**<lsb assigned for iv*/\n+\tuint32_t sb_sha;\n+\t/**<lsb assigned for sha ctx*/\n+\tuint32_t sb_hmac;\n+\t/**<lsb assigned for hmac ctx*/\n+} ____cacheline_aligned;\n+\n+/**\n+ * A structure describing a CCP device.\n+ */\n+struct ccp_device {\n+\tTAILQ_ENTRY(ccp_device) next;\n+\tint id;\n+\t/**<CCP dev id on platform*/\n+\tstruct ccp_queue cmd_q[MAX_HW_QUEUES];\n+\t/**<CCP queue*/\n+\tint cmd_q_count;\n+\t/**<# of ccp Queues*/\n+\tstruct rte_pci_device pci;\n+\tstruct stats stat;\n+\tunsigned long lsbmap[CCP_BITMAP_SIZE(SLSB_MAP_SIZE)];\n+\t/**<shared lsb mask of ccp*/\n+\trte_spinlock_t lsb_lock;\n+\t/**<protection for shared lsb region allocation*/\n+\tint qidx;\n+\t/**<current queue index */\n+\tint hwrng_retries;\n+\t/**<retry counter for CCP TRNG */\n+} __rte_cache_aligned;\n+\n+\n+/**CCP H/W engine related*/\n+/**\n+ * ccp_engine - CCP operation identifiers\n+ *\n+ * @CCP_ENGINE_AES: AES operation\n+ * @CCP_ENGINE_XTS_AES: 128-bit XTS AES operation\n+ * @CCP_ENGINE_3DES: DES/3DES operation\n+ * @CCP_ENGINE_SHA: SHA operation\n+ * @CCP_ENGINE_RSA: RSA operation\n+ * @CCP_ENGINE_PASSTHRU: pass-through operation\n+ * @CCP_ENGINE_ZLIB_DECOMPRESS: unused\n+ * @CCP_ENGINE_ECC: ECC operation\n+ */\n+enum ccp_engine {\n+\tCCP_ENGINE_AES = 0,\n+\tCCP_ENGINE_XTS_AES_128,\n+\tCCP_ENGINE_3DES,\n+\tCCP_ENGINE_SHA,\n+\tCCP_ENGINE_RSA,\n+\tCCP_ENGINE_PASSTHRU,\n+\tCCP_ENGINE_ZLIB_DECOMPRESS,\n+\tCCP_ENGINE_ECC,\n+\tCCP_ENGINE__LAST,\n+};\n+\n+\n+/***** Passthru engine *****/\n+/**\n+ * ccp_passthru_bitwise - type of bitwise passthru operation\n+ *\n+ * @CCP_PASSTHRU_BITWISE_NOOP: no bitwise operation performed\n+ * @CCP_PASSTHRU_BITWISE_AND: perform bitwise AND of src with mask\n+ * @CCP_PASSTHRU_BITWISE_OR: perform bitwise OR of src with mask\n+ * @CCP_PASSTHRU_BITWISE_XOR: perform bitwise XOR of src with mask\n+ * @CCP_PASSTHRU_BITWISE_MASK: overwrite with mask\n+ */\n+enum ccp_passthru_bitwise {\n+\tCCP_PASSTHRU_BITWISE_NOOP = 0,\n+\tCCP_PASSTHRU_BITWISE_AND,\n+\tCCP_PASSTHRU_BITWISE_OR,\n+\tCCP_PASSTHRU_BITWISE_XOR,\n+\tCCP_PASSTHRU_BITWISE_MASK,\n+\tCCP_PASSTHRU_BITWISE__LAST,\n+};\n+\n+/**\n+ * ccp_passthru_byteswap - type of byteswap passthru operation\n+ *\n+ * @CCP_PASSTHRU_BYTESWAP_NOOP: no byte swapping performed\n+ * @CCP_PASSTHRU_BYTESWAP_32BIT: swap bytes within 32-bit words\n+ * @CCP_PASSTHRU_BYTESWAP_256BIT: swap bytes within 256-bit words\n+ */\n+enum ccp_passthru_byteswap {\n+\tCCP_PASSTHRU_BYTESWAP_NOOP = 0,\n+\tCCP_PASSTHRU_BYTESWAP_32BIT,\n+\tCCP_PASSTHRU_BYTESWAP_256BIT,\n+\tCCP_PASSTHRU_BYTESWAP__LAST,\n+};\n+\n+/**\n+ * CCP passthru\n+ */\n+struct ccp_passthru {\n+\tphys_addr_t src_addr;\n+\tphys_addr_t dest_addr;\n+\tenum ccp_passthru_bitwise bit_mod;\n+\tenum ccp_passthru_byteswap byte_swap;\n+\tint len;\n+\tint dir;\n+};\n+\n+/* CCP version 5: Union to define the function field (cmd_reg1/dword0) */\n+union ccp_function {\n+\tstruct {\n+\t\tuint16_t size:7;\n+\t\tuint16_t encrypt:1;\n+\t\tuint16_t mode:5;\n+\t\tuint16_t type:2;\n+\t} aes;\n+\tstruct {\n+\t\tuint16_t size:7;\n+\t\tuint16_t encrypt:1;\n+\t\tuint16_t mode:5;\n+\t\tuint16_t type:2;\n+\t} des;\n+\tstruct {\n+\t\tuint16_t size:7;\n+\t\tuint16_t encrypt:1;\n+\t\tuint16_t rsvd:5;\n+\t\tuint16_t type:2;\n+\t} aes_xts;\n+\tstruct {\n+\t\tuint16_t rsvd1:10;\n+\t\tuint16_t type:4;\n+\t\tuint16_t rsvd2:1;\n+\t} sha;\n+\tstruct {\n+\t\tuint16_t mode:3;\n+\t\tuint16_t size:12;\n+\t} rsa;\n+\tstruct {\n+\t\tuint16_t byteswap:2;\n+\t\tuint16_t bitwise:3;\n+\t\tuint16_t reflect:2;\n+\t\tuint16_t rsvd:8;\n+\t} pt;\n+\tstruct {\n+\t\tuint16_t rsvd:13;\n+\t} zlib;\n+\tstruct {\n+\t\tuint16_t size:10;\n+\t\tuint16_t type:2;\n+\t\tuint16_t mode:3;\n+\t} ecc;\n+\tuint16_t raw;\n+};\n+\n+\n+/**\n+ * descriptor for version 5 CPP commands\n+ * 8 32-bit words:\n+ * word 0: function; engine; control bits\n+ * word 1: length of source data\n+ * word 2: low 32 bits of source pointer\n+ * word 3: upper 16 bits of source pointer; source memory type\n+ * word 4: low 32 bits of destination pointer\n+ * word 5: upper 16 bits of destination pointer; destination memory\n+ * type\n+ * word 6: low 32 bits of key pointer\n+ * word 7: upper 16 bits of key pointer; key memory type\n+ */\n+struct dword0 {\n+\tuint32_t soc:1;\n+\tuint32_t ioc:1;\n+\tuint32_t rsvd1:1;\n+\tuint32_t init:1;\n+\tuint32_t eom:1;\n+\tuint32_t function:15;\n+\tuint32_t engine:4;\n+\tuint32_t prot:1;\n+\tuint32_t rsvd2:7;\n+};\n+\n+struct dword3 {\n+\tuint32_t src_hi:16;\n+\tuint32_t src_mem:2;\n+\tuint32_t lsb_cxt_id:8;\n+\tuint32_t rsvd1:5;\n+\tuint32_t fixed:1;\n+};\n+\n+union dword4 {\n+\tuint32_t dst_lo;\t/* NON-SHA */\n+\tuint32_t sha_len_lo;\t/* SHA */\n+};\n+\n+union dword5 {\n+\tstruct {\n+\t\tuint32_t dst_hi:16;\n+\t\tuint32_t dst_mem:2;\n+\t\tuint32_t rsvd1:13;\n+\t\tuint32_t fixed:1;\n+\t}\n+\tfields;\n+\tuint32_t sha_len_hi;\n+};\n+\n+struct dword7 {\n+\tuint32_t key_hi:16;\n+\tuint32_t key_mem:2;\n+\tuint32_t rsvd1:14;\n+};\n+\n+struct ccp_desc {\n+\tstruct dword0 dw0;\n+\tuint32_t length;\n+\tuint32_t src_lo;\n+\tstruct dword3 dw3;\n+\tunion dword4 dw4;\n+\tunion dword5 dw5;\n+\tuint32_t key_lo;\n+\tstruct dword7 dw7;\n+};\n+\n+enum ccp_memtype {\n+\tCCP_MEMTYPE_SYSTEM = 0,\n+\tCCP_MEMTYPE_SB,\n+\tCCP_MEMTYPE_LOCAL,\n+\tCCP_MEMTYPE__LAST,\n+};\n+\n+/**\n+ * cmd id to follow order\n+ */\n+enum ccp_cmd_order {\n+\tCCP_CMD_CIPHER = 0,\n+\tCCP_CMD_AUTH,\n+\tCCP_CMD_CIPHER_HASH,\n+\tCCP_CMD_HASH_CIPHER,\n+\tCCP_CMD_COMBINED,\n+\tCCP_CMD_NOT_SUPPORTED,\n+};\n+\n+static inline uint32_t\n+low32_value(unsigned long addr)\n+{\n+\treturn ((uint64_t)addr) & 0x0ffffffff;\n+}\n+\n+static inline uint32_t\n+high32_value(unsigned long addr)\n+{\n+\treturn ((uint64_t)addr >> 32) & 0x00000ffff;\n+}\n+\n+/*\n+ * Start CCP device\n+ */\n+int ccp_dev_start(struct rte_cryptodev *dev);\n+\n+/**\n+ * Detect ccp platform and initialize all ccp devices\n+ *\n+ * @param ccp_id rte_pci_id list for supported CCP devices\n+ * @return no. of successfully initialized CCP devices\n+ */\n+int ccp_probe_devices(const struct rte_pci_id *ccp_id);\n+\n+/**\n+ * allocate a ccp command queue\n+ *\n+ * @dev rte crypto device\n+ * @param slot_req number of required\n+ * @return allotted CCP queue on success otherwise NULL\n+ */\n+struct ccp_queue *ccp_allot_queue(struct rte_cryptodev *dev, int slot_req);\n+\n+/**\n+ * read hwrng value\n+ *\n+ * @param trng_value data pointer to write RNG value\n+ * @return 0 on success otherwise -1\n+ */\n+int ccp_read_hwrng(uint32_t *trng_value);\n+\n+#endif /* _CCP_DEV_H_ */\ndiff --git a/drivers/crypto/ccp/ccp_pci.c b/drivers/crypto/ccp/ccp_pci.c\nnew file mode 100644\nindex 0000000..efc2ebf\n--- /dev/null\n+++ b/drivers/crypto/ccp/ccp_pci.c\n@@ -0,0 +1,331 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2017 Advance Micro Devices, Inc. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Advance Micro Devices, Inc nor the names\n+ * of its contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written\n+ * permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <dirent.h>\n+#include <fcntl.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <unistd.h>\n+\n+#include <rte_string_fns.h>\n+\n+#include <ccp_pci.h>\n+\n+static const char * const uio_module_names[] = {\n+\t\"igb_uio\",\n+\t\"uio_pci_generic\",\n+};\n+\n+int\n+ccp_check_pci_uio_module(void)\n+{\n+\tFILE *fp;\n+\tint i;\n+\tchar buf[BUFSIZ];\n+\n+\tfp = fopen(PROC_MODULES, \"r\");\n+\tif (fp == NULL)\n+\t\treturn -1;\n+\ti = 0;\n+\twhile (uio_module_names[i] != NULL) {\n+\t\twhile (fgets(buf, sizeof(buf), fp) != NULL) {\n+\t\t\tif (!strncmp(buf, uio_module_names[i],\n+\t\t\t\t strlen(uio_module_names[i])))\n+\t\t\t\treturn i;\n+\t\t}\n+\t\ti++;\n+\t\trewind(fp);\n+\t}\n+\tprintf(\"Insert igb_uio or uio_pci_generic kernel module(s)\");\n+\treturn -1;/* uio not inserted */\n+}\n+\n+/*\n+ * split up a pci address into its constituent parts.\n+ */\n+int\n+ccp_parse_pci_addr_format(const char *buf, int bufsize, uint16_t *domain,\n+\t\t\t uint8_t *bus, uint8_t *devid, uint8_t *function)\n+{\n+\t/* first split on ':' */\n+\tunion splitaddr {\n+\t\tstruct {\n+\t\t\tchar *domain;\n+\t\t\tchar *bus;\n+\t\t\tchar *devid;\n+\t\t\tchar *function;\n+\t\t};\n+\t\tchar *str[PCI_FMT_NVAL];\n+\t\t/* last element-separator is \".\" not \":\" */\n+\t} splitaddr;\n+\n+\tchar *buf_copy = strndup(buf, bufsize);\n+\n+\tif (buf_copy == NULL)\n+\t\treturn -1;\n+\n+\tif (rte_strsplit(buf_copy, bufsize, splitaddr.str, PCI_FMT_NVAL, ':')\n+\t\t\t!= PCI_FMT_NVAL - 1)\n+\t\tgoto error;\n+\t/* final split is on '.' between devid and function */\n+\tsplitaddr.function = strchr(splitaddr.devid, '.');\n+\tif (splitaddr.function == NULL)\n+\t\tgoto error;\n+\t*splitaddr.function++ = '\\0';\n+\n+\t/* now convert to int values */\n+\terrno = 0;\n+\t*domain = (uint8_t)strtoul(splitaddr.domain, NULL, 16);\n+\t*bus = (uint8_t)strtoul(splitaddr.bus, NULL, 16);\n+\t*devid = (uint8_t)strtoul(splitaddr.devid, NULL, 16);\n+\t*function = (uint8_t)strtoul(splitaddr.function, NULL, 10);\n+\tif (errno != 0)\n+\t\tgoto error;\n+\n+\tfree(buf_copy); /* free the copy made with strdup */\n+\treturn 0;\n+error:\n+\tfree(buf_copy);\n+\treturn -1;\n+}\n+\n+int\n+ccp_pci_parse_sysfs_value(const char *filename, unsigned long *val)\n+{\n+\tFILE *f;\n+\tchar buf[BUFSIZ];\n+\tchar *end = NULL;\n+\n+\tf = fopen(filename, \"r\");\n+\tif (f == NULL)\n+\t\treturn -1;\n+\tif (fgets(buf, sizeof(buf), f) == NULL) {\n+\t\tfclose(f);\n+\t\treturn -1;\n+\t}\n+\t*val = strtoul(buf, &end, 0);\n+\tif ((buf[0] == '\\0') || (end == NULL) || (*end != '\\n')) {\n+\t\tfclose(f);\n+\t\treturn -1;\n+\t}\n+\tfclose(f);\n+\treturn 0;\n+}\n+\n+/** IO resource type: */\n+#define IORESOURCE_IO 0x00000100\n+#define IORESOURCE_MEM 0x00000200\n+\n+/* parse one line of the \"resource\" sysfs file (note that the 'line'\n+ * string is modified)\n+ */\n+static int\n+ccp_pci_parse_one_sysfs_resource(char *line, size_t len, uint64_t *phys_addr,\n+\t\t\t\t uint64_t *end_addr, uint64_t *flags)\n+{\n+\tunion pci_resource_info {\n+\t\tstruct {\n+\t\t\tchar *phys_addr;\n+\t\t\tchar *end_addr;\n+\t\t\tchar *flags;\n+\t\t};\n+\t\tchar *ptrs[PCI_RESOURCE_FMT_NVAL];\n+\t} res_info;\n+\n+\tif (rte_strsplit(line, len, res_info.ptrs, 3, ' ') != 3)\n+\t\treturn -1;\n+\terrno = 0;\n+\t*phys_addr = strtoull(res_info.phys_addr, NULL, 16);\n+\t*end_addr = strtoull(res_info.end_addr, NULL, 16);\n+\t*flags = strtoull(res_info.flags, NULL, 16);\n+\tif (errno != 0)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+/* parse the \"resource\" sysfs file */\n+int\n+ccp_pci_parse_sysfs_resource(const char *filename, struct rte_pci_device *dev)\n+{\n+\tFILE *fp;\n+\tchar buf[BUFSIZ];\n+\tint i;\n+\tuint64_t phys_addr, end_addr, flags;\n+\n+\tfp = fopen(filename, \"r\");\n+\tif (fp == NULL)\n+\t\treturn -1;\n+\n+\tfor (i = 0; i < PCI_MAX_RESOURCE; i++) {\n+\t\tif (fgets(buf, sizeof(buf), fp) == NULL)\n+\t\t\tgoto error;\n+\t\tif (ccp_pci_parse_one_sysfs_resource(buf, sizeof(buf),\n+\t\t\t\t&phys_addr, &end_addr, &flags) < 0)\n+\t\t\tgoto error;\n+\n+\t\tif (flags & IORESOURCE_MEM) {\n+\t\t\tdev->mem_resource[i].phys_addr = phys_addr;\n+\t\t\tdev->mem_resource[i].len = end_addr - phys_addr + 1;\n+\t\t\t/* not mapped for now */\n+\t\t\tdev->mem_resource[i].addr = NULL;\n+\t\t}\n+\t}\n+\tfclose(fp);\n+\treturn 0;\n+\n+error:\n+\tfclose(fp);\n+\treturn -1;\n+}\n+\n+int\n+ccp_find_uio_devname(const char *dirname)\n+{\n+\n+\tDIR *dir;\n+\tstruct dirent *e;\n+\tchar dirname_uio[PATH_MAX];\n+\tunsigned int uio_num;\n+\tint ret = -1;\n+\n+\t/* depending on kernel version, uio can be located in uio/uioX\n+\t * or uio:uioX\n+\t */\n+\tsnprintf(dirname_uio, sizeof(dirname_uio), \"%s/uio\", dirname);\n+\tdir = opendir(dirname_uio);\n+\tif (dir == NULL) {\n+\t/* retry with the parent directory might be different kernel version*/\n+\t\tdir = opendir(dirname);\n+\t\tif (dir == NULL)\n+\t\t\treturn -1;\n+\t}\n+\n+\t/* take the first file starting with \"uio\" */\n+\twhile ((e = readdir(dir)) != NULL) {\n+\t\t/* format could be uio%d ...*/\n+\t\tint shortprefix_len = sizeof(\"uio\") - 1;\n+\t\t/* ... or uio:uio%d */\n+\t\tint longprefix_len = sizeof(\"uio:uio\") - 1;\n+\t\tchar *endptr;\n+\n+\t\tif (strncmp(e->d_name, \"uio\", 3) != 0)\n+\t\t\tcontinue;\n+\n+\t\t/* first try uio%d */\n+\t\terrno = 0;\n+\t\tuio_num = strtoull(e->d_name + shortprefix_len, &endptr, 10);\n+\t\tif (errno == 0 && endptr != (e->d_name + shortprefix_len)) {\n+\t\t\tret = uio_num;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* then try uio:uio%d */\n+\t\terrno = 0;\n+\t\tuio_num = strtoull(e->d_name + longprefix_len, &endptr, 10);\n+\t\tif (errno == 0 && endptr != (e->d_name + longprefix_len)) {\n+\t\t\tret = uio_num;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tclosedir(dir);\n+\treturn ret;\n+\n+\n+}\n+\n+#define UIO_NEWID \"/sys/bus/pci/drivers/%s/new_id\"\n+#define UIO_BIND \"/sys/bus/pci/drivers/%s/bind\"\n+\n+int\n+ccp_bind_uio(int idx, const char *dirname, struct rte_pci_id *id)\n+{\n+\tFILE *fp;\n+\tint cnt;\n+\tchar path[PATH_MAX];\n+\tchar *name = NULL;\n+\tchar buf[BUFSIZ];\n+\tchar driver_name[PATH_MAX];\n+\tchar filename[PATH_MAX];\n+\n+\tsnprintf(filename, sizeof(filename), \"%s/driver\", dirname);\n+\tcnt = readlink(filename, path, PATH_MAX);\n+\tif (cnt >= PATH_MAX)\n+\t\treturn -1;\n+\tif (cnt >= 0) {\n+\t\tpath[cnt] = '\\0';\n+\t\tname = strrchr(path, '/');\n+\t\tif (name) {\n+\t\t\tstrncpy(driver_name, name + 1, strlen(name + 1) + 1);\n+\t\t\tif (!strcmp(driver_name, uio_module_names[0]) ||\n+\t\t\t !strcmp(driver_name, uio_module_names[1]))\n+\t\t\t\treturn 0; /* Already binded */\n+\t\t\tsnprintf(filename, sizeof(filename), \"%s/driver/unbind\",\n+\t\t\t\t dirname);\n+\t\t\tfp = fopen(filename, \"w\");\n+\t\t\tif (fp != NULL) {\n+\t\t\t\tname = strrchr(dirname, '/');\n+\t\t\t\tname += 1;\n+\t\t\t\tif (fwrite(name, strlen(name), 1, fp) == 0) {\n+\t\t\t\t\tfclose(fp);\n+\t\t\t\t\treturn -1; /* Failed to unbind */\n+\t\t\t\t}\n+\t\t\t\tfclose(fp);\n+\t\t\t}\n+\t\t}\n+\t}\n+\tsnprintf(filename, sizeof(filename), UIO_NEWID, uio_module_names[idx]);\n+\tsnprintf(buf, sizeof(buf), \"%x %x\", id->vendor_id, id->device_id);\n+\tfp = fopen(filename, \"w\");\n+\tif (fp != NULL) {\n+\t\tif (fwrite(buf, strlen(buf), 1, fp) == 0) {\n+\t\t\tfclose(fp);\n+\t\t\treturn -1; /* Failed to bind */\n+\t\t}\n+\t\tfclose(fp);\n+\t} else\n+\t\treturn -1; /* Failed to bind */\n+\tsnprintf(filename, sizeof(filename), UIO_BIND, uio_module_names[idx]);\n+\tname = strrchr(dirname, '/');\n+\tname += 1;\n+\tfp = fopen(filename, \"w\");\n+\tif (fp != NULL) {\n+\t\tif (fwrite(name, strlen(name), 1, fp) == 0) {\n+\t\t\tfclose(fp);\n+\t\t\treturn -1; /* Failed to bind */\n+\t\t}\n+\t\tfclose(fp);\n+\t\treturn 0; /* Bind success*/\n+\t}\n+\treturn -1; /* Failed to bind */\n+}\ndiff --git a/drivers/crypto/ccp/ccp_pci.h b/drivers/crypto/ccp/ccp_pci.h\nnew file mode 100644\nindex 0000000..f187141\n--- /dev/null\n+++ b/drivers/crypto/ccp/ccp_pci.h\n@@ -0,0 +1,58 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2017 Advance Micro Devices, Inc. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Advance Micro Devices, Inc nor the names\n+ * of its contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written\n+ * permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _CCP_PCI_H_\n+#define _CCP_PCI_H_\n+\n+#include <stdint.h>\n+\n+#include <rte_pci.h>\n+\n+#define SYSFS_PCI_DEVICES \"/sys/bus/pci/devices\"\n+#define PROC_MODULES \"/proc/modules\"\n+\n+int ccp_check_pci_uio_module(void);\n+\n+int ccp_parse_pci_addr_format(const char *buf, int bufsize, uint16_t *domain,\n+\t\t\t uint8_t *bus, uint8_t *devid, uint8_t *function);\n+\n+int ccp_pci_parse_sysfs_value(const char *filename, unsigned long *val);\n+\n+int ccp_pci_parse_sysfs_resource(const char *filename,\n+\t\t\t\t struct rte_pci_device *dev);\n+\n+int ccp_find_uio_devname(const char *dirname);\n+\n+int ccp_bind_uio(int idx, const char *dirname, struct rte_pci_id *id);\n+\n+#endif /* _CCP_PCI_H_ */\ndiff --git a/drivers/crypto/ccp/ccp_pmd_ops.c b/drivers/crypto/ccp/ccp_pmd_ops.c\nnew file mode 100644\nindex 0000000..4b64aaf\n--- /dev/null\n+++ b/drivers/crypto/ccp/ccp_pmd_ops.c\n@@ -0,0 +1,860 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2017 Advance Micro Devices, Inc. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Advance Micro Devices, Inc nor the names\n+ * of its contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written\n+ * permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <string.h>\n+\n+#include <rte_common.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_malloc.h>\n+\n+#include <ccp_pmd_private.h>\n+#include <ccp_dev.h>\n+#include <ccp_crypto.h>\n+\n+static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = {\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\t{\t/* MD5 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_MD5_HMAC,\n+\t\t\t\t .block_size = 64,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 1,\n+\t\t\t\t\t .max = 64,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 16,\n+\t\t\t\t\t .max = 16,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+#endif\n+\t{\t/* SHA1 */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA1,\n+\t\t\t\t .block_size = 64,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 0,\n+\t\t\t\t\t .max = 0,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 20,\n+\t\t\t\t\t .max = 20,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA1 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,\n+\t\t\t\t .block_size = 64,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 1,\n+\t\t\t\t\t .max = 64,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 20,\n+\t\t\t\t\t .max = 20,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA224 */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA224,\n+\t\t\t\t .block_size = 64,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 0,\n+\t\t\t\t\t .max = 0,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 28,\n+\t\t\t\t\t .max = 28,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA224 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,\n+\t\t\t\t .block_size = 64,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 1,\n+\t\t\t\t\t .max = 64,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 28,\n+\t\t\t\t\t .max = 28,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA3-224 */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA3_224,\n+\t\t\t\t .block_size = 144,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 0,\n+\t\t\t\t\t .max = 0,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 28,\n+\t\t\t\t\t .max = 28,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA3-224 HMAC*/\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA3_224_HMAC,\n+\t\t\t\t .block_size = 144,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 1,\n+\t\t\t\t\t .max = 144,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 28,\n+\t\t\t\t\t .max = 28,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA256 */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA256,\n+\t\t\t\t .block_size = 64,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 0,\n+\t\t\t\t\t .max = 0,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 32,\n+\t\t\t\t\t .max = 32,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA256 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,\n+\t\t\t\t .block_size = 64,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 1,\n+\t\t\t\t\t .max = 64,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 32,\n+\t\t\t\t\t .max = 32,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA3-256 */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA3_256,\n+\t\t\t\t .block_size = 136,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 0,\n+\t\t\t\t\t .max = 0,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 32,\n+\t\t\t\t\t .max = 32,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA3-256-HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA3_256_HMAC,\n+\t\t\t\t .block_size = 136,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 1,\n+\t\t\t\t\t .max = 136,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 32,\n+\t\t\t\t\t .max = 32,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA384 */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA384,\n+\t\t\t\t .block_size = 128,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 0,\n+\t\t\t\t\t .max = 0,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 48,\n+\t\t\t\t\t .max = 48,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA384 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,\n+\t\t\t\t .block_size = 128,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 1,\n+\t\t\t\t\t .max = 128,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 48,\n+\t\t\t\t\t .max = 48,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA3-384 */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA3_384,\n+\t\t\t\t .block_size = 104,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 0,\n+\t\t\t\t\t .max = 0,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 48,\n+\t\t\t\t\t .max = 48,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA3-384-HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA3_384_HMAC,\n+\t\t\t\t .block_size = 104,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 1,\n+\t\t\t\t\t .max = 104,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 48,\n+\t\t\t\t\t .max = 48,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA512 */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA512,\n+\t\t\t\t .block_size = 128,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 0,\n+\t\t\t\t\t .max = 0,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 64,\n+\t\t\t\t\t .max = 64,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA512 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,\n+\t\t\t\t .block_size = 128,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 1,\n+\t\t\t\t\t .max = 128,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 64,\n+\t\t\t\t\t .max = 64,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA3-512 */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA3_512,\n+\t\t\t\t .block_size = 72,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 0,\n+\t\t\t\t\t .max = 0,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 64,\n+\t\t\t\t\t .max = 64,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t }, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA3-512-HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_SHA3_512_HMAC,\n+\t\t\t\t .block_size = 72,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 1,\n+\t\t\t\t\t .max = 72,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 64,\n+\t\t\t\t\t .max = 64,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/*AES-CMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t .algo = RTE_CRYPTO_AUTH_AES_CMAC,\n+\t\t\t\t .block_size = 16,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 16,\n+\t\t\t\t\t .max = 32,\n+\t\t\t\t\t .increment = 8\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 16,\n+\t\t\t\t\t .max = 16,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = { 0 }\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{ /* AES ECB */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_ECB,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t .min = 16,\n+\t\t\t\t .max = 32,\n+\t\t\t\t .increment = 8\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t .min = 0,\n+\t\t\t\t .max = 0,\n+\t\t\t\t .increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{ /* AES CBC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_CBC,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* AES CTR */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_CTR,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 20,\n+\t\t\t\t\t.max = 36,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 8,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* 3DES CBC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_3DES_CBC,\n+\t\t\t\t.block_size = 8,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 24,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 8,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{ /* AES GCM */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\n+\t\t\t{.aead = {\n+\t\t\t\t .algo = RTE_CRYPTO_AEAD_AES_GCM,\n+\t\t\t\t .block_size = 16,\n+\t\t\t\t .key_size = {\n+\t\t\t\t\t .min = 16,\n+\t\t\t\t\t .max = 32,\n+\t\t\t\t\t .increment = 8\n+\t\t\t\t },\n+\t\t\t\t .digest_size = {\n+\t\t\t\t\t .min = 16,\n+\t\t\t\t\t .max = 16,\n+\t\t\t\t\t .increment = 0\n+\t\t\t\t },\n+\t\t\t\t .aad_size = {\n+\t\t\t\t\t .min = 0,\n+\t\t\t\t\t .max = 65535,\n+\t\t\t\t\t .increment = 1\n+\t\t\t\t },\n+\t\t\t\t .iv_size = {\n+\t\t\t\t\t .min = 12,\n+\t\t\t\t\t .max = 16,\n+\t\t\t\t\t .increment = 4\n+\t\t\t\t },\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+static int\n+ccp_pmd_config(struct rte_cryptodev *dev __rte_unused,\n+\t struct rte_cryptodev_config *config __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+static int\n+ccp_pmd_start(struct rte_cryptodev *dev)\n+{\n+\treturn ccp_dev_start(dev);\n+}\n+\n+static void\n+ccp_pmd_stop(struct rte_cryptodev *dev __rte_unused)\n+{\n+\n+}\n+\n+static int\n+ccp_pmd_close(struct rte_cryptodev *dev __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+static void\n+ccp_pmd_stats_get(struct rte_cryptodev *dev,\n+\t\t struct rte_cryptodev_stats *stats)\n+{\n+\tint qp_id;\n+\n+\tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n+\t\tstruct ccp_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\t\tstats->enqueued_count += qp->qp_stats.enqueued_count;\n+\t\tstats->dequeued_count += qp->qp_stats.dequeued_count;\n+\n+\t\tstats->enqueue_err_count += qp->qp_stats.enqueue_err_count;\n+\t\tstats->dequeue_err_count += qp->qp_stats.dequeue_err_count;\n+\t}\n+\n+}\n+\n+static void\n+ccp_pmd_stats_reset(struct rte_cryptodev *dev)\n+{\n+\tint qp_id;\n+\n+\tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n+\t\tstruct ccp_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\t\tmemset(&qp->qp_stats, 0, sizeof(qp->qp_stats));\n+\t}\n+}\n+\n+static void\n+ccp_pmd_info_get(struct rte_cryptodev *dev,\n+\t\t struct rte_cryptodev_info *dev_info)\n+{\n+\tstruct ccp_private *internals = dev->data->dev_private;\n+\n+\tif (dev_info != NULL) {\n+\t\tdev_info->driver_id = dev->driver_id;\n+\t\tdev_info->feature_flags = dev->feature_flags;\n+\t\tdev_info->capabilities = ccp_pmd_capabilities;\n+\t\tdev_info->max_nb_queue_pairs = internals->max_nb_qpairs;\n+\t\tdev_info->sym.max_nb_sessions = internals->max_nb_sessions;\n+\t}\n+}\n+\n+static int\n+ccp_pmd_qp_release(struct rte_cryptodev *dev, uint16_t qp_id)\n+{\n+\tif (dev->data->queue_pairs[qp_id] != NULL) {\n+\t\trte_free(dev->data->queue_pairs[qp_id]);\n+\t\tdev->data->queue_pairs[qp_id] = NULL;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+ccp_pmd_qp_set_unique_name(struct rte_cryptodev *dev,\n+\t\tstruct ccp_qp *qp)\n+{\n+\tunsigned int n = snprintf(qp->name, sizeof(qp->name),\n+\t\t\t\"ccp_pmd_%u_qp_%u\",\n+\t\t\tdev->data->dev_id, qp->id);\n+\n+\tif (n > sizeof(qp->name))\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+static struct rte_ring *\n+ccp_pmd_qp_create_batch_info_ring(struct ccp_qp *qp,\n+\t\t\t\t unsigned int ring_size, int socket_id)\n+{\n+\tstruct rte_ring *r;\n+\n+\tr = rte_ring_lookup(qp->name);\n+\tif (r) {\n+\t\tif (r->size >= ring_size) {\n+\t\t\tCCP_LOG_INFO(\n+\t\t\t\t\"Reusing ring %s for processed packets\",\n+\t\t\t\tqp->name);\n+\t\t\treturn r;\n+\t\t}\n+\t\tCCP_LOG_INFO(\n+\t\t\t\"Unable to reuse ring %s for processed packets\",\n+\t\t\t qp->name);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn rte_ring_create(qp->name, ring_size, socket_id,\n+\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n+}\n+\n+static int\n+ccp_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n+\t\t const struct rte_cryptodev_qp_conf *qp_conf,\n+\t\t int socket_id, struct rte_mempool *session_pool)\n+{\n+\tstruct ccp_private *internals = dev->data->dev_private;\n+\tstruct ccp_qp *qp;\n+\tint retval = 0;\n+\n+\tif (qp_id >= internals->max_nb_qpairs) {\n+\t\tCCP_LOG_ERR(\"Invalid qp_id %u, should be less than %u\",\n+\t\t\t qp_id, internals->max_nb_qpairs);\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\t/* Free memory prior to re-allocation if needed. */\n+\tif (dev->data->queue_pairs[qp_id] != NULL)\n+\t\tccp_pmd_qp_release(dev, qp_id);\n+\n+\t/* Allocate the queue pair data structure. */\n+\tqp = rte_zmalloc_socket(\"CCP Crypto PMD Queue Pair\", sizeof(*qp),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n+\tif (qp == NULL) {\n+\t\tCCP_LOG_ERR(\"Failed to allocate queue pair memory\");\n+\t\treturn (-ENOMEM);\n+\t}\n+\n+\tqp->dev = dev;\n+\tqp->id = qp_id;\n+\tdev->data->queue_pairs[qp_id] = qp;\n+\n+\tretval = ccp_pmd_qp_set_unique_name(dev, qp);\n+\tif (retval) {\n+\t\tCCP_LOG_ERR(\"Failed to create unique name for ccp qp\");\n+\t\tgoto qp_setup_cleanup;\n+\t}\n+\n+\tqp->processed_pkts = ccp_pmd_qp_create_batch_info_ring(qp,\n+\t\t\tqp_conf->nb_descriptors, socket_id);\n+\tif (qp->processed_pkts == NULL) {\n+\t\tCCP_LOG_ERR(\"Failed to create batch info ring\");\n+\t\tgoto qp_setup_cleanup;\n+\t}\n+\n+\tqp->sess_mp = session_pool;\n+\n+\t/* mempool for batch info*/\n+\tqp->batch_mp = rte_mempool_create(\n+\t\t\t\tqp->name,\n+\t\t\t\tqp_conf->nb_descriptors,\n+\t\t\t\tsizeof(struct ccp_batch_info),\n+\t\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\t\t0, NULL, NULL, NULL, NULL,\n+\t\t\t\tSOCKET_ID_ANY, 0);\n+\tif (qp->batch_mp == NULL)\n+\t\tgoto qp_setup_cleanup;\n+\tmemset(&qp->qp_stats, 0, sizeof(qp->qp_stats));\n+\treturn 0;\n+\n+qp_setup_cleanup:\n+\tdev->data->queue_pairs[qp_id] = NULL;\n+\tif (qp)\n+\t\trte_free(qp);\n+\treturn -1;\n+}\n+\n+static int\n+ccp_pmd_qp_start(struct rte_cryptodev *dev __rte_unused,\n+\t\t uint16_t queue_pair_id __rte_unused)\n+{\n+\treturn -ENOTSUP;\n+}\n+\n+static int\n+ccp_pmd_qp_stop(struct rte_cryptodev *dev __rte_unused,\n+\t\tuint16_t queue_pair_id __rte_unused)\n+{\n+\treturn -ENOTSUP;\n+}\n+\n+static uint32_t\n+ccp_pmd_qp_count(struct rte_cryptodev *dev)\n+{\n+\treturn dev->data->nb_queue_pairs;\n+}\n+\n+static unsigned\n+ccp_pmd_session_get_size(struct rte_cryptodev *dev __rte_unused)\n+{\n+\treturn sizeof(struct ccp_session);\n+}\n+\n+static int\n+ccp_pmd_session_configure(struct rte_cryptodev *dev,\n+\t\t\t struct rte_crypto_sym_xform *xform,\n+\t\t\t struct rte_cryptodev_sym_session *sess,\n+\t\t\t struct rte_mempool *mempool)\n+{\n+\tint ret;\n+\tvoid *sess_private_data;\n+\n+\tif (unlikely(sess == NULL || xform == NULL)) {\n+\t\tCCP_LOG_ERR(\"Invalid session struct or xform\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (rte_mempool_get(mempool, &sess_private_data)) {\n+\t\tCCP_LOG_ERR(\"Couldn't get object from session mempool\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tret = ccp_set_session_parameters(sess_private_data, xform);\n+\tif (ret != 0) {\n+\t\tCCP_LOG_ERR(\"failed configure session parameters\");\n+\n+\t\t/* Return session to mempool */\n+\t\trte_mempool_put(mempool, sess_private_data);\n+\t\treturn ret;\n+\t}\n+\tset_session_private_data(sess, dev->driver_id,\n+\t\t\t\t sess_private_data);\n+\n+\treturn 0;\n+}\n+\n+static void\n+ccp_pmd_session_clear(struct rte_cryptodev *dev,\n+\t\t struct rte_cryptodev_sym_session *sess)\n+{\n+\tuint8_t index = dev->driver_id;\n+\tvoid *sess_priv = get_session_private_data(sess, index);\n+\n+\tif (sess_priv) {\n+\t\tstruct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);\n+\n+\t\trte_mempool_put(sess_mp, sess_priv);\n+\t\tmemset(sess_priv, 0, sizeof(struct ccp_session));\n+\t\tset_session_private_data(sess, index, NULL);\n+\t}\n+}\n+\n+struct rte_cryptodev_ops ccp_ops = {\n+\t\t.dev_configure\t\t= ccp_pmd_config,\n+\t\t.dev_start\t\t= ccp_pmd_start,\n+\t\t.dev_stop\t\t= ccp_pmd_stop,\n+\t\t.dev_close\t\t= ccp_pmd_close,\n+\n+\t\t.stats_get\t\t= ccp_pmd_stats_get,\n+\t\t.stats_reset\t\t= ccp_pmd_stats_reset,\n+\n+\t\t.dev_infos_get\t\t= ccp_pmd_info_get,\n+\n+\t\t.queue_pair_setup\t= ccp_pmd_qp_setup,\n+\t\t.queue_pair_release\t= ccp_pmd_qp_release,\n+\t\t.queue_pair_start\t= ccp_pmd_qp_start,\n+\t\t.queue_pair_stop\t= ccp_pmd_qp_stop,\n+\t\t.queue_pair_count\t= ccp_pmd_qp_count,\n+\n+\t\t.session_get_size\t= ccp_pmd_session_get_size,\n+\t\t.session_configure\t= ccp_pmd_session_configure,\n+\t\t.session_clear\t\t= ccp_pmd_session_clear\n+};\n+\n+struct rte_cryptodev_ops *ccp_pmd_ops = &ccp_ops;\ndiff --git a/drivers/crypto/ccp/ccp_pmd_private.h b/drivers/crypto/ccp/ccp_pmd_private.h\nnew file mode 100644\nindex 0000000..ab5e82b\n--- /dev/null\n+++ b/drivers/crypto/ccp/ccp_pmd_private.h\n@@ -0,0 +1,135 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2017 Advance Micro Devices, Inc. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Advance Micro Devices, Inc nor the names\n+ * of its contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written\n+ * permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _CCP_PMD_PRIVATE_H_\n+#define _CCP_PMD_PRIVATE_H_\n+\n+#include <rte_config.h>\n+#include <rte_cryptodev.h>\n+\n+#define CRYPTODEV_NAME_CCP_PMD crypto_ccp\n+\n+#define CCP_LOG_ERR(fmt, args...) \\\n+\tRTE_LOG(ERR, CRYPTODEV, \"[%s] %s() line %u: \" fmt \"\\n\", \\\n+\t\t\tRTE_STR(CRYPTODEV_NAME_CCP_PMD), \\\n+\t\t\t__func__, __LINE__, ## args)\n+\n+#ifdef RTE_LIBRTE_CCP_DEBUG\n+#define CCP_LOG_INFO(fmt, args...) \\\n+\tRTE_LOG(INFO, CRYPTODEV, \"[%s] %s() line %u: \" fmt \"\\n\", \\\n+\t\t\tRTE_STR(CRYPTODEV_NAME_CCP_PMD), \\\n+\t\t\t__func__, __LINE__, ## args)\n+\n+#define CCP_LOG_DBG(fmt, args...) \\\n+\tRTE_LOG(DEBUG, CRYPTODEV, \"[%s] %s() line %u: \" fmt \"\\n\", \\\n+\t\t\tRTE_STR(CRYPTODEV_NAME_CCP_PMD), \\\n+\t\t\t__func__, __LINE__, ## args)\n+#else\n+#define CCP_LOG_INFO(fmt, args...)\n+#define CCP_LOG_DBG(fmt, args...)\n+#endif\n+\n+/**< Maximum queue pairs supported by CCP PMD */\n+#define CCP_PMD_MAX_QUEUE_PAIRS\t1\n+#define CCP_NB_MAX_DESCRIPTORS 1024\n+#define CCP_MAX_BURST 64\n+\n+#include <ccp_dev.h>\n+\n+/* private data structure for each CCP crypto device */\n+struct ccp_private {\n+\tunsigned int max_nb_qpairs;\t/**< Max number of queue pairs */\n+\tunsigned int max_nb_sessions;\t/**< Max number of sessions */\n+\tuint8_t crypto_num_dev;\t\t/**< Number of working crypto devices */\n+\tstruct ccp_device *last_dev;\t/**< Last working crypto device */\n+};\n+\n+/* CCP batch info */\n+struct ccp_batch_info {\n+\tstruct rte_crypto_op *op[CCP_MAX_BURST];\n+\t/**< optable populated at enque time from app*/\n+\tint op_idx;\n+\tstruct ccp_queue *cmd_q;\n+\tuint16_t opcnt;\n+\t/**<# of crypto ops in batch*/\n+\tint desccnt;\n+\t/**<# of ccp queue descriptors*/\n+\tuint32_t head_offset;\n+\t/**< ccp queue head tail offsets time of enqueue*/\n+\tuint32_t tail_offset;\n+\tuint8_t lsb_buf[CCP_SB_BYTES * CCP_MAX_BURST];\n+\tphys_addr_t lsb_buf_phys;\n+\t/**< LSB intermediate buf for passthru */\n+\tint lsb_buf_idx;\n+#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH\n+\tint auth_only;\n+\t/**< auth only ops batch */\n+#endif\n+} __rte_cache_aligned;\n+\n+/**< CCP crypto queue pair */\n+struct ccp_qp {\n+\tuint16_t id;\n+\t/**< Queue Pair Identifier */\n+\tchar name[RTE_CRYPTODEV_NAME_LEN];\n+\t/**< Unique Queue Pair Name */\n+\tstruct rte_ring *processed_pkts;\n+\t/**< Ring for placing process packets */\n+\tstruct rte_mempool *sess_mp;\n+\t/**< Session Mempool */\n+\tstruct rte_mempool *batch_mp;\n+\t/**< Session Mempool for batch info */\n+\tstruct rte_cryptodev_stats qp_stats;\n+\t/**< Queue pair statistics */\n+\tstruct ccp_batch_info *b_info;\n+\t/**< Store ops pulled out of queue */\n+\tstruct rte_cryptodev *dev;\n+\t/**< rte crypto device to which this qp belongs */\n+} __rte_cache_aligned;\n+\n+\n+/**< device specific operations function pointer structure */\n+extern struct rte_cryptodev_ops *ccp_pmd_ops;\n+\n+\n+extern struct rte_cryptodev_ops *ccp_cpu_pmd_ops;\n+uint16_t\n+ccp_cpu_pmd_enqueue_burst(void *queue_pair,\n+\t\t\t struct rte_crypto_op **ops,\n+\t\t\t uint16_t nb_ops);\n+uint16_t\n+ccp_cpu_pmd_dequeue_burst(void *queue_pair,\n+\t\t\t struct rte_crypto_op **ops,\n+\t\t\t uint16_t nb_ops);\n+\n+#endif /* _CCP_PMD_PRIVATE_H_ */\ndiff --git a/drivers/crypto/ccp/rte_ccp_pmd.c b/drivers/crypto/ccp/rte_ccp_pmd.c\nnew file mode 100644\nindex 0000000..e7e3b99\n--- /dev/null\n+++ b/drivers/crypto/ccp/rte_ccp_pmd.c\n@@ -0,0 +1,283 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2017 Advance Micro Devices, Inc. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Advance Micro Devices, Inc nor the names\n+ * of its contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written\n+ * permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_config.h>\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_cryptodev_vdev.h>\n+#include <rte_vdev.h>\n+#include <rte_malloc.h>\n+\n+#include <ccp_crypto.h>\n+#include <ccp_dev.h>\n+#include <ccp_pmd_private.h>\n+\n+/**\n+ * Global static parameter used to find if CCP device is already initialized.\n+ */\n+static unsigned int ccp_pmd_init_done;\n+uint8_t cryptodev_driver_id;\n+\n+static struct ccp_session *\n+get_ccp_session(struct ccp_qp *qp, struct rte_crypto_op *op)\n+{\n+\tstruct ccp_session *sess = NULL;\n+\n+\tif (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {\n+\t\tif (unlikely(op->sym->session == NULL))\n+\t\t\treturn NULL;\n+\n+\t\tsess = (struct ccp_session *)\n+\t\t\tget_session_private_data(\n+\t\t\t\top->sym->session,\n+\t\t\t\tcryptodev_driver_id);\n+\t} else {\n+\t\tvoid *_sess;\n+\t\tvoid *_sess_private_data = NULL;\n+\n+\t\tif (rte_mempool_get(qp->sess_mp, &_sess))\n+\t\t\treturn NULL;\n+\t\tif (rte_mempool_get(qp->sess_mp, (void **)&_sess_private_data))\n+\t\t\treturn NULL;\n+\n+\t\tsess = (struct ccp_session *)_sess_private_data;\n+\n+\t\tif (unlikely(ccp_set_session_parameters(sess,\n+\t\t\t\t\t\t\top->sym->xform) != 0)) {\n+\t\t\trte_mempool_put(qp->sess_mp, _sess);\n+\t\t\trte_mempool_put(qp->sess_mp, _sess_private_data);\n+\t\t\tsess = NULL;\n+\t\t}\n+\t\top->sym->session = (struct rte_cryptodev_sym_session *)_sess;\n+\t\tset_session_private_data(op->sym->session, cryptodev_driver_id,\n+\t\t\t\t\t _sess_private_data);\n+\t}\n+\n+\treturn sess;\n+}\n+\n+static uint16_t\n+ccp_pmd_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,\n+\t\t uint16_t nb_ops)\n+{\n+\tstruct ccp_session *sess = NULL;\n+\tstruct ccp_qp *qp = queue_pair;\n+\tstruct ccp_queue *cmd_q;\n+\tstruct rte_cryptodev *dev = qp->dev;\n+\tint i, enq_cnt, slots_req = 0;\n+\n+\tif (nb_ops == 0)\n+\t\treturn 0;\n+\n+\tif (unlikely(rte_ring_full(qp->processed_pkts) != 0))\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < nb_ops; i++) {\n+\t\tsess = get_ccp_session(qp, ops[i]);\n+\t\tif (unlikely(sess == NULL) && (i == 0)) {\n+\t\t\tqp->qp_stats.enqueue_err_count++;\n+\t\t\treturn 0;\n+\t\t} else if (sess == NULL) {\n+\t\t\tnb_ops = i;\n+\t\t\tbreak;\n+\t\t}\n+\t\tslots_req += ccp_compute_slot_count(sess);\n+\t}\n+\n+\tcmd_q = ccp_allot_queue(dev, slots_req);\n+\tif (unlikely(cmd_q == NULL))\n+\t\treturn 0;\n+\n+\tenq_cnt = process_ops_to_enqueue(qp, ops, cmd_q, nb_ops, slots_req);\n+\tqp->qp_stats.enqueued_count += enq_cnt;\n+\treturn enq_cnt;\n+}\n+\n+static uint16_t\n+ccp_pmd_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops,\n+\t\tuint16_t nb_ops)\n+{\n+\tstruct ccp_qp *qp = queue_pair;\n+\tunsigned int nb_dequeued, i;\n+\n+\tnb_dequeued = process_ops_to_dequeue(qp, ops, nb_ops);\n+\n+\t/* Free session if a session-less crypto op. */\n+\tfor (i = 0; i < nb_dequeued; i++)\n+\t\tif (unlikely(ops[i]->sess_type ==\n+\t\t\t RTE_CRYPTO_OP_SESSIONLESS)) {\n+\t\t\trte_mempool_put(qp->sess_mp, ops[i]->sym->session);\n+\t\t\tops[i]->sym->session = NULL;\n+\t\t}\n+\tqp->qp_stats.dequeued_count += nb_dequeued;\n+\n+\treturn nb_dequeued;\n+}\n+\n+/*\n+ * The set of PCI devices this driver supports\n+ */\n+static struct rte_pci_id ccp_pci_id[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(0x1022, 0x1456), /* AMD CCP-5a */\n+\t},\n+\t{\n+\t\tRTE_PCI_DEVICE(0x1022, 0x1468), /* AMD CCP-5b */\n+\t},\n+\t{.device_id = 0},\n+};\n+\n+/** Remove ccp pmd */\n+static int\n+cryptodev_ccp_remove(struct rte_vdev_device *dev)\n+{\n+\tconst char *name;\n+\n+\tname = rte_vdev_device_name(dev);\n+\tif (name == NULL)\n+\t\treturn -EINVAL;\n+\n+\tRTE_LOG(INFO, PMD, \"Closing ccp device %s on numa socket %u\\n\",\n+\t\t\tname, rte_socket_id());\n+\n+\treturn 0;\n+}\n+\n+/** Create crypto device */\n+static int\n+cryptodev_ccp_create(const char *name,\n+\t\t struct rte_vdev_device *vdev,\n+\t\t struct rte_crypto_vdev_init_params *init_params)\n+{\n+\tstruct rte_cryptodev *dev;\n+\tstruct ccp_private *internals;\n+\tuint8_t cryptodev_cnt = 0;\n+\n+\tif (init_params->name[0] == '\\0')\n+\t\tsnprintf(init_params->name, sizeof(init_params->name),\n+\t\t\t\t\"%s\", name);\n+\n+\tdev = rte_cryptodev_vdev_pmd_init(init_params->name,\n+\t\t\tsizeof(struct ccp_private),\n+\t\t\tinit_params->socket_id,\n+\t\t\tvdev);\n+\tif (dev == NULL) {\n+\t\tCCP_LOG_ERR(\"failed to create cryptodev vdev\");\n+\t\tgoto init_error;\n+\t}\n+\n+\tcryptodev_cnt = ccp_probe_devices(ccp_pci_id);\n+\n+\tif (cryptodev_cnt == 0) {\n+\t\tCCP_LOG_ERR(\"failed to detect CCP crypto device\");\n+\t\tgoto init_error;\n+\t}\n+\n+\tprintf(\"CCP : Crypto device count = %d\\n\", cryptodev_cnt);\n+\tdev->driver_id = cryptodev_driver_id;\n+\n+\t/* register rx/tx burst functions for data path */\n+\tdev->dev_ops = ccp_pmd_ops;\n+\tdev->enqueue_burst = ccp_pmd_enqueue_burst;\n+\tdev->dequeue_burst = ccp_pmd_dequeue_burst;\n+\n+\tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n+\t\t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n+\t\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING;\n+\n+\tinternals = dev->data->dev_private;\n+\n+\tinternals->max_nb_qpairs = init_params->max_nb_queue_pairs;\n+\tinternals->max_nb_sessions = init_params->max_nb_sessions;\n+\tinternals->crypto_num_dev = cryptodev_cnt;\n+\n+\treturn 0;\n+\n+init_error:\n+\tCCP_LOG_ERR(\"driver %s: cryptodev_ccp_create failed\",\n+\t\t init_params->name);\n+\tcryptodev_ccp_remove(vdev);\n+\n+\treturn -EFAULT;\n+}\n+\n+/** Probe ccp pmd */\n+static int\n+cryptodev_ccp_probe(struct rte_vdev_device *vdev)\n+{\n+\tint rc = 0;\n+\tconst char *name;\n+\tstruct rte_crypto_vdev_init_params init_params = {\n+\t\tCCP_PMD_MAX_QUEUE_PAIRS,\n+\t\tRTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_SESSIONS,\n+\t\trte_socket_id(),\n+\t\t{0}\n+\t};\n+\tconst char *input_args;\n+\n+\tif (ccp_pmd_init_done) {\n+\t\tRTE_LOG(INFO, PMD, \"CCP PMD already initialized\\n\");\n+\t\treturn -EFAULT;\n+\t}\n+\tname = rte_vdev_device_name(vdev);\n+\tif (name == NULL)\n+\t\treturn -EINVAL;\n+\n+\tinput_args = rte_vdev_device_args(vdev);\n+\trte_cryptodev_vdev_parse_init_params(&init_params, input_args);\n+\tinit_params.max_nb_queue_pairs = CCP_PMD_MAX_QUEUE_PAIRS;\n+\n+\tRTE_LOG(INFO, PMD, \"Initialising %s on NUMA node %d\\n\", name,\n+\t\t\tinit_params.socket_id);\n+\tRTE_LOG(INFO, PMD, \"Max number of queue pairs = %d\\n\",\n+\t\t\tinit_params.max_nb_queue_pairs);\n+\tRTE_LOG(INFO, PMD, \"Max number of sessions = %d\\n\",\n+\t\t\tinit_params.max_nb_sessions);\n+\n+\trc = cryptodev_ccp_create(name, vdev, &init_params);\n+\tif (rc)\n+\t\treturn rc;\n+\tccp_pmd_init_done = 1;\n+\treturn 0;\n+}\n+\n+static struct rte_vdev_driver cryptodev_ccp_pmd_drv = {\n+\t.probe = cryptodev_ccp_probe,\n+\t.remove = cryptodev_ccp_remove\n+};\n+\n+RTE_PMD_REGISTER_VDEV(CRYPTODEV_NAME_CCP_PMD, cryptodev_ccp_pmd_drv);\n+RTE_PMD_REGISTER_PARAM_STRING(CRYPTODEV_NAME_CCP_PMD,\n+\t\"max_nb_queue_pairs=<int> max_nb_sessions=<int> socket_id=<int>\");\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(cryptodev_ccp_pmd_drv, cryptodev_driver_id);\ndiff --git a/drivers/crypto/ccp/rte_pmd_ccp_version.map b/drivers/crypto/ccp/rte_pmd_ccp_version.map\nnew file mode 100644\nindex 0000000..a753031\n--- /dev/null\n+++ b/drivers/crypto/ccp/rte_pmd_ccp_version.map\n@@ -0,0 +1,3 @@\n+DPDK_17.11 {\n+\tlocal: *;\n+};\ndiff --git a/lib/librte_cryptodev/rte_crypto_sym.h b/lib/librte_cryptodev/rte_crypto_sym.h\nindex 0ceaa91..eea3c87 100644\n--- a/lib/librte_cryptodev/rte_crypto_sym.h\n+++ b/lib/librte_cryptodev/rte_crypto_sym.h\n@@ -274,6 +274,24 @@ enum rte_crypto_auth_algorithm {\n \tRTE_CRYPTO_AUTH_ZUC_EIA3,\n \t/**< ZUC algorithm in EIA3 mode */\n \n+\t/**< SHA3 algorithm support*/\n+\tRTE_CRYPTO_AUTH_SHA3_224,\n+\t/**< 224 bit SHA3 algorithm. */\n+\tRTE_CRYPTO_AUTH_SHA3_224_HMAC,\n+\t/**< HMAC using 224 bit SHA3 algorithm. */\n+\tRTE_CRYPTO_AUTH_SHA3_256,\n+\t/**< 256 bit SHA3 algorithm. */\n+\tRTE_CRYPTO_AUTH_SHA3_256_HMAC,\n+\t/**< HMAC using 256 bit SHA3 algorithm. */\n+\tRTE_CRYPTO_AUTH_SHA3_384,\n+\t/**< 384 bit SHA3 algorithm. */\n+\tRTE_CRYPTO_AUTH_SHA3_384_HMAC,\n+\t/**< HMAC using 384 bit SHA3 algorithm. */\n+\tRTE_CRYPTO_AUTH_SHA3_512,\n+\t/**< 512 bit SHA3 algorithm. */\n+\tRTE_CRYPTO_AUTH_SHA3_512_HMAC,\n+\t/**< HMAC using 512 bit SHA3 algorithm. */\n+\n \tRTE_CRYPTO_AUTH_LIST_END\n };\n \ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex c25fdd9..c65bd55 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -152,6 +152,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += -L$(AESNI_MULTI_BUFFER_LIB_PATH)\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += -lrte_pmd_aesni_gcm\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += -L$(AESNI_MULTI_BUFFER_LIB_PATH) -lIPSec_MB\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += -lrte_pmd_openssl -lcrypto\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += -lrte_pmd_ccp -lcrypto\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO) += -lrte_pmd_null_crypto\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += -lrte_pmd_qat -lcrypto\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += -lrte_pmd_snow3g\n", "prefixes": [ "dpdk-dev" ] }