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GET /api/patches/27972/?format=api
{ "id": 27972, "url": "http://patches.dpdk.org/api/patches/27972/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1503658183-4078-18-git-send-email-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1503658183-4078-18-git-send-email-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1503658183-4078-18-git-send-email-hemant.agrawal@nxp.com", "date": "2017-08-25T10:49:33", "name": "[dpdk-dev,17/27] net/dpaa2: add support for link status event", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0a091ad582e5c06a139396d23a47f725015e1370", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1503658183-4078-18-git-send-email-hemant.agrawal@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/27972/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/27972/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 222BD9989;\n\tFri, 25 Aug 2017 12:50:40 +0200 (CEST)", "from NAM03-DM3-obe.outbound.protection.outlook.com\n\t(mail-dm3nam03on0060.outbound.protection.outlook.com [104.47.41.60])\n\tby dpdk.org (Postfix) with ESMTP id E52CF9155\n\tfor <dev@dpdk.org>; Fri, 25 Aug 2017 12:50:34 +0200 (CEST)", "from DM5PR03CA0034.namprd03.prod.outlook.com (10.174.189.151) by\n\tCO2PR03MB2262.namprd03.prod.outlook.com (10.166.92.143) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.1.1385.9; Fri, 25 Aug 2017 10:50:33 +0000", "from BY2FFO11OLC003.protection.gbl (2a01:111:f400:7c0c::160) by\n\tDM5PR03CA0034.outlook.office365.com (2603:10b6:4:3b::23) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.1.1385.9 via Frontend Transport; Fri, 25 Aug 2017 10:50:33 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBY2FFO11OLC003.mail.protection.outlook.com (10.1.15.183) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1341.15\n\tvia Frontend Transport; Fri, 25 Aug 2017 10:50:33 +0000", "from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net\n\t[10.232.134.28])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv7PAnw6L032070; Fri, 25 Aug 2017 03:50:31 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "<ferruh.yigit@intel.com>", "CC": "<dev@dpdk.org>, <shreyansh.jain@nxp.com>", "Date": "Fri, 25 Aug 2017 16:19:33 +0530", "Message-ID": "<1503658183-4078-18-git-send-email-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1503658183-4078-1-git-send-email-hemant.agrawal@nxp.com>", "References": "<1503658183-4078-1-git-send-email-hemant.agrawal@nxp.com>", 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"5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CO2PR03MB2262", "Subject": "[dpdk-dev] [PATCH 17/27] net/dpaa2: add support for link status\n\tevent", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n doc/guides/nics/features/dpaa2.ini | 1 +\n drivers/net/dpaa2/dpaa2_ethdev.c | 123 +++++++++++++++++++\n drivers/net/dpaa2/mc/dpni.c | 233 ++++++++++++++++++++++++++++++++++++\n drivers/net/dpaa2/mc/fsl_dpni.h | 49 ++++++++\n drivers/net/dpaa2/mc/fsl_dpni_cmd.h | 50 ++++++++\n 5 files changed, 456 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/dpaa2.ini b/doc/guides/nics/features/dpaa2.ini\nindex 146e087..ba4321c 100644\n--- a/doc/guides/nics/features/dpaa2.ini\n+++ b/doc/guides/nics/features/dpaa2.ini\n@@ -6,6 +6,7 @@\n [Features]\n Speed capabilities = P\n Link status = Y\n+Link status event = Y\n Queue start/stop = Y\n Jumbo frame = Y\n MTU update = Y\ndiff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c\nindex d7950a5..49dc42b 100644\n--- a/drivers/net/dpaa2/dpaa2_ethdev.c\n+++ b/drivers/net/dpaa2/dpaa2_ethdev.c\n@@ -54,6 +54,8 @@\n \n static struct rte_dpaa2_driver rte_dpaa2_pmd;\n static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);\n+static int dpaa2_dev_link_update(struct rte_eth_dev *dev,\n+\t\t\t\t int wait_to_complete);\n static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);\n static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);\n static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n@@ -344,6 +346,10 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev)\n \t\t\treturn ret;\n \t\t}\n \t}\n+\n+\t/* update the current status */\n+\tdpaa2_dev_link_update(dev, 0);\n+\n \treturn 0;\n }\n \n@@ -556,9 +562,87 @@ dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)\n \treturn NULL;\n }\n \n+/**\n+ * Dpaa2 link Interrupt handler\n+ *\n+ * @param param\n+ * The address of parameter (struct rte_eth_dev *) regsitered before.\n+ *\n+ * @return\n+ * void\n+ */\n+static void\n+dpaa2_interrupt_handler(void *param)\n+{\n+\tstruct rte_eth_dev *dev = param;\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n+\tint ret;\n+\tint irq_index = DPNI_IRQ_INDEX;\n+\tunsigned int status, clear = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (dpni == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"dpni is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,\n+\t\t\t\t irq_index, &status);\n+\tif (unlikely(ret)) {\n+\t\tRTE_LOG(ERR, PMD, \"Can't get irq status (err %d)\", ret);\n+\t\tclear = 0xffffffff;\n+\t\tgoto out;\n+\t}\n+\n+\tif (status & DPNI_IRQ_EVENT_LINK_CHANGED) {\n+\t\tclear = DPNI_IRQ_EVENT_LINK_CHANGED;\n+\t\tdpaa2_dev_link_update(dev, 0);\n+\t\t/* calling all the apps registered for link status event */\n+\t\t_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,\n+\t\t\t\t\t NULL, NULL);\n+\t}\n+out:\n+\tret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,\n+\t\t\t\t irq_index, clear);\n+\tif (unlikely(ret))\n+\t\tRTE_LOG(ERR, PMD, \"Can't clear irq status (err %d)\", ret);\n+}\n+\n+static int\n+dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)\n+{\n+\tint err = 0;\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n+\tint irq_index = DPNI_IRQ_INDEX;\n+\tunsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\terr = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,\n+\t\t\t\tirq_index, mask);\n+\tif (err < 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Error: dpni_set_irq_mask():%d (%s)\", err,\n+\t\t\t strerror(-err));\n+\t\treturn err;\n+\t}\n+\n+\terr = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,\n+\t\t\t\t irq_index, enable);\n+\tif (err < 0)\n+\t\tPMD_INIT_LOG(ERR, \"Error: dpni_set_irq_enable():%d (%s)\", err,\n+\t\t\t strerror(-err));\n+\n+\treturn err;\n+}\n+\n static int\n dpaa2_dev_start(struct rte_eth_dev *dev)\n {\n+\tstruct rte_device *rdev = dev->device;\n+\tstruct rte_dpaa2_device *dpaa2_dev;\n \tstruct rte_eth_dev_data *data = dev->data;\n \tstruct dpaa2_dev_priv *priv = data->dev_private;\n \tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n@@ -568,6 +652,10 @@ dpaa2_dev_start(struct rte_eth_dev *dev)\n \tstruct dpni_queue_id qid;\n \tstruct dpaa2_queue *dpaa2_q;\n \tint ret, i;\n+\tstruct rte_intr_handle *intr_handle;\n+\n+\tdpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);\n+\tintr_handle = &dpaa2_dev->intr_handle;\n \n \tPMD_INIT_FUNC_TRACE();\n \n@@ -647,6 +735,24 @@ dpaa2_dev_start(struct rte_eth_dev *dev)\n \tif (priv->max_vlan_filters)\n \t\tdpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);\n \n+\t/* if the interrupts were configured on this devices*/\n+\tif (intr_handle && (intr_handle->fd) &&\n+\t (dev->data->dev_conf.intr_conf.lsc != 0)) {\n+\t\t/* Registering LSC interrupt handler */\n+\t\trte_intr_callback_register(intr_handle,\n+\t\t\t\t\t dpaa2_interrupt_handler,\n+\t\t\t\t\t (void *)dev);\n+\n+\t\t/* enable vfio intr/eventfd mapping\n+\t\t * Interrupt index 0 is required, so we can not use\n+\t\t * rte_intr_enable.\n+\t\t */\n+\t\trte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);\n+\n+\t\t/* enable dpni_irqs */\n+\t\tdpaa2_eth_setup_irqs(dev, 1);\n+\t}\n+\n \treturn 0;\n }\n \n@@ -661,9 +767,25 @@ dpaa2_dev_stop(struct rte_eth_dev *dev)\n \tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n \tint ret;\n \tstruct rte_eth_link link;\n+\tstruct rte_intr_handle *intr_handle = dev->intr_handle;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\t/* reset interrupt callback */\n+\tif (intr_handle && (intr_handle->fd) &&\n+\t (dev->data->dev_conf.intr_conf.lsc != 0)) {\n+\t\t/*disable dpni irqs */\n+\t\tdpaa2_eth_setup_irqs(dev, 0);\n+\n+\t\t/* disable vfio intr before callback unregister */\n+\t\trte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);\n+\n+\t\t/* Unregistering LSC interrupt handler */\n+\t\trte_intr_callback_unregister(intr_handle,\n+\t\t\t\t\t dpaa2_interrupt_handler,\n+\t\t\t\t\t (void *)dev);\n+\t}\n+\n \tdpaa2_dev_set_link_down(dev);\n \n \tret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);\n@@ -1458,6 +1580,7 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)\n \t}\n \n \teth_dev->dev_ops = &dpaa2_ethdev_ops;\n+\teth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;\n \n \teth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;\n \teth_dev->tx_pkt_burst = dpaa2_dev_tx;\ndiff --git a/drivers/net/dpaa2/mc/dpni.c b/drivers/net/dpaa2/mc/dpni.c\nindex f95e669..6f671fe 100644\n--- a/drivers/net/dpaa2/mc/dpni.c\n+++ b/drivers/net/dpaa2/mc/dpni.c\n@@ -351,6 +351,239 @@ int dpni_reset(struct fsl_mc_io *mc_io,\n }\n \n /**\n+ * dpni_set_irq_enable() - Set overall interrupt state.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPNI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @en:\t\tInterrupt state: - enable = 1, disable = 0\n+ *\n+ * Allows GPP software to control when interrupts are generated.\n+ * Each interrupt can have up to 32 causes. The enable/disable control's the\n+ * overall interrupt state. if the interrupt is disabled no causes will cause\n+ * an interrupt.\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpni_set_irq_enable(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t irq_index,\n+\t\t\tuint8_t en)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tstruct dpni_cmd_set_irq_enable *cmd_params;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ_ENABLE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tcmd_params = (struct dpni_cmd_set_irq_enable *)cmd.params;\n+\tdpni_set_field(cmd_params->enable, ENABLE, en);\n+\tcmd_params->irq_index = irq_index;\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+/**\n+ * dpni_get_irq_enable() - Get overall interrupt state\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPNI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @en:\t\tReturned interrupt state - enable = 1, disable = 0\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpni_get_irq_enable(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t irq_index,\n+\t\t\tuint8_t *en)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tstruct dpni_cmd_get_irq_enable *cmd_params;\n+\tstruct dpni_rsp_get_irq_enable *rsp_params;\n+\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_ENABLE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tcmd_params = (struct dpni_cmd_get_irq_enable *)cmd.params;\n+\tcmd_params->irq_index = irq_index;\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\trsp_params = (struct dpni_rsp_get_irq_enable *)cmd.params;\n+\t*en = dpni_get_field(rsp_params->enabled, ENABLE);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dpni_set_irq_mask() - Set interrupt mask.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPNI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @mask:\tEvent mask to trigger interrupt;\n+ *\t\teach bit:\n+ *\t\t\t0 = ignore event\n+ *\t\t\t1 = consider event for asserting IRQ\n+ *\n+ * Every interrupt can have up to 32 causes and the interrupt model supports\n+ * masking/unmasking each cause independently\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpni_set_irq_mask(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token,\n+\t\t uint8_t irq_index,\n+\t\t uint32_t mask)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tstruct dpni_cmd_set_irq_mask *cmd_params;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ_MASK,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tcmd_params = (struct dpni_cmd_set_irq_mask *)cmd.params;\n+\tcmd_params->mask = cpu_to_le32(mask);\n+\tcmd_params->irq_index = irq_index;\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+/**\n+ * dpni_get_irq_mask() - Get interrupt mask.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPNI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @mask:\tReturned event mask to trigger interrupt\n+ *\n+ * Every interrupt can have up to 32 causes and the interrupt model supports\n+ * masking/unmasking each cause independently\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpni_get_irq_mask(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token,\n+\t\t uint8_t irq_index,\n+\t\t uint32_t *mask)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tstruct dpni_cmd_get_irq_mask *cmd_params;\n+\tstruct dpni_rsp_get_irq_mask *rsp_params;\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_MASK,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tcmd_params = (struct dpni_cmd_get_irq_mask *)cmd.params;\n+\tcmd_params->irq_index = irq_index;\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\trsp_params = (struct dpni_rsp_get_irq_mask *)cmd.params;\n+\t*mask = le32_to_cpu(rsp_params->mask);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dpni_get_irq_status() - Get the current status of any pending interrupts.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPNI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @status:\tReturned interrupts status - one bit per cause:\n+ *\t\t\t0 = no interrupt pending\n+ *\t\t\t1 = interrupt pending\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpni_get_irq_status(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t irq_index,\n+\t\t\tuint32_t *status)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tstruct dpni_cmd_get_irq_status *cmd_params;\n+\tstruct dpni_rsp_get_irq_status *rsp_params;\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_STATUS,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tcmd_params = (struct dpni_cmd_get_irq_status *)cmd.params;\n+\tcmd_params->status = cpu_to_le32(*status);\n+\tcmd_params->irq_index = irq_index;\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\trsp_params = (struct dpni_rsp_get_irq_status *)cmd.params;\n+\t*status = le32_to_cpu(rsp_params->status);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dpni_clear_irq_status() - Clear a pending interrupt's status\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPNI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @status:\tbits to clear (W1C) - one bit per cause:\n+ *\t\t\t0 = don't change\n+ *\t\t\t1 = clear status bit\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpni_clear_irq_status(struct fsl_mc_io *mc_io,\n+\t\t\t uint32_t cmd_flags,\n+\t\t\t uint16_t token,\n+\t\t\t uint8_t irq_index,\n+\t\t\t uint32_t status)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tstruct dpni_cmd_clear_irq_status *cmd_params;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPNI_CMDID_CLEAR_IRQ_STATUS,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tcmd_params = (struct dpni_cmd_clear_irq_status *)cmd.params;\n+\tcmd_params->irq_index = irq_index;\n+\tcmd_params->status = cpu_to_le32(status);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+/**\n * dpni_get_attributes() - Retrieve DPNI attributes.\n * @mc_io:\tPointer to MC portal's I/O object\n * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\ndiff --git a/drivers/net/dpaa2/mc/fsl_dpni.h b/drivers/net/dpaa2/mc/fsl_dpni.h\nindex 092d3b3..5227ea1 100644\n--- a/drivers/net/dpaa2/mc/fsl_dpni.h\n+++ b/drivers/net/dpaa2/mc/fsl_dpni.h\n@@ -247,6 +247,55 @@ int dpni_reset(struct fsl_mc_io *mc_io,\n \t uint16_t token);\n \n /**\n+ * DPNI IRQ Index and Events\n+ */\n+\n+/**\n+ * IRQ index\n+ */\n+#define DPNI_IRQ_INDEX\t\t\t\t0\n+/**\n+ * IRQ event - indicates a change in link state\n+ */\n+#define DPNI_IRQ_EVENT_LINK_CHANGED\t\t0x00000001\n+\n+int dpni_set_irq_enable(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t irq_index,\n+\t\t\tuint8_t en);\n+\n+int dpni_get_irq_enable(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t irq_index,\n+\t\t\tuint8_t *en);\n+\n+int dpni_set_irq_mask(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token,\n+\t\t uint8_t irq_index,\n+\t\t uint32_t mask);\n+\n+int dpni_get_irq_mask(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token,\n+\t\t uint8_t irq_index,\n+\t\t uint32_t *mask);\n+\n+int dpni_get_irq_status(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t irq_index,\n+\t\t\tuint32_t *status);\n+\n+int dpni_clear_irq_status(struct fsl_mc_io *mc_io,\n+\t\t\t uint32_t cmd_flags,\n+\t\t\t uint16_t token,\n+\t\t\t uint8_t irq_index,\n+\t\t\t uint32_t status);\n+\n+/**\n * struct dpni_attr - Structure representing DPNI attributes\n * @options: Any combination of the following options:\n *\t\tDPNI_OPT_TX_FRM_RELEASE\ndiff --git a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h\nindex 81226aa..1a48332 100644\n--- a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h\n+++ b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h\n@@ -64,6 +64,13 @@\n #define DPNI_CMDID_RESET\t\t\tDPNI_CMD(0x005)\n #define DPNI_CMDID_IS_ENABLED\t\t\tDPNI_CMD(0x006)\n \n+#define DPNI_CMDID_SET_IRQ_ENABLE\t\tDPNI_CMD(0x012)\n+#define DPNI_CMDID_GET_IRQ_ENABLE\t\tDPNI_CMD(0x013)\n+#define DPNI_CMDID_SET_IRQ_MASK\t\t\tDPNI_CMD(0x014)\n+#define DPNI_CMDID_GET_IRQ_MASK\t\t\tDPNI_CMD(0x015)\n+#define DPNI_CMDID_GET_IRQ_STATUS\t\tDPNI_CMD(0x016)\n+#define DPNI_CMDID_CLEAR_IRQ_STATUS\t\tDPNI_CMD(0x017)\n+\n #define DPNI_CMDID_SET_POOLS\t\t\tDPNI_CMD_V2(0x200)\n #define DPNI_CMDID_SET_ERRORS_BEHAVIOR\t\tDPNI_CMD(0x20B)\n \n@@ -169,6 +176,49 @@ struct dpni_rsp_is_enabled {\n \tuint8_t enabled;\n };\n \n+struct dpni_cmd_set_irq_enable {\n+\tuint8_t enable;\n+\tuint8_t pad[3];\n+\tuint8_t irq_index;\n+};\n+\n+struct dpni_cmd_get_irq_enable {\n+\tuint32_t pad;\n+\tuint8_t irq_index;\n+};\n+\n+struct dpni_rsp_get_irq_enable {\n+\tuint8_t enabled;\n+};\n+\n+struct dpni_cmd_set_irq_mask {\n+\tuint32_t mask;\n+\tuint8_t irq_index;\n+};\n+\n+struct dpni_cmd_get_irq_mask {\n+\tuint32_t pad;\n+\tuint8_t irq_index;\n+};\n+\n+struct dpni_rsp_get_irq_mask {\n+\tuint32_t mask;\n+};\n+\n+struct dpni_cmd_get_irq_status {\n+\tuint32_t status;\n+\tuint8_t irq_index;\n+};\n+\n+struct dpni_rsp_get_irq_status {\n+\tuint32_t status;\n+};\n+\n+struct dpni_cmd_clear_irq_status {\n+\tuint32_t status;\n+\tuint8_t irq_index;\n+};\n+\n struct dpni_rsp_get_attr {\n \t/* response word 0 */\n \tuint32_t options;\n", "prefixes": [ "dpdk-dev", "17/27" ] }