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GET /api/patches/27719/?format=api
{ "id": 27719, "url": "http://patches.dpdk.org/api/patches/27719/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1503409570-9946-3-git-send-email-rasland@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1503409570-9946-3-git-send-email-rasland@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1503409570-9946-3-git-send-email-rasland@mellanox.com", "date": "2017-08-22T13:46:10", "name": "[dpdk-dev,3/3] net/mlx5: add hardware timestamp", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e59f7f4205583df3414e2788b71905503cb40252", "submitter": { "id": 513, "url": "http://patches.dpdk.org/api/people/513/?format=api", "name": "Raslan Darawsheh", "email": "rasland@mellanox.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1503409570-9946-3-git-send-email-rasland@mellanox.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/27719/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/27719/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id CC9B17D5E;\n\tTue, 22 Aug 2017 15:46:31 +0200 (CEST)", "from EUR01-VE1-obe.outbound.protection.outlook.com\n\t(mail-ve1eur01on0048.outbound.protection.outlook.com [104.47.1.48])\n\tby dpdk.org (Postfix) with ESMTP id A2B217D57\n\tfor <dev@dpdk.org>; Tue, 22 Aug 2017 15:46:29 +0200 (CEST)", "from mellanox.com (37.142.13.130) by\n\tAM2PR05MB1218.eurprd05.prod.outlook.com (2a01:111:e400:8450::16) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1362.18;\n\tTue, 22 Aug 2017 13:46:27 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com;\n\ts=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=OiGd9R1pfDO+9tEYcWeTpLuPQoQ4bZk4x6eLHDMoOa8=;\n\tb=w/QjBw2PCzSBHXb33hGrR3OQAwkXE8lEpaCbf74SDEliy8pCoedC+vMuOuR8RRPaCN1SIButEI7xs4BbXznMYgJ8udtMudi+VFqN8B9QrEXoswgXqoUKduaLOy/qB1rI3hxVB3YK68+MnB/Z8eQoUvWuowHRj0LzpbOS5mlMPcg=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=rasland@mellanox.com; ", "From": "Raslan Darawsheh <rasland@mellanox.com>", "To": "thomas@monjalon.net, jingjing.wu@intel.com, dev@dpdk.org,\n\tnelio.laranjeiro@6wind.com, adrien.mazarguil@6wind.com", "Date": "Tue, 22 Aug 2017 16:46:10 +0300", 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"X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(7370300001)(4630300001)(6009001)(199003)(189002)(68736007)(2950100002)(110136004)(21086003)(6116002)(47776003)(69596002)(7350300001)(478600001)(2906002)(6666003)(189998001)(48376002)(3846002)(36756003)(86362001)(55016002)(66066001)(50986999)(53936002)(76176999)(33026002)(5660300001)(33646002)(42186005)(50466002)(305945005)(7736002)(8676002)(81156014)(97736004)(106356001)(25786009)(101416001)(81166006)(575784001)(105586002)(5003940100001)(50226002)(309714004);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM2PR05MB1218; H:mellanox.com; FPR:;\n\tSPF:None; \n\tPTR:InfoNoRecords; A:1; MX:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: mellanox.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "Mellanox.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Aug 2017 13:46:27.0704\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM2PR05MB1218", "Subject": "[dpdk-dev] [PATCH 3/3] net/mlx5: add hardware timestamp", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Expose a new capapilty of Rx hw timestamp and\nadded new device args to enable it hw_timestamp.\nIt will add the raw hw timestamp into the packets.\n\nIts expected that it will lower down the performance since using it\nwill disable the cqe comprission, and will add extra checkes in\nthe vec rx path.\n\nSigned-off-by: Raslan Darawsheh <rasland@mellanox.com>\n---\n drivers/net/mlx5/mlx5.c | 23 +++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_ethdev.c | 3 ++-\n drivers/net/mlx5/mlx5_rxq.c | 3 +++\n drivers/net/mlx5/mlx5_rxtx.c | 5 +++++\n drivers/net/mlx5/mlx5_rxtx.h | 1 +\n drivers/net/mlx5/mlx5_rxtx_vec_sse.c | 14 ++++++++++++++\n 7 files changed, 49 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex b7e5046..4b3a3ab 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -94,6 +94,9 @@\n /* Device parameter to enable hardware TSO offload. */\n #define MLX5_TSO \"tso\"\n \n+/* Device parameter to enable hardware timestamp offload. */\n+#define MLX5_RX_TIMESTAMP \"rx_timestamp\"\n+\n /* Device parameter to enable hardware Tx vector. */\n #define MLX5_TX_VEC_EN \"tx_vec_en\"\n \n@@ -113,6 +116,7 @@ struct mlx5_args {\n \tint tso;\n \tint tx_vec_en;\n \tint rx_vec_en;\n+\tint hw_timestamp;\n };\n /**\n * Retrieve integer value from environment variable.\n@@ -336,6 +340,8 @@ mlx5_args_check(const char *key, const char *val, void *opaque)\n \t\targs->tx_vec_en = !!tmp;\n \t} else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {\n \t\targs->rx_vec_en = !!tmp;\n+\t} else if (strcmp(MLX5_RX_TIMESTAMP, key) == 0) {\n+\t\targs->hw_timestamp = !!tmp;\n \t} else {\n \t\tWARN(\"%s: unknown parameter\", key);\n \t\treturn -EINVAL;\n@@ -367,6 +373,7 @@ mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs)\n \t\tMLX5_TSO,\n \t\tMLX5_TX_VEC_EN,\n \t\tMLX5_RX_VEC_EN,\n+\t\tMLX5_RX_TIMESTAMP,\n \t\tNULL,\n \t};\n \tstruct rte_kvargs *kvlist;\n@@ -426,6 +433,8 @@ mlx5_args_assign(struct priv *priv, struct mlx5_args *args)\n \t\tpriv->tx_vec_en = args->tx_vec_en;\n \tif (args->rx_vec_en != MLX5_ARG_UNSET)\n \t\tpriv->rx_vec_en = args->rx_vec_en;\n+\tif (args->hw_timestamp != MLX5_ARG_UNSET)\n+\t\tpriv->hw_timestamp = args->hw_timestamp;\n }\n \n /**\n@@ -573,6 +582,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\t\t.tso = MLX5_ARG_UNSET,\n \t\t\t.tx_vec_en = MLX5_ARG_UNSET,\n \t\t\t.rx_vec_en = MLX5_ARG_UNSET,\n+\t\t\t.hw_timestamp = MLX5_ARG_UNSET,\n \t\t};\n \n \t\texp_device_attr.comp_mask =\n@@ -581,6 +591,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\t\tIBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS |\n \t\t\tIBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN |\n \t\t\tIBV_EXP_DEVICE_ATTR_TSO_CAPS |\n+\t\t\tIBV_EXP_DEVICE_ATTR_WITH_TIMESTAMP_MASK |\n \t\t\t0;\n \n \t\tDEBUG(\"using port %u (%08\" PRIx32 \")\", port, test);\n@@ -662,6 +673,18 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\t\t\t\t IBV_EXP_DEVICE_VXLAN_SUPPORT);\n \t\tDEBUG(\"L2 tunnel checksum offloads are %ssupported\",\n \t\t (priv->hw_csum_l2tun ? \"\" : \"not \"));\n+\t\tif (priv->hw_timestamp) {\n+\t\t\tpriv->hw_timestamp =\n+\t\t\t\t(exp_device_attr.comp_mask |\n+\t\t\t\t IBV_EXP_DEVICE_ATTR_WITH_TIMESTAMP_MASK);\n+\t\t\tDEBUG(\"Timestamping offload is %ssupported\",\n+\t\t\t (priv->hw_timestamp ? \"\" : \"not \"));\n+\t\t\tpriv->cqe_comp = (priv->hw_timestamp ?\n+\t\t\t\t\t 0 : priv->cqe_comp);\n+\t\t\tDEBUG(\"%s\",\n+\t\t\t (priv->hw_timestamp ?\n+\t\t\t \"cqe compression is disabled\" : \"\"));\n+\t\t}\n \n \t\tpriv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size;\n \t\t/* Remove this check once DPDK supports larger/variable\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 43c5384..4d19351 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -120,6 +120,7 @@ struct priv {\n \tunsigned int allmulti_req:1; /* All multicast mode requested. */\n \tunsigned int hw_csum:1; /* Checksum offload is supported. */\n \tunsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */\n+\tunsigned int hw_timestamp:1; /* rx timestamp offload is supported. */\n \tunsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */\n \tunsigned int hw_fcs_strip:1; /* FCS stripping is supported. */\n \tunsigned int hw_padding:1; /* End alignment padding is supported. */\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex b0eb3cd..1942de7 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -686,7 +686,8 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n \t\t DEV_RX_OFFLOAD_UDP_CKSUM |\n \t\t DEV_RX_OFFLOAD_TCP_CKSUM) :\n \t\t 0) |\n-\t\t(priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0);\n+\t\t(priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0) |\n+\t\t(priv->hw_timestamp ? DEV_RX_OFFLOAD_TIMESTAMP : 0);\n \tif (!priv->mps)\n \t\tinfo->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;\n \tif (priv->hw_csum)\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 74387a7..c8ccde2 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -929,6 +929,7 @@ rxq_ctrl_setup(struct rte_eth_dev *dev, struct rxq_ctrl *rxq_ctrl,\n \tif (priv->hw_csum_l2tun)\n \t\ttmpl.rxq.csum_l2tun =\n \t\t\t!!dev->data->dev_conf.rxmode.hw_ip_checksum;\n+\ttmpl.rxq.timestamp = priv->hw_timestamp;\n \t/* Use the entire RX mempool as the memory region. */\n \ttmpl.mr = mlx5_mp2mr(priv->pd, mp);\n \tif (tmpl.mr == NULL) {\n@@ -950,6 +951,8 @@ rxq_ctrl_setup(struct rte_eth_dev *dev, struct rxq_ctrl *rxq_ctrl,\n \tattr.cq = (struct ibv_exp_cq_init_attr){\n \t\t.comp_mask = 0,\n \t};\n+\tif (priv->hw_timestamp)\n+\t\tattr.cq.flags |= IBV_EXP_CQ_TIMESTAMP;\n \tif (priv->cqe_comp) {\n \t\tattr.cq.comp_mask |= IBV_EXP_CQ_INIT_ATTR_FLAGS;\n \t\tattr.cq.flags |= IBV_EXP_CQ_COMPRESSED_CQE;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex b07bcd1..47344f2 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -1865,6 +1865,11 @@ mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\t\t\tPKT_RX_VLAN_STRIPPED;\n \t\t\t\tpkt->vlan_tci = ntohs(cqe->vlan_info);\n \t\t\t}\n+\t\t\tif (rxq->timestamp) {\n+\t\t\t\tpkt->timestamp =\n+\t\t\t\t\trte_be_to_cpu_64(cqe->timestamp);\n+\t\t\t\tpkt->ol_flags |= PKT_RX_TIMESTAMP;\n+\t\t\t}\n \t\t\tif (rxq->crc_present)\n \t\t\t\tlen -= ETHER_CRC_LEN;\n \t\t\tPKT_LEN(pkt) = len;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 7de1d10..20c0f87 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -107,6 +107,7 @@ struct rxq_zip {\n struct rxq {\n \tunsigned int csum:1; /* Enable checksum offloading. */\n \tunsigned int csum_l2tun:1; /* Same for L2 tunnels. */\n+\tunsigned int timestamp:1; /* Enable timestamp offloading. */\n \tunsigned int vlan_strip:1; /* Enable VLAN stripping. */\n \tunsigned int crc_present:1; /* CRC must be subtracted. */\n \tunsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.c b/drivers/net/mlx5/mlx5_rxtx_vec_sse.c\nindex 8560f74..9f1fd87 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.c\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.c\n@@ -1214,6 +1214,20 @@ rxq_burst_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\trxq->pending_err |= !!_mm_cvtsi128_si64(opcode);\n \t\t/* D.5 fill in mbuf - rearm_data and packet_type. */\n \t\trxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);\n+\t\tif (rxq->timestamp) {\n+\t\t\tpkts[pos]->timestamp =\n+\t\t\t\trte_be_to_cpu_64(cq[pos].timestamp);\n+\t\t\tpkts[pos + 1]->timestamp =\n+\t\t\t\trte_be_to_cpu_64(cq[pos + 1].timestamp);\n+\t\t\tpkts[pos + 2]->timestamp =\n+\t\t\t\trte_be_to_cpu_64(cq[pos + 2].timestamp);\n+\t\t\tpkts[pos + 3]->timestamp =\n+\t\t\t\trte_be_to_cpu_64(cq[pos + 3].timestamp);\n+\t\t\tpkts[pos]->ol_flags |= PKT_RX_TIMESTAMP;\n+\t\t\tpkts[pos + 1]->ol_flags |= PKT_RX_TIMESTAMP;\n+\t\t\tpkts[pos + 2]->ol_flags |= PKT_RX_TIMESTAMP;\n+\t\t\tpkts[pos + 3]->ol_flags |= PKT_RX_TIMESTAMP;\n+\t\t}\n #ifdef MLX5_PMD_SOFT_COUNTERS\n \t\t/* Add up received bytes count. */\n \t\tbyte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);\n", "prefixes": [ "dpdk-dev", "3/3" ] }