get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/27134/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 27134,
    "url": "http://patches.dpdk.org/api/patches/27134/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1500891015-21625-1-git-send-email-rasesh.mody@cavium.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1500891015-21625-1-git-send-email-rasesh.mody@cavium.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1500891015-21625-1-git-send-email-rasesh.mody@cavium.com",
    "date": "2017-07-24T10:10:09",
    "name": "[dpdk-dev,INTERNAL,REVIEW,1/7] net/qede/base: fix recovery from previous ungraceful exit",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c8ad682412aee8cf4277815743d9684c71fe87f4",
    "submitter": {
        "id": 569,
        "url": "http://patches.dpdk.org/api/people/569/?format=api",
        "name": "Mody, Rasesh",
        "email": "rasesh.mody@cavium.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1500891015-21625-1-git-send-email-rasesh.mody@cavium.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/27134/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/27134/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 469E27CBB;\n\tMon, 24 Jul 2017 12:10:28 +0200 (CEST)",
            "from NAM01-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam01on0047.outbound.protection.outlook.com [104.47.34.47])\n\tby dpdk.org (Postfix) with ESMTP id 74B817CAC\n\tfor <dev@dpdk.org>; Mon, 24 Jul 2017 12:10:26 +0200 (CEST)",
            "from CO2PR07CA0061.namprd07.prod.outlook.com (10.174.192.29) by\n\tBY2PR07MB2438.namprd07.prod.outlook.com (10.166.115.18) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n\t15.1.1282.10; Mon, 24 Jul 2017 10:10:23 +0000",
            "from BY2FFO11FD014.protection.gbl (2a01:111:f400:7c0c::157) by\n\tCO2PR07CA0061.outlook.office365.com (2603:10b6:100::29) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n\t15.1.1282.10 via Frontend Transport; Mon, 24 Jul 2017 10:10:23 +0000",
            "from CAEXCH02.caveonetworks.com (50.232.66.26) by\n\tBY2FFO11FD014.mail.protection.outlook.com (10.1.14.76) with Microsoft\n\tSMTP Server (version=TLS1_0,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA_P384) id\n\t15.1.1240.9 via Frontend Transport; Mon, 24 Jul 2017 10:10:22 +0000",
            "from avsmtprelay01.qlc.com (10.1.112.194) by\n\tCAEXCH02.caveonetworks.com (10.17.4.29) with Microsoft SMTP Server id\n\t14.2.347.0; Mon, 24 Jul 2017 03:10:22 -0700",
            "from avluser05.qlc.com (avluser05.qlc.com [10.1.113.115])\tby\n\tavsmtprelay01.qlc.com (Postfix) with ESMTP id 469F58BF705FD;\n\tMon, 24 Jul 2017 03:10:22 -0700 (PDT)",
            "(from rmody@localhost)\tby avluser05.qlc.com (8.14.4/8.14.4/Submit)\n\tid v6OAAMmc021669;\tMon, 24 Jul 2017 03:10:22 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=robXkuQFr0pgBCTg1823IH8RqzlTi8ea5UjdZuYqJKY=;\n\tb=mCEe69pKfr8tEZGPjYRIsg2Q8N0OiLgbHoW8yOL0Mh+re1voYi5Q0vQQXAbVD52+4bJdrlxuvYNHY7KQdvC8+lAGHcWLw/UjNM9PlXkKn2hL2xWCDDmHc+XaWOtjaFMAZzBTFhRnlrNZwAZJQLvQc5JbWFCqdGOlm9k4QawPtVY=",
        "Authentication-Results": "spf=none (sender IP is 50.232.66.26)\n\tsmtp.mailfrom=cavium.com; dpdk.org; dkim=none (message not signed)\n\theader.d=none; dpdk.org; dmarc=none action=none header.from=cavium.com;",
        "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)",
        "X-Authentication-Warning": "avluser05.qlc.com: rmody set sender to\n\trasesh.mody@cavium.com using -f",
        "From": "Rasesh Mody <rasesh.mody@cavium.com>",
        "To": "<dev@dpdk.org>",
        "CC": "Rasesh Mody <rasesh.mody@cavium.com>, <Dept-EngDPDKDev@cavium.com>",
        "Date": "Mon, 24 Jul 2017 03:10:09 -0700",
        "Message-ID": "<1500891015-21625-1-git-send-email-rasesh.mody@cavium.com>",
        "X-Mailer": "git-send-email 1.7.10.3",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-EOPAttributedMessage": "0",
        "X-Forefront-Antispam-Report": "CIP:50.232.66.26; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(39840400002)(39400400002)(39850400002)(39450400003)(39410400002)(2980300002)(428002)(199003)(189002)(81166006)(6666003)(50466002)(4720700003)(69596002)(72206003)(54906002)(50226002)(5660300001)(6916009)(36756003)(87636003)(8936002)(2906002)(478600001)(4326008)(626005)(42186005)(48376002)(86362001)(8676002)(47776003)(106466001)(356003)(305945005)(101416001)(189998001)(105586002)(5003940100001)(107886003)(110136004)(81156014)(38730400002)(2351001)(33646002)(50986999)(217873001);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BY2PR07MB2438;\n\tH:CAEXCH02.caveonetworks.com; \n\tFPR:; SPF:None; PTR:50-232-66-26-static.hfc.comcastbusiness.net; A:1;\n\tMX:1; LANG:en; ",
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        "Subject": "[dpdk-dev] [INTERNAL REVIEW 1/7] net/qede/base: fix recovery from\n\tprevious ungraceful exit",
        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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    },
    "content": "This patch modifies the recovery flow to allow ongoing PCIe\ntransactions to be completed. To achieve this, the load sequence is\nchanged such that the \"final_cleanup\" notification is sent while the\nFID_enable is cleared.\nThis change ensures that the chip cleanup actions takes place from\nprevious driver instance if needed.\n\nFixes: ec94dbc57362 (\"qede: add base driver\")\n\nSigned-off-by: Rasesh Mody <rasesh.mody@cavium.com>\n---\n drivers/net/qede/base/ecore_dev.c     |  121 +++++++++++++++------------\n drivers/net/qede/base/ecore_dev_api.h |   12 +++\n drivers/net/qede/base/ecore_int.c     |  144 ++++++++++++++++-----------------\n drivers/net/qede/base/ecore_int.h     |    3 +\n drivers/net/qede/base/ecore_mcp.c     |   45 +++++++++++\n drivers/net/qede/base/ecore_mcp.h     |   11 +++\n drivers/net/qede/base/ecore_mcp_api.h |   11 +++\n 7 files changed, 224 insertions(+), 123 deletions(-)",
    "diff": "diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex 4cfa668..65b89b8 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -1080,7 +1080,7 @@ enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,\n \t}\n \n \tDP_VERBOSE(p_hwfn, ECORE_MSG_IOV,\n-\t\t   \"Sending final cleanup for PFVF[%d] [Command %08x\\n]\",\n+\t\t   \"Sending final cleanup for PFVF[%d] [Command %08x]\\n\",\n \t\t   id, command);\n \n \tecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);\n@@ -1776,13 +1776,6 @@ static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,\n \t/* perform debug configuration when chip is out of reset */\n \tOSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);\n \n-\t/* Cleanup chip from previous driver if such remains exist */\n-\trc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);\n-\tif (rc != ECORE_SUCCESS) {\n-\t\tecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);\n-\t\treturn rc;\n-\t}\n-\n \t/* PF Init sequence */\n \trc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);\n \tif (rc)\n@@ -1866,17 +1859,17 @@ static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,\n \treturn rc;\n }\n \n-static enum _ecore_status_t\n-ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,\n-\t\t      struct ecore_ptt *p_ptt, u8 enable)\n+enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\t  struct ecore_ptt *p_ptt,\n+\t\t\t\t\t\t  bool b_enable)\n {\n-\tu32 delay_idx = 0, val, set_val = enable ? 1 : 0;\n+\tu32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;\n \n-\t/* Change PF in PXP */\n+\t/* Configure the PF's internal FID_enable for master transactions */\n \tecore_wr(p_hwfn, p_ptt,\n \t\t PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);\n \n-\t/* wait until value is set - try for 1 second every 50us */\n+\t/* Wait until value is set - try for 1 second every 50us */\n \tfor (delay_idx = 0; delay_idx < 20000; delay_idx++) {\n \t\tval = ecore_rd(p_hwfn, p_ptt,\n \t\t\t       PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);\n@@ -1918,14 +1911,21 @@ enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,\n \treturn ECORE_SUCCESS;\n }\n \n+static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t     struct ecore_ptt *p_ptt)\n+{\n+\tecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,\n+\t\t 1 << p_hwfn->abs_pf_id);\n+}\n+\n enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t\t\t\t   struct ecore_hw_init_params *p_params)\n {\n \tstruct ecore_load_req_params load_req_params;\n-\tu32 load_code, param, drv_mb_param;\n+\tu32 load_code, resp, param, drv_mb_param;\n \tbool b_default_mtu = true;\n \tstruct ecore_hwfn *p_hwfn;\n-\tenum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n \tint i;\n \n \tif ((p_params->int_mode == ECORE_INT_MODE_MSI) &&\n@@ -1942,7 +1942,7 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t}\n \n \tfor_each_hwfn(p_dev, i) {\n-\t\tstruct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];\n+\t\tp_hwfn = &p_dev->hwfns[i];\n \n \t\t/* If management didn't provide a default, set one of our own */\n \t\tif (!p_hwfn->hw_info.mtu) {\n@@ -1955,11 +1955,6 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t\t\tcontinue;\n \t\t}\n \n-\t\t/* Enable DMAE in PXP */\n-\t\trc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);\n-\t\tif (rc != ECORE_SUCCESS)\n-\t\t\treturn rc;\n-\n \t\trc = ecore_calc_hw_mode(p_hwfn);\n \t\tif (rc != ECORE_SUCCESS)\n \t\t\treturn rc;\n@@ -2009,6 +2004,30 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t\t\tqm_lock_init = true;\n \t\t}\n \n+\t\t/* Clean up chip from previous driver if such remains exist.\n+\t\t * This is not needed when the PF is the first one on the\n+\t\t * engine, since afterwards we are going to init the FW.\n+\t\t */\n+\t\tif (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {\n+\t\t\trc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t\t\t p_hwfn->rel_pf_id, false);\n+\t\t\tif (rc != ECORE_SUCCESS) {\n+\t\t\t\tecore_hw_err_notify(p_hwfn,\n+\t\t\t\t\t\t    ECORE_HW_ERR_RAMROD_FAIL);\n+\t\t\t\tgoto load_err;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Log and clean previous pglue_b errors if such exist */\n+\t\tecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);\n+\t\tecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);\n+\n+\t\t/* Enable the PF's internal FID_enable in the PXP */\n+\t\trc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t\t\t  true);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\tgoto load_err;\n+\n \t\tswitch (load_code) {\n \t\tcase FW_MSG_CODE_DRV_LOAD_ENGINE:\n \t\t\trc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,\n@@ -2037,35 +2056,28 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t\t\tbreak;\n \t\t}\n \n-\t\tif (rc != ECORE_SUCCESS)\n+\t\tif (rc != ECORE_SUCCESS) {\n \t\t\tDP_NOTICE(p_hwfn, true,\n \t\t\t\t  \"init phase failed for loadcode 0x%x (rc %d)\\n\",\n \t\t\t\t  load_code, rc);\n+\t\t\tgoto load_err;\n+\t\t}\n \n-\t\t/* ACK mfw regardless of success or failure of initialization */\n-\t\tmfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t\t       DRV_MSG_CODE_LOAD_DONE,\n-\t\t\t\t       0, &load_code, &param);\n+\t\trc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);\n \t\tif (rc != ECORE_SUCCESS)\n \t\t\treturn rc;\n \n-\t\tif (mfw_rc != ECORE_SUCCESS) {\n-\t\t\tDP_NOTICE(p_hwfn, true,\n-\t\t\t\t  \"Failed sending a LOAD_DONE command\\n\");\n-\t\t\treturn mfw_rc;\n-\t\t}\n-\n \t\t/* send DCBX attention request command */\n \t\tDP_VERBOSE(p_hwfn, ECORE_MSG_DCB,\n \t\t\t   \"sending phony dcbx set command to trigger DCBx attention handling\\n\");\n-\t\tmfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t\t       DRV_MSG_CODE_SET_DCBX,\n-\t\t\t\t       1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,\n-\t\t\t\t       &load_code, &param);\n-\t\tif (mfw_rc != ECORE_SUCCESS) {\n+\t\trc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t   DRV_MSG_CODE_SET_DCBX,\n+\t\t\t\t   1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, &resp,\n+\t\t\t\t   &param);\n+\t\tif (rc != ECORE_SUCCESS) {\n \t\t\tDP_NOTICE(p_hwfn, true,\n \t\t\t\t  \"Failed to send DCBX attention request\\n\");\n-\t\t\treturn mfw_rc;\n+\t\t\treturn rc;\n \t\t}\n \n \t\tp_hwfn->hw_init_done = true;\n@@ -2076,7 +2088,7 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t\tdrv_mb_param = STORM_FW_VERSION;\n \t\trc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,\n \t\t\t\t   DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,\n-\t\t\t\t   drv_mb_param, &load_code, &param);\n+\t\t\t\t   drv_mb_param, &resp, &param);\n \t\tif (rc != ECORE_SUCCESS)\n \t\t\tDP_INFO(p_hwfn, \"Failed to update firmware version\\n\");\n \n@@ -2094,6 +2106,14 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t}\n \n \treturn rc;\n+\n+load_err:\n+\t/* The MFW load lock should be released regardless of success or failure\n+\t * of initialization.\n+\t * TODO: replace this with an attempt to send cancel_load.\n+\t */\n+\tecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);\n+\treturn rc;\n }\n \n #define ECORE_HW_STOP_RETRY_LIMIT\t(10)\n@@ -2261,18 +2281,20 @@ enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)\n \t\t}\n \t} /* hwfn loop */\n \n-\tif (IS_PF(p_dev)) {\n+\tif (IS_PF(p_dev) && !p_dev->recov_in_prog) {\n \t\tp_hwfn = ECORE_LEADING_HWFN(p_dev);\n \t\tp_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;\n \n-\t\t/* Disable DMAE in PXP - in CMT, this should only be done for\n-\t\t * first hw-function, and only after all transactions have\n-\t\t * stopped for all active hw-functions.\n-\t\t */\n-\t\trc = ecore_change_pci_hwfn(p_hwfn, p_ptt, false);\n+\t\t /* Clear the PF's internal FID_enable in the PXP.\n+\t\t  * In CMT this should only be done for first hw-function, and\n+\t\t  * only after all transactions have stopped for all active\n+\t\t  * hw-functions.\n+\t\t  */\n+\t\trc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t\t\t  false);\n \t\tif (rc != ECORE_SUCCESS) {\n \t\t\tDP_NOTICE(p_hwfn, true,\n-\t\t\t\t  \"ecore_change_pci_hwfn failed. rc = %d.\\n\",\n+\t\t\t\t  \"ecore_pglueb_set_pfid_enable() failed. rc = %d.\\n\",\n \t\t\t\t  rc);\n \t\t\trc2 = ECORE_UNKNOWN_ERROR;\n \t\t}\n@@ -2370,9 +2392,8 @@ static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)\n \t\t\t PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);\n \t}\n \n-\t/* Clean Previous errors if such exist */\n-\tecore_wr(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);\n+\t/* Clean previous pglue_b errors if such exist */\n+\tecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);\n \n \t/* enable internal target-read */\n \tecore_wr(p_hwfn, p_hwfn->p_main_ptt,\ndiff --git a/drivers/net/qede/base/ecore_dev_api.h b/drivers/net/qede/base/ecore_dev_api.h\nindex 886407b..eea22e0 100644\n--- a/drivers/net/qede/base/ecore_dev_api.h\n+++ b/drivers/net/qede/base/ecore_dev_api.h\n@@ -584,4 +584,16 @@ enum _ecore_status_t\n ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn, u16 rx_coal,\n \t\t\t u16 tx_coal, void *p_handle);\n \n+/**\n+ * @brief ecore_pglueb_set_pfid_enable - Enable or disable PCI BUS MASTER\n+ *\n+ * @param p_hwfn\n+ * @param p_ptt\n+ * @param b_enable - true/false\n+ *\n+ * @return enum _ecore_status_t\n+ */\n+enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\t  struct ecore_ptt *p_ptt,\n+\t\t\t\t\t\t  bool b_enable);\n #endif\ndiff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c\nindex 2afca29..b57c510 100644\n--- a/drivers/net/qede/base/ecore_int.c\n+++ b/drivers/net/qede/base/ecore_int.c\n@@ -284,122 +284,119 @@ static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)\n #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)\n #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)\n #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)\n-static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)\n+\n+enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\t   struct ecore_ptt *p_ptt)\n {\n \tu32 tmp;\n \n-\ttmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n-\t\t       PGLUE_B_REG_TX_ERR_WR_DETAILS2);\n+\ttmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);\n \tif (tmp & ECORE_PGLUE_ATTENTION_VALID) {\n \t\tu32 addr_lo, addr_hi, details;\n \n-\t\taddr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\taddr_lo = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_TX_ERR_WR_ADD_31_0);\n-\t\taddr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\taddr_hi = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_TX_ERR_WR_ADD_63_32);\n-\t\tdetails = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\tdetails = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_TX_ERR_WR_DETAILS);\n \n-\t\tDP_INFO(p_hwfn,\n-\t\t\t\"Illegal write by chip to [%08x:%08x] blocked.\"\n-\t\t\t\"Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\"\n-\t\t\t\" Details2 %08x [Was_error %02x BME deassert %02x\"\n-\t\t\t\" FID_enable deassert %02x]\\n\",\n-\t\t\taddr_hi, addr_lo, details,\n-\t\t\t(u8)((details &\n-\t\t\t      ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>\n-\t\t\t     ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),\n-\t\t\t(u8)((details &\n-\t\t\t      ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>\n-\t\t\t     ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),\n-\t\t\t(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID)\n-\t\t\t     ? 1 : 0), tmp,\n-\t\t\t(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1\n-\t\t\t     : 0),\n-\t\t\t(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 :\n-\t\t\t     0),\n-\t\t\t(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1\n-\t\t\t     : 0));\n+\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t  \"Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\\n\",\n+\t\t\t  addr_hi, addr_lo, details,\n+\t\t\t  (u8)((details &\n+\t\t\t\tECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>\n+\t\t\t       ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),\n+\t\t\t  (u8)((details &\n+\t\t\t\tECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>\n+\t\t\t       ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),\n+\t\t\t  (u8)((details &\n+\t\t\t       ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),\n+\t\t\t  tmp,\n+\t\t\t  (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?\n+\t\t\t\t1 : 0),\n+\t\t\t  (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?\n+\t\t\t\t1 : 0),\n+\t\t\t  (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?\n+\t\t\t\t1 : 0));\n \t}\n \n-\ttmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n-\t\t       PGLUE_B_REG_TX_ERR_RD_DETAILS2);\n+\ttmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);\n \tif (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {\n \t\tu32 addr_lo, addr_hi, details;\n \n-\t\taddr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\taddr_lo = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_TX_ERR_RD_ADD_31_0);\n-\t\taddr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\taddr_hi = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_TX_ERR_RD_ADD_63_32);\n-\t\tdetails = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\tdetails = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_TX_ERR_RD_DETAILS);\n \n-\t\tDP_INFO(p_hwfn,\n-\t\t\t\"Illegal read by chip from [%08x:%08x] blocked.\"\n-\t\t\t\" Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\"\n-\t\t\t\" Details2 %08x [Was_error %02x BME deassert %02x\"\n-\t\t\t\" FID_enable deassert %02x]\\n\",\n-\t\t\taddr_hi, addr_lo, details,\n-\t\t\t(u8)((details &\n-\t\t\t      ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>\n-\t\t\t     ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),\n-\t\t\t(u8)((details &\n-\t\t\t      ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>\n-\t\t\t     ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),\n-\t\t\t(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID)\n-\t\t\t     ? 1 : 0), tmp,\n-\t\t\t(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1\n-\t\t\t     : 0),\n-\t\t\t(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 :\n-\t\t\t     0),\n-\t\t\t(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1\n-\t\t\t     : 0));\n+\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t  \"Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\\n\",\n+\t\t\t  addr_hi, addr_lo, details,\n+\t\t\t  (u8)((details &\n+\t\t\t\tECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>\n+\t\t\t       ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),\n+\t\t\t  (u8)((details &\n+\t\t\t\tECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>\n+\t\t\t       ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),\n+\t\t\t  (u8)((details &\n+\t\t\t       ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),\n+\t\t\t  tmp,\n+\t\t\t  (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?\n+\t\t\t\t1 : 0),\n+\t\t\t  (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?\n+\t\t\t\t1 : 0),\n+\t\t\t  (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?\n+\t\t\t\t1 : 0));\n \t}\n \n-\ttmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n-\t\t       PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);\n+\ttmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);\n \tif (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)\n-\t\tDP_INFO(p_hwfn, \"ICPL error - %08x\\n\", tmp);\n+\t\tDP_NOTICE(p_hwfn, false, \"ICPL erorr - %08x\\n\", tmp);\n \n-\ttmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n-\t\t       PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);\n+\ttmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);\n \tif (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {\n \t\tu32 addr_hi, addr_lo;\n \n-\t\taddr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\taddr_lo = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);\n-\t\taddr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\taddr_hi = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);\n \n-\t\tDP_INFO(p_hwfn, \"ICPL error - %08x [Address %08x:%08x]\\n\",\n-\t\t\ttmp, addr_hi, addr_lo);\n+\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t  \"ICPL erorr - %08x [Address %08x:%08x]\\n\",\n+\t\t\t  tmp, addr_hi, addr_lo);\n \t}\n \n-\ttmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n-\t\t       PGLUE_B_REG_VF_ILT_ERR_DETAILS2);\n+\ttmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);\n \tif (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {\n \t\tu32 addr_hi, addr_lo, details;\n \n-\t\taddr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\taddr_lo = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);\n-\t\taddr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\taddr_hi = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);\n-\t\tdetails = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n+\t\tdetails = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t   PGLUE_B_REG_VF_ILT_ERR_DETAILS);\n \n-\t\tDP_INFO(p_hwfn,\n-\t\t\t\"ILT error - Details %08x Details2 %08x\"\n-\t\t\t\" [Address %08x:%08x]\\n\",\n-\t\t\tdetails, tmp, addr_hi, addr_lo);\n+\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t  \"ILT error - Details %08x Details2 %08x [Address %08x:%08x]\\n\",\n+\t\t\t  details, tmp, addr_hi, addr_lo);\n \t}\n \n \t/* Clear the indications */\n-\tecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,\n-\t\t PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));\n+\tecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));\n \n \treturn ECORE_SUCCESS;\n }\n \n+static enum _ecore_status_t ecore_pglueb_rbc_attn_cb(struct ecore_hwfn *p_hwfn)\n+{\n+\treturn ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt);\n+}\n+\n static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)\n {\n \tDP_NOTICE(p_hwfn, false, \"FW assertion!\\n\");\n@@ -505,7 +502,7 @@ enum aeu_invert_reg_special_type {\n \t {\t\t\t/* After Invert 2 */\n \t  {\"PGLUE config_space\", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},\n \t  {\"PGLUE misc_flr\", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},\n-\t  {\"PGLUE B RBC\", ATTENTION_PAR_INT, ecore_pglub_rbc_attn_cb,\n+\t  {\"PGLUE B RBC\", ATTENTION_PAR_INT, ecore_pglueb_rbc_attn_cb,\n \t   BLOCK_PGLUE_B},\n \t  {\"PGLUE misc_mctp\", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},\n \t  {\"Flash event\", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},\n@@ -827,8 +824,9 @@ static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,\n \t\t\t\t     ATTN_TYPE_INTERRUPT, !b_fatal);\n }\n \n+\t/* @DPDK */\n \t/* Reach assertion if attention is fatal */\n-\tif (b_fatal) {\n+\tif (b_fatal || (strcmp(p_bit_name, \"PGLUE B RBC\") == 0)) {\n \t\tDP_NOTICE(p_hwfn, true, \"`%s': Fatal attention\\n\",\n \t\t\t  p_bit_name);\n \ndiff --git a/drivers/net/qede/base/ecore_int.h b/drivers/net/qede/base/ecore_int.h\nindex 0c8929e..067ed60 100644\n--- a/drivers/net/qede/base/ecore_int.h\n+++ b/drivers/net/qede/base/ecore_int.h\n@@ -208,4 +208,7 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,\n #define ECORE_MAPPING_MEMORY_SIZE(dev) NUM_OF_SBS(dev)\n #endif\n \n+enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\t   struct ecore_ptt *p_ptt);\n+\n #endif /* __ECORE_INT_H__ */\ndiff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c\nindex 03cc901..88c5ceb 100644\n--- a/drivers/net/qede/base/ecore_mcp.c\n+++ b/drivers/net/qede/base/ecore_mcp.c\n@@ -893,6 +893,30 @@ enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,\n \treturn ECORE_SUCCESS;\n }\n \n+enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t struct ecore_ptt *p_ptt)\n+{\n+\tu32 resp = 0, param = 0;\n+\tenum _ecore_status_t rc;\n+\n+\trc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,\n+\t\t\t   &param);\n+\tif (rc != ECORE_SUCCESS) {\n+\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t  \"Failed to send a LOAD_DONE command, rc = %d\\n\", rc);\n+\t\treturn rc;\n+\t}\n+\n+#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR     (1 << 0)\n+\n+\t/* Check if there is a DID mismatch between nvm-cfg/efuse */\n+\tif (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)\n+\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t  \"warning: device configuration is not supported on this board type. The device may not function as expected.\\n\");\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t  struct ecore_ptt *p_ptt)\n {\n@@ -2893,6 +2917,27 @@ struct ecore_resc_alloc_out_params {\n \tu32 flags;\n };\n \n+#define ECORE_RECOVERY_PROLOG_SLEEP_MS\t100\n+\n+enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)\n+{\n+\tstruct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);\n+\tstruct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;\n+\tenum _ecore_status_t rc;\n+\n+\t/* Allow ongoing PCIe transactions to complete */\n+\tOSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);\n+\n+\t/* Clear the PF's internal FID_enable in the PXP */\n+\trc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t  \"ecore_pglueb_set_pfid_enable() failed. rc = %d.\\n\",\n+\t\t\t  rc);\n+\n+\treturn rc;\n+}\n+\n static enum _ecore_status_t\n ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,\n \t\t\t      struct ecore_ptt *p_ptt,\ndiff --git a/drivers/net/qede/base/ecore_mcp.h b/drivers/net/qede/base/ecore_mcp.h\nindex 37d1835..77fb5a3 100644\n--- a/drivers/net/qede/base/ecore_mcp.h\n+++ b/drivers/net/qede/base/ecore_mcp.h\n@@ -171,6 +171,17 @@ enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\tstruct ecore_load_req_params *p_params);\n \n /**\n+ * @brief Sends a LOAD_DONE message to the MFW\n+ *\n+ * @param p_hwfn\n+ * @param p_ptt\n+ *\n+ * @return enum _ecore_status_t - ECORE_SUCCESS - Operation was successful.\n+ */\n+enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t struct ecore_ptt *p_ptt);\n+\n+/**\n  * @brief Sends a UNLOAD_REQ message to the MFW\n  *\n  * @param p_hwfn\ndiff --git a/drivers/net/qede/base/ecore_mcp_api.h b/drivers/net/qede/base/ecore_mcp_api.h\nindex 190c135..abc190c 100644\n--- a/drivers/net/qede/base/ecore_mcp_api.h\n+++ b/drivers/net/qede/base/ecore_mcp_api.h\n@@ -736,6 +736,17 @@ enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t\t  struct ecore_ptt *p_ptt);\n \n /**\n+ * @brief A recovery handler must call this function as its first step.\n+ *        It is assumed that the handler is not run from an interrupt context.\n+ *\n+ *  @param p_dev\n+ *  @param p_ptt\n+ *\n+ * @return enum _ecore_status_t\n+ */\n+enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev);\n+\n+/**\n  * @brief Notify MFW about the change in base device properties\n  *\n  *  @param p_hwfn\n",
    "prefixes": [
        "dpdk-dev",
        "INTERNAL",
        "REVIEW",
        "1/7"
    ]
}