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GET /api/patches/26991/?format=api
{ "id": 26991, "url": "http://patches.dpdk.org/api/patches/26991/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1500310635-13180-1-git-send-email-arkadiuszx.kusztal@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1500310635-13180-1-git-send-email-arkadiuszx.kusztal@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1500310635-13180-1-git-send-email-arkadiuszx.kusztal@intel.com", "date": "2017-07-17T16:57:15", "name": "[dpdk-dev] crypto/qat: fix handle device-agnostic session", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a4efd37b0be436e607f6e8f8724b525eb9a0895b", "submitter": { "id": 452, "url": "http://patches.dpdk.org/api/people/452/?format=api", "name": "Arkadiusz Kusztal", "email": "arkadiuszx.kusztal@intel.com" }, "delegate": { "id": 22, "url": "http://patches.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1500310635-13180-1-git-send-email-arkadiuszx.kusztal@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/26991/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/26991/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 24763377E;\n\tMon, 17 Jul 2017 18:57:42 +0200 (CEST)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby dpdk.org (Postfix) with ESMTP id 9EFA0376C\n\tfor <dev@dpdk.org>; Mon, 17 Jul 2017 18:57:39 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga104.jf.intel.com with ESMTP; 17 Jul 2017 09:57:38 -0700", "from sivswdev03.ir.intel.com (HELO localhost.localdomain)\n\t([10.237.217.157])\n\tby FMSMGA003.fm.intel.com with ESMTP; 17 Jul 2017 09:57:36 -0700" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.40,375,1496127600\"; d=\"scan'208\";a=\"879777561\"", "From": "Arek Kusztal <arkadiuszx.kusztal@intel.com>", "To": "dev@dpdk.org", "Cc": "fiona.trahe@intel.com, pablo.de.lara.guarch@intel.com,\n\tjohn.griffin@intel.com, deepak.k.jain@intel.com,\n\tArek Kusztal <arkadiuszx.kusztal@intel.com>", "Date": "Mon, 17 Jul 2017 17:57:15 +0100", "Message-Id": "<1500310635-13180-1-git-send-email-arkadiuszx.kusztal@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "Subject": "[dpdk-dev] [PATCH] crypto/qat: fix handle device-agnostic session", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Older generations of QuickAssist hardware\nmay not support all algorithms supported by newer\ngenerations. When sessions were specific to the device\nthis only needed to be handled on session creation.\nWith device-agnostic sessions, a session created\nfor a newer device may get routed to an older device which\ncan't support it.\nThis patch adds an enum to define QAT device generations\nand uses this to detect and handle the above case on the\ndata path.\nIt also renames the capabilities structures and #defines\nto match the generation names and adds the generation\nto the device table in the documentation.\n\nFixes: b3bbd9e5f265 (\"cryptodev: support device independent sessions\")\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\n---\n doc/guides/cryptodevs/qat.rst | 30 ++++++++++++------------\n drivers/crypto/qat/qat_adf/qat_algs.h | 2 ++\n drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++\n drivers/crypto/qat/qat_crypto.c | 14 ++++++++---\n drivers/crypto/qat/qat_crypto.h | 8 +++++++\n drivers/crypto/qat/qat_crypto_capabilities.h | 4 ++--\n drivers/crypto/qat/qat_qp.c | 5 ++++\n drivers/crypto/qat/rte_qat_cryptodev.c | 16 +++++++------\n 8 files changed, 54 insertions(+), 27 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst\nindex b0b1760..a3fce7b 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -113,21 +113,21 @@ available kernel drivers and device ids are :\n \n .. _table_qat_pmds_drivers:\n \n-.. table:: QAT devices and drivers\n-\n- +----------+--------+---------------+------------+--------+---------+--------+------------+\n- | Device | Driver | Kernel Module | Pci Driver | PF Did | Num PFs | Vf Did | VFs per PF |\n- +==========+========+===============+============+========+=========+========+============+\n- | DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |\n- +----------+--------+---------------+------------+--------+---------+--------+------------+\n- | DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |\n- +----------+--------+---------------+------------+--------+---------+--------+------------+\n- | C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |\n- +----------+--------+---------------+------------+--------+---------+--------+------------+\n- | C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |\n- +----------+--------+---------------+------------+--------+---------+--------+------------+\n- | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |\n- +----------+--------+---------------+------------+--------+---------+--------+------------+\n+.. table:: QAT device generations, devices and drivers\n+\n+ +-----+----------+--------+---------------+------------+--------+------+--------+--------+\n+ | Gen | Device | Driver | Kernel Module | Pci Driver | PF Did | #PFs | Vf Did | VFs/PF |\n+ +=====+==========+========+===============+============+========+======+========+========+\n+ | 1 | DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |\n+ +-----+----------+--------+---------------+------------+--------+------+--------+--------+\n+ | 1 | DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |\n+ +-----+----------+--------+---------------+------------+--------+------+--------+--------+\n+ | 2 | C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |\n+ +-----+----------+--------+---------------+------------+--------+------+--------+--------+\n+ | 2 | C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |\n+ +-----+----------+--------+---------------+------------+--------+------+--------+--------+\n+ | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |\n+ +-----+----------+--------+---------------+------------+--------+------+--------+--------+\n \n \n The ``Driver`` column indicates either the Linux kernel version in which\ndiff --git a/drivers/crypto/qat/qat_adf/qat_algs.h b/drivers/crypto/qat/qat_adf/qat_algs.h\nindex 4c0a09b..c280325 100644\n--- a/drivers/crypto/qat/qat_adf/qat_algs.h\n+++ b/drivers/crypto/qat/qat_adf/qat_algs.h\n@@ -51,6 +51,7 @@\n #include \"icp_qat_hw.h\"\n #include \"icp_qat_fw.h\"\n #include \"icp_qat_fw_la.h\"\n+#include \"../qat_crypto.h\"\n \n /*\n * Key Modifier (KM) value used in KASUMI algorithm in F9 mode to XOR\n@@ -137,6 +138,7 @@ struct qat_session {\n \t} auth_iv;\n \tuint16_t digest_length;\n \trte_spinlock_t lock;\t/* protects this struct */\n+\tenum qat_device_gen min_qat_dev_gen;\n };\n \n int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg);\ndiff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\nindex cff8d12..7c753e4 100644\n--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\n+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\n@@ -606,6 +606,7 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,\n \t\tcipher_cd_ctrl->cipher_state_sz =\n \t\t\tICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;\n \t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n+\t\tcdesc->min_qat_dev_gen = QAT_GEN2;\n \t} else {\n \t\ttotal_key_size = cipherkeylen;\n \t\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;\n@@ -858,6 +859,7 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,\n \t\tcdesc->cd_cur_ptr += state1_size + state2_size\n \t\t\t+ ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;\n \t\tauth_param->hash_state_sz = ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;\n+\t\tcdesc->min_qat_dev_gen = QAT_GEN2;\n \n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_MD5:\ndiff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c\nindex 098109e..9c5e08c 100644\n--- a/drivers/crypto/qat/qat_crypto.c\n+++ b/drivers/crypto/qat/qat_crypto.c\n@@ -214,7 +214,7 @@ adf_modulo(uint32_t data, uint32_t shift);\n \n static inline int\n qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,\n-\t\tstruct qat_crypto_op_cookie *qat_op_cookie);\n+\t\tstruct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);\n \n void\n qat_crypto_sym_clear_session(struct rte_cryptodev *dev,\n@@ -492,6 +492,8 @@ qat_crypto_set_session_parameters(struct rte_cryptodev *dev,\n \tsession->cd_paddr = rte_mempool_virt2phy(NULL, session) +\n \t\t\toffsetof(struct qat_session, cd);\n \n+\tsession->min_qat_dev_gen = QAT_GEN1;\n+\n \t/* Get requested QAT command id */\n \tqat_cmd_id = qat_get_cmd_id(xform);\n \tif (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {\n@@ -924,7 +926,7 @@ qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n \n \twhile (nb_ops_sent != nb_ops_possible) {\n \t\tret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,\n-\t\t\t\ttmp_qp->op_cookies[tail / queue->msg_size]);\n+\t\t\ttmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);\n \t\tif (ret != 0) {\n \t\t\ttmp_qp->stats.enqueue_err_count++;\n \t\t\t/*\n@@ -1081,7 +1083,7 @@ set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,\n \n static inline int\n qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,\n-\t\tstruct qat_crypto_op_cookie *qat_op_cookie)\n+\t\tstruct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)\n {\n \tint ret = 0;\n \tstruct qat_session *ctx;\n@@ -1117,6 +1119,12 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,\n \t\treturn -EINVAL;\n \t}\n \n+\tif (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {\n+\t\tPMD_DRV_LOG(ERR, \"Session alg not supported on this device gen\");\n+\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;\n+\t\treturn -EINVAL;\n+\t}\n+\n \tqat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;\n \trte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));\n \tqat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;\ndiff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h\nindex 915f960..d637dac 100644\n--- a/drivers/crypto/qat/qat_crypto.h\n+++ b/drivers/crypto/qat/qat_crypto.h\n@@ -50,6 +50,11 @@\n \t(((num) + (align) - 1) & ~((align) - 1))\n #define QAT_64_BTYE_ALIGN_MASK (~0x3f)\n \n+enum qat_device_gen {\n+\tQAT_GEN1 = 1,\n+\tQAT_GEN2,\n+};\n+\n /**\n * Structure associated with each queue.\n */\n@@ -77,6 +82,7 @@ struct qat_qp {\n \tstruct rte_mempool *op_cookie_pool;\n \tvoid **op_cookies;\n \tuint32_t nb_descriptors;\n+\tenum qat_device_gen qat_dev_gen;\n } __rte_cache_aligned;\n \n /** private data structure for each QAT device */\n@@ -85,6 +91,8 @@ struct qat_pmd_private {\n \t/**< Max number of queue pairs supported by device */\n \tunsigned max_nb_sessions;\n \t/**< Max number of sessions supported by device */\n+\tenum qat_device_gen qat_dev_gen;\n+\t/**< QAT device generation */\n \tconst struct rte_cryptodev_capabilities *qat_dev_capabilities;\n };\n \ndiff --git a/drivers/crypto/qat/qat_crypto_capabilities.h b/drivers/crypto/qat/qat_crypto_capabilities.h\nindex d18bcbd..567e1ac 100644\n--- a/drivers/crypto/qat/qat_crypto_capabilities.h\n+++ b/drivers/crypto/qat/qat_crypto_capabilities.h\n@@ -34,7 +34,7 @@\n #ifndef _QAT_CRYPTO_CAPABILITIES_H_\n #define _QAT_CRYPTO_CAPABILITIES_H_\n \n-#define QAT_BASE_CPM16_SYM_CAPABILITIES\t\t\t\t\t\\\n+#define QAT_BASE_GEN1_SYM_CAPABILITIES\t\t\t\t\t\\\n \t{\t/* SHA1 HMAC */\t\t\t\t\t\t\\\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n \t\t{.sym = {\t\t\t\t\t\t\\\n@@ -506,7 +506,7 @@\n \t\t}, }\t\t\t\t\t\t\t\\\n \t}\n \n-#define QAT_EXTRA_CPM17_SYM_CAPABILITIES\t\t\t\t\\\n+#define QAT_EXTRA_GEN2_SYM_CAPABILITIES\t\t\t\t\t\\\n \t{\t/* ZUC (EEA3) */\t\t\t\t\t\\\n \t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n \t\t{.sym = {\t\t\t\t\t\t\\\ndiff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c\nindex 2b2ab42..5048d21 100644\n--- a/drivers/crypto/qat/qat_qp.c\n+++ b/drivers/crypto/qat/qat_qp.c\n@@ -243,6 +243,11 @@ int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,\n \t\t\t\toffsetof(struct qat_crypto_op_cookie,\n \t\t\t\tqat_sgl_list_dst);\n \t}\n+\n+\tstruct qat_pmd_private *internals\n+\t\t= dev->data->dev_private;\n+\tqp->qat_dev_gen = internals->qat_dev_gen;\n+\n \tdev->data->queue_pairs[queue_pair_id] = qp;\n \treturn 0;\n \ndiff --git a/drivers/crypto/qat/rte_qat_cryptodev.c b/drivers/crypto/qat/rte_qat_cryptodev.c\nindex 9a710e6..7d56fca 100644\n--- a/drivers/crypto/qat/rte_qat_cryptodev.c\n+++ b/drivers/crypto/qat/rte_qat_cryptodev.c\n@@ -42,14 +42,14 @@\n \n uint8_t cryptodev_qat_driver_id;\n \n-static const struct rte_cryptodev_capabilities qat_cpm16_capabilities[] = {\n-\tQAT_BASE_CPM16_SYM_CAPABILITIES,\n+static const struct rte_cryptodev_capabilities qat_gen1_capabilities[] = {\n+\tQAT_BASE_GEN1_SYM_CAPABILITIES,\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n \n-static const struct rte_cryptodev_capabilities qat_cpm17_capabilities[] = {\n-\tQAT_BASE_CPM16_SYM_CAPABILITIES,\n-\tQAT_EXTRA_CPM17_SYM_CAPABILITIES,\n+static const struct rte_cryptodev_capabilities qat_gen2_capabilities[] = {\n+\tQAT_BASE_GEN1_SYM_CAPABILITIES,\n+\tQAT_EXTRA_GEN2_SYM_CAPABILITIES,\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n \n@@ -122,12 +122,14 @@ crypto_qat_dev_init(struct rte_cryptodev *cryptodev)\n \tinternals->max_nb_sessions = RTE_QAT_PMD_MAX_NB_SESSIONS;\n \tswitch (RTE_DEV_TO_PCI(cryptodev->device)->id.device_id) {\n \tcase 0x0443:\n-\t\tinternals->qat_dev_capabilities = qat_cpm16_capabilities;\n+\t\tinternals->qat_dev_gen = QAT_GEN1;\n+\t\tinternals->qat_dev_capabilities = qat_gen1_capabilities;\n \t\tbreak;\n \tcase 0x37c9:\n \tcase 0x19e3:\n \tcase 0x6f55:\n-\t\tinternals->qat_dev_capabilities = qat_cpm17_capabilities;\n+\t\tinternals->qat_dev_gen = QAT_GEN2;\n+\t\tinternals->qat_dev_capabilities = qat_gen2_capabilities;\n \t\tbreak;\n \tdefault:\n \t\tPMD_DRV_LOG(ERR,\n", "prefixes": [ "dpdk-dev" ] }