Patch Detail

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{
    "id": 26081,
    "url": "http://patches.dpdk.org/api/patches/26081/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1498812875-6945-20-git-send-email-nipun.gupta@nxp.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1498812875-6945-20-git-send-email-nipun.gupta@nxp.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1498812875-6945-20-git-send-email-nipun.gupta@nxp.com",
    "date": "2017-06-30T08:54:33",
    "name": "[dpdk-dev,19/21,v5] bus/fslmc: enable portal interrupt handling",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "0b1161905c4436c627400cceb02d66b995613854",
    "submitter": {
        "id": 471,
        "url": "http://patches.dpdk.org/api/people/471/?format=api",
        "name": "Nipun Gupta",
        "email": "nipun.gupta@nxp.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1498812875-6945-20-git-send-email-nipun.gupta@nxp.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/26081/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/26081/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id D13737CD5;\n\tFri, 30 Jun 2017 10:56:05 +0200 (CEST)",
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            "from b27504-OptiPlex-790.ap.freescale.net\n\t(b27504-OptiPlex-790.ap.freescale.net [10.232.132.60])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv5U8sfKD032271; Fri, 30 Jun 2017 01:55:42 -0700"
        ],
        "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;",
        "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;",
        "From": "Nipun Gupta <nipun.gupta@nxp.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<hemant.agrawal@nxp.com>, <jerin.jacob@caviumnetworks.com>,\n\t<harry.van.haaren@intel.com>, <bruce.richardson@intel.com>,\n\t<gage.eads@intel.com>, <shreyansh.jain@nxp.com>, Nipun Gupta\n\t<nipun.gupta@nxp.com>",
        "Date": "Fri, 30 Jun 2017 14:24:33 +0530",
        "Message-ID": "<1498812875-6945-20-git-send-email-nipun.gupta@nxp.com>",
        "X-Mailer": "git-send-email 1.9.1",
        "In-Reply-To": "<1498812875-6945-1-git-send-email-nipun.gupta@nxp.com>",
        "References": "<1495735361-4840-1-git-send-email-nipun.gupta@nxp.com>\n\t<1498812875-6945-1-git-send-email-nipun.gupta@nxp.com>",
        "X-EOPAttributedMessage": "0",
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        "Subject": "[dpdk-dev] [PATCH 19/21 v5] bus/fslmc: enable portal interrupt\n\thandling",
        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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    },
    "content": "Eventdev requires portal interrupts to handle timeout in the\nevent dequeue. This patch provides mechanism to enable the\nportal interrupts.\n\nSigned-off-by: Nipun Gupta <nipun.gupta@nxp.com>\n---\n drivers/bus/fslmc/portal/dpaa2_hw_dpio.c           | 108 ++++++++++++++++++++-\n drivers/bus/fslmc/portal/dpaa2_hw_pvt.h            |   3 +-\n drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h |  30 ++++++\n drivers/bus/fslmc/qbman/qbman_portal.c             |  22 +++++\n drivers/bus/fslmc/rte_bus_fslmc_version.map        |   1 +\n 5 files changed, 158 insertions(+), 6 deletions(-)",
    "diff": "diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\nindex 63378f0..5d53342 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\n@@ -46,6 +46,8 @@\n #include <sys/stat.h>\n #include <sys/mman.h>\n #include <sys/syscall.h>\n+#include <sys/epoll.h>\n+#include<sys/eventfd.h>\n \n #include <rte_mbuf.h>\n #include <rte_ethdev.h>\n@@ -106,6 +108,95 @@\n \treturn dpaa2_core_cluster_base + x;\n }\n \n+static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)\n+{\n+#define STRING_LEN\t28\n+#define COMMAND_LEN\t50\n+\tuint32_t cpu_mask = 1;\n+\tint ret;\n+\tsize_t len = 0;\n+\tchar *temp = NULL, *token = NULL;\n+\tchar string[STRING_LEN], command[COMMAND_LEN];\n+\tFILE *file;\n+\n+\tsnprintf(string, STRING_LEN, \"dpio.%d\", dpio_id);\n+\tfile = fopen(\"/proc/interrupts\", \"r\");\n+\tif (!file) {\n+\t\tPMD_DRV_LOG(WARN, \"Failed to open /proc/interrupts file\\n\");\n+\t\treturn;\n+\t}\n+\twhile (getline(&temp, &len, file) != -1) {\n+\t\tif ((strstr(temp, string)) != NULL) {\n+\t\t\ttoken = strtok(temp, \":\");\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (!token) {\n+\t\tPMD_DRV_LOG(WARN, \"Failed to get interrupt id for dpio.%d\\n\",\n+\t\t\t    dpio_id);\n+\t\tif (temp)\n+\t\t\tfree(temp);\n+\t\tfclose(file);\n+\t\treturn;\n+\t}\n+\n+\tcpu_mask = cpu_mask << rte_lcore_id();\n+\tsnprintf(command, COMMAND_LEN, \"echo %X > /proc/irq/%s/smp_affinity\",\n+\t\t cpu_mask, token);\n+\tret = system(command);\n+\tif (ret < 0)\n+\t\tPMD_DRV_LOG(WARN,\n+\t\t\t\"Failed to affine interrupts on respective core\\n\");\n+\telse\n+\t\tPMD_DRV_LOG(WARN, \" %s command is executed\\n\", command);\n+\n+\tfree(temp);\n+\tfclose(file);\n+}\n+\n+static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)\n+{\n+\tstruct epoll_event epoll_ev;\n+\tint eventfd, dpio_epoll_fd, ret;\n+\tint threshold = 0x3, timeout = 0xFF;\n+\n+\tdpio_epoll_fd = epoll_create(1);\n+\tret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Interrupt registeration failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tif (getenv(\"DPAA2_PORTAL_INTR_THRESHOLD\"))\n+\t\tthreshold = atoi(getenv(\"DPAA2_PORTAL_INTR_THRESHOLD\"));\n+\n+\tif (getenv(\"DPAA2_PORTAL_INTR_TIMEOUT\"))\n+\t\tsscanf(getenv(\"DPAA2_PORTAL_INTR_TIMEOUT\"), \"%x\", &timeout);\n+\n+\tqbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,\n+\t\t\t\t\tQBMAN_SWP_INTERRUPT_DQRI);\n+\tqbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);\n+\tqbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);\n+\tqbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);\n+\tqbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);\n+\n+\teventfd = dpio_dev->intr_handle.fd;\n+\tepoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;\n+\tepoll_ev.data.fd = eventfd;\n+\n+\tret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);\n+\tif (ret < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"epoll_ctl failed\\n\");\n+\t\treturn -1;\n+\t}\n+\tdpio_dev->epoll_fd = dpio_epoll_fd;\n+\n+\tdpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id);\n+\n+\treturn 0;\n+}\n+\n static int\n configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)\n {\n@@ -215,6 +306,11 @@\n \t\treturn -1;\n \t}\n \n+\tif (dpaa2_dpio_intr_init(dpio_dev)) {\n+\t\tPMD_DRV_LOG(ERR, \"Interrupt registration failed for dpio\\n\");\n+\t\treturn -1;\n+\t}\n+\n \treturn 0;\n }\n \n@@ -339,6 +435,7 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)\n {\n \tstruct dpaa2_dpio_dev *dpio_dev;\n \tstruct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};\n+\tint vfio_dev_fd;\n \n \tif (obj_info->num_regions < NUM_DPIO_REGIONS) {\n \t\tPMD_INIT_LOG(ERR, \"ERROR, Not sufficient number \"\n@@ -355,13 +452,14 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)\n \n \tdpio_dev->dpio = NULL;\n \tdpio_dev->hw_id = object_id;\n-\tdpio_dev->vfio_fd = vdev->fd;\n+\tdpio_dev->intr_handle.vfio_dev_fd = vdev->fd;\n \trte_atomic16_init(&dpio_dev->ref_count);\n \t/* Using single portal  for all devices */\n \tdpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];\n \n \treg_info.index = 0;\n-\tif (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info)) {\n+\tvfio_dev_fd = dpio_dev->intr_handle.vfio_dev_fd;\n+\tif (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info)) {\n \t\tPMD_INIT_LOG(ERR, \"vfio: error getting region info\\n\");\n \t\trte_free(dpio_dev);\n \t\treturn -1;\n@@ -370,7 +468,7 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)\n \tdpio_dev->ce_size = reg_info.size;\n \tdpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,\n \t\t\t\tPROT_WRITE | PROT_READ, MAP_SHARED,\n-\t\t\t\tdpio_dev->vfio_fd, reg_info.offset);\n+\t\t\t\tvfio_dev_fd, reg_info.offset);\n \n \t/* Create Mapping for QBMan Cache Enabled area. This is a fix for\n \t * SMMU fault for DQRR statshing transaction.\n@@ -383,7 +481,7 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)\n \t}\n \n \treg_info.index = 1;\n-\tif (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info)) {\n+\tif (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info)) {\n \t\tPMD_INIT_LOG(ERR, \"vfio: error getting region info\\n\");\n \t\trte_free(dpio_dev);\n \t\treturn -1;\n@@ -392,7 +490,7 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)\n \tdpio_dev->ci_size = reg_info.size;\n \tdpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,\n \t\t\t\tPROT_WRITE | PROT_READ, MAP_SHARED,\n-\t\t\t\tdpio_dev->vfio_fd, reg_info.offset);\n+\t\t\t\tvfio_dev_fd, reg_info.offset);\n \n \tif (configure_dpio_qbman_swp(dpio_dev)) {\n \t\tPMD_INIT_LOG(ERR,\ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\nindex 975e431..f5644b9 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n@@ -101,7 +101,8 @@ struct dpaa2_dpio_dev {\n \tuintptr_t qbman_portal_ci_paddr;\n \t\t/**< Physical address of Cache Inhibit Area */\n \tuintptr_t ci_size; /**< Size of the CI region */\n-\tint32_t\tvfio_fd; /**< File descriptor received via VFIO */\n+\tstruct rte_intr_handle intr_handle; /* Interrupt related info */\n+\tint32_t\tepoll_fd; /**< File descriptor created for interrupt polling */\n \tint32_t hw_id; /**< An unique ID of this DPIO device instance */\n \tuint64_t dqrr_held;\n \tuint8_t dqrr_size;\ndiff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\nindex 06bd063..9e9047e 100644\n--- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\n+++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\n@@ -124,6 +124,36 @@\n void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask);\n \n /**\n+ * qbman_swp_dqrr_thrshld_read_status() - Get the data in software portal\n+ * DQRR interrupt threshold register.\n+ * @p: the given software portal object.\n+ */\n+uint32_t qbman_swp_dqrr_thrshld_read_status(struct qbman_swp *p);\n+\n+/**\n+ * qbman_swp_dqrr_thrshld_write() - Set the data in software portal\n+ * DQRR interrupt threshold register.\n+ * @p: the given software portal object.\n+ * @mask: The value to set in SWP_DQRR_ITR register.\n+ */\n+void qbman_swp_dqrr_thrshld_write(struct qbman_swp *p, uint32_t mask);\n+\n+/**\n+ * qbman_swp_intr_timeout_read_status() - Get the data in software portal\n+ * Interrupt Time-Out period register.\n+ * @p: the given software portal object.\n+ */\n+uint32_t qbman_swp_intr_timeout_read_status(struct qbman_swp *p);\n+\n+/**\n+ * qbman_swp_intr_timeout_write() - Set the data in software portal\n+ * Interrupt Time-Out period register.\n+ * @p: the given software portal object.\n+ * @mask: The value to set in SWP_ITPR register.\n+ */\n+void qbman_swp_intr_timeout_write(struct qbman_swp *p, uint32_t mask);\n+\n+/**\n  * qbman_swp_interrupt_get_trigger() - Get the data in software portal\n  * interrupt enable register.\n  * @p: the given software portal object.\ndiff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c\nindex 8002690..dd62e9a 100644\n--- a/drivers/bus/fslmc/qbman/qbman_portal.c\n+++ b/drivers/bus/fslmc/qbman/qbman_portal.c\n@@ -44,6 +44,8 @@\n #define QBMAN_CINH_SWP_IER     0xe40\n #define QBMAN_CINH_SWP_ISDR    0xe80\n #define QBMAN_CINH_SWP_IIR     0xec0\n+#define QBMAN_CINH_SWP_DQRR_ITR    0xa80\n+#define QBMAN_CINH_SWP_ITPR    0xf40\n \n /* CENA register offsets */\n #define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6))\n@@ -218,6 +220,26 @@ void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask)\n \tqbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISR, mask);\n }\n \n+uint32_t qbman_swp_dqrr_thrshld_read_status(struct qbman_swp *p)\n+{\n+\treturn qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_DQRR_ITR);\n+}\n+\n+void qbman_swp_dqrr_thrshld_write(struct qbman_swp *p, uint32_t mask)\n+{\n+\tqbman_cinh_write(&p->sys, QBMAN_CINH_SWP_DQRR_ITR, mask);\n+}\n+\n+uint32_t qbman_swp_intr_timeout_read_status(struct qbman_swp *p)\n+{\n+\treturn qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ITPR);\n+}\n+\n+void qbman_swp_intr_timeout_write(struct qbman_swp *p, uint32_t mask)\n+{\n+\tqbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ITPR, mask);\n+}\n+\n uint32_t qbman_swp_interrupt_get_trigger(struct qbman_swp *p)\n {\n \treturn qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IER);\ndiff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map\nindex 9950557..3cdf14e 100644\n--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map\n+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map\n@@ -70,6 +70,7 @@ DPDK_17.08 {\n \tqbman_swp_dqrr_consume;\n \tqbman_swp_dqrr_next;\n \tqbman_swp_enqueue_multiple_eqdesc;\n+\tqbman_swp_interrupt_clear_status;\n \tqbman_swp_push_set;\n \trte_dpaa2_alloc_dpci_dev;\n \trte_fslmc_object_register;\n",
    "prefixes": [
        "dpdk-dev",
        "19/21",
        "v5"
    ]
}