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GET /api/patches/22233/?format=api
{ "id": 22233, "url": "http://patches.dpdk.org/api/patches/22233/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1490340531-11403-31-git-send-email-rasesh.mody@cavium.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1490340531-11403-31-git-send-email-rasesh.mody@cavium.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1490340531-11403-31-git-send-email-rasesh.mody@cavium.com", "date": "2017-03-24T07:28:20", "name": "[dpdk-dev,v3,30/61] net/qede/base: infrastructure changes for VF tunnelling", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "a953a926ea7cbedd50646491821f43364c367bc8", "submitter": { "id": 569, "url": "http://patches.dpdk.org/api/people/569/?format=api", "name": "Mody, Rasesh", "email": "rasesh.mody@cavium.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1490340531-11403-31-git-send-email-rasesh.mody@cavium.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/22233/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/22233/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 6CCC3D1FE;\n\tFri, 24 Mar 2017 08:32:59 +0100 (CET)", "from mx0b-0016ce01.pphosted.com (mx0a-0016ce01.pphosted.com\n\t[67.231.148.157]) by dpdk.org (Postfix) with ESMTP id B87FFD040\n\tfor <dev@dpdk.org>; Fri, 24 Mar 2017 08:30:48 +0100 (CET)", "from pps.filterd (m0095336.ppops.net [127.0.0.1])\n\tby mx0a-0016ce01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv2O7UkL6011810; Fri, 24 Mar 2017 00:30:46 -0700", "from avcashub1.qlogic.com ([198.186.0.115])\n\tby mx0a-0016ce01.pphosted.com with ESMTP id 29b9xy1bng-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tFri, 24 Mar 2017 00:30:46 -0700", "from avluser05.qlc.com (10.1.113.115) by avcashub1.qlogic.org\n\t(10.1.4.190) with Microsoft SMTP Server (TLS) id 14.3.235.1;\n\tFri, 24 Mar 2017 00:30:46 -0700", "(from rmody@localhost)\tby avluser05.qlc.com (8.14.4/8.14.4/Submit)\n\tid v2O7UkAR011663;\tFri, 24 Mar 2017 00:30:46 -0700" ], "X-Authentication-Warning": "avluser05.qlc.com: rmody set sender to\n\trasesh.mody@cavium.com using -f", "From": "Rasesh Mody <rasesh.mody@cavium.com>", "To": "<ferruh.yigit@intel.com>, <dev@dpdk.org>", "CC": "Rasesh Mody <rasesh.mody@cavium.com>, <Dept-EngDPDKDev@cavium.com>", "Date": "Fri, 24 Mar 2017 00:28:20 -0700", "Message-ID": "<1490340531-11403-31-git-send-email-rasesh.mody@cavium.com>", "X-Mailer": "git-send-email 1.7.10.3", "In-Reply-To": "<dd51cd87-72b4-fa89-3dc1-b79c32df1355@intel.com>", "References": "<dd51cd87-72b4-fa89-3dc1-b79c32df1355@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "disclaimer": "bypass", "X-Proofpoint-Virus-Version": "vendor=nai engine=5800 definitions=8476\n\tsignatures=668449", "X-Proofpoint-Spam-Details": "rule=notspam policy=default score=0\n\tpriorityscore=1501 malwarescore=0\n\tsuspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015\n\tlowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam\n\tadjust=0\n\treason=mlx scancount=1 engine=8.0.1-1702020001\n\tdefinitions=main-1703240068", "Subject": "[dpdk-dev] [PATCH v3 30/61] net/qede/base: infrastructure changes\n\tfor VF tunnelling", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Infrastructure changes for VF tunnelling.\n\nSigned-off-by: Rasesh Mody <rasesh.mody@cavium.com>\n---\n drivers/net/qede/base/bcm_osal.h | 3 +-\n drivers/net/qede/base/ecore.h | 14 ++++-\n drivers/net/qede/base/ecore_sp_commands.c | 87 +++++++++++++++++++----------\n drivers/net/qede/qede_if.h | 5 ++\n drivers/net/qede/qede_main.c | 18 ++++++\n 5 files changed, 93 insertions(+), 34 deletions(-)", "diff": "diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\nindex 82e3ebd..513d542 100644\n--- a/drivers/net/qede/base/bcm_osal.h\n+++ b/drivers/net/qede/base/bcm_osal.h\n@@ -292,7 +292,8 @@ typedef struct osal_list_t {\n #define OSAL_WMB(dev)\t\t\trte_wmb()\n #define OSAL_DMA_SYNC(dev, addr, length, is_post) nothing\n \n-#define OSAL_BITS_PER_BYTE\t\t(8)\n+#define OSAL_BIT(nr) (1UL << (nr))\n+#define OSAL_BITS_PER_BYTE\t(8)\n #define OSAL_BITS_PER_UL\t(sizeof(unsigned long) * OSAL_BITS_PER_BYTE)\n #define OSAL_BITS_PER_UL_MASK\t\t(OSAL_BITS_PER_UL - 1)\n \ndiff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex de0f49a..5c12c1e 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -470,6 +470,17 @@ struct ecore_fw_data {\n \tu32 init_ops_size;\n };\n \n+struct ecore_tunnel_info {\n+\tu8\t\ttunn_clss_vxlan;\n+\tu8\t\ttunn_clss_l2geneve;\n+\tu8\t\ttunn_clss_ipgeneve;\n+\tu8\t\ttunn_clss_l2gre;\n+\tu8\t\ttunn_clss_ipgre;\n+\tunsigned long\ttunn_mode;\n+\tu16\t\tport_vxlan_udp_port;\n+\tu16\t\tport_geneve_udp_port;\n+};\n+\n struct ecore_hwfn {\n \tstruct ecore_dev\t\t*p_dev;\n \tu8\t\t\t\tmy_id;\t\t/* ID inside the PF */\n@@ -724,8 +735,7 @@ struct ecore_dev {\n \t/* SRIOV */\n \tstruct ecore_hw_sriov_info\t*p_iov_info;\n #define IS_ECORE_SRIOV(p_dev)\t\t(!!(p_dev)->p_iov_info)\n-\tunsigned long\t\t\ttunn_mode;\n-\n+\tstruct ecore_tunnel_info\ttunnel;\n \tbool\t\t\t\tb_is_vf;\n \n \tu32\t\t\t\tdrv_type;\ndiff --git a/drivers/net/qede/base/ecore_sp_commands.c b/drivers/net/qede/base/ecore_sp_commands.c\nindex b831970..f5860a0 100644\n--- a/drivers/net/qede/base/ecore_sp_commands.c\n+++ b/drivers/net/qede/base/ecore_sp_commands.c\n@@ -111,8 +111,9 @@ ecore_tunn_set_pf_fix_tunn_mode(struct ecore_hwfn *p_hwfn,\n \t\t\t\tstruct ecore_tunn_update_params *p_src,\n \t\t\t\tstruct pf_update_tunnel_config *p_tunn_cfg)\n {\n-\tunsigned long cached_tunn_mode = p_hwfn->p_dev->tunn_mode;\n \tunsigned long update_mask = p_src->tunn_mode_update_mask;\n+\tstruct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;\n+\tunsigned long cached_tunn_mode = p_tun->tunn_mode;\n \tunsigned long tunn_mode = p_src->tunn_mode;\n \tunsigned long new_tunn_mode = 0;\n \n@@ -149,9 +150,10 @@ ecore_tunn_set_pf_fix_tunn_mode(struct ecore_hwfn *p_hwfn,\n \t}\n \n \tif (p_src->update_geneve_udp_port) {\n+\t\tp_tun->port_geneve_udp_port = p_src->geneve_udp_port;\n \t\tp_tunn_cfg->set_geneve_udp_port_flg = 1;\n \t\tp_tunn_cfg->geneve_udp_port =\n-\t\t OSAL_CPU_TO_LE16(p_src->geneve_udp_port);\n+\t\t\t\tOSAL_CPU_TO_LE16(p_tun->port_geneve_udp_port);\n \t}\n \n \tif (OSAL_TEST_BIT(ECORE_MODE_L2GENEVE_TUNN, &update_mask)) {\n@@ -178,33 +180,39 @@ ecore_tunn_set_pf_update_params(struct ecore_hwfn *p_hwfn,\n \t\t\t\tstruct ecore_tunn_update_params *p_src,\n \t\t\t\tstruct pf_update_tunnel_config *p_tunn_cfg)\n {\n-\tunsigned long tunn_mode = p_src->tunn_mode;\n+\tstruct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;\n \tenum tunnel_clss type;\n \n \tecore_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg);\n+\tp_tun->tunn_mode = p_src->tunn_mode;\n+\n \tp_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss;\n \tp_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss;\n \n \ttype = ecore_tunn_get_clss_type(p_src->tunn_clss_vxlan);\n-\tp_tunn_cfg->tunnel_clss_vxlan = type;\n+\tp_tun->tunn_clss_vxlan = type;\n+\tp_tunn_cfg->tunnel_clss_vxlan = p_tun->tunn_clss_vxlan;\n \ttype = ecore_tunn_get_clss_type(p_src->tunn_clss_l2gre);\n-\tp_tunn_cfg->tunnel_clss_l2gre = type;\n+\tp_tun->tunn_clss_l2gre = type;\n+\tp_tunn_cfg->tunnel_clss_l2gre = p_tun->tunn_clss_l2gre;\n \ttype = ecore_tunn_get_clss_type(p_src->tunn_clss_ipgre);\n-\tp_tunn_cfg->tunnel_clss_ipgre = type;\n+\tp_tun->tunn_clss_ipgre = type;\n+\tp_tunn_cfg->tunnel_clss_ipgre = p_tun->tunn_clss_ipgre;\n \n \tif (p_src->update_vxlan_udp_port) {\n+\t\tp_tun->port_vxlan_udp_port = p_src->vxlan_udp_port;\n \t\tp_tunn_cfg->set_vxlan_udp_port_flg = 1;\n \t\tp_tunn_cfg->vxlan_udp_port =\n-\t\t OSAL_CPU_TO_LE16(p_src->vxlan_udp_port);\n+\t\t\t\tOSAL_CPU_TO_LE16(p_tun->port_vxlan_udp_port);\n \t}\n \n-\tif (OSAL_TEST_BIT(ECORE_MODE_L2GRE_TUNN, &tunn_mode))\n+\tif (OSAL_TEST_BIT(ECORE_MODE_L2GRE_TUNN, &p_tun->tunn_mode))\n \t\tp_tunn_cfg->tx_enable_l2gre = 1;\n \n-\tif (OSAL_TEST_BIT(ECORE_MODE_IPGRE_TUNN, &tunn_mode))\n+\tif (OSAL_TEST_BIT(ECORE_MODE_IPGRE_TUNN, &p_tun->tunn_mode))\n \t\tp_tunn_cfg->tx_enable_ipgre = 1;\n \n-\tif (OSAL_TEST_BIT(ECORE_MODE_VXLAN_TUNN, &tunn_mode))\n+\tif (OSAL_TEST_BIT(ECORE_MODE_VXLAN_TUNN, &p_tun->tunn_mode))\n \t\tp_tunn_cfg->tx_enable_vxlan = 1;\n \n \tif (ECORE_IS_BB_A0(p_hwfn->p_dev)) {\n@@ -215,21 +223,24 @@ ecore_tunn_set_pf_update_params(struct ecore_hwfn *p_hwfn,\n \t}\n \n \tif (p_src->update_geneve_udp_port) {\n+\t\tp_tun->port_geneve_udp_port = p_src->geneve_udp_port;\n \t\tp_tunn_cfg->set_geneve_udp_port_flg = 1;\n \t\tp_tunn_cfg->geneve_udp_port =\n-\t\t OSAL_CPU_TO_LE16(p_src->geneve_udp_port);\n+\t\t\t\tOSAL_CPU_TO_LE16(p_tun->port_geneve_udp_port);\n \t}\n \n-\tif (OSAL_TEST_BIT(ECORE_MODE_L2GENEVE_TUNN, &tunn_mode))\n+\tif (OSAL_TEST_BIT(ECORE_MODE_L2GENEVE_TUNN, &p_tun->tunn_mode))\n \t\tp_tunn_cfg->tx_enable_l2geneve = 1;\n \n-\tif (OSAL_TEST_BIT(ECORE_MODE_IPGENEVE_TUNN, &tunn_mode))\n+\tif (OSAL_TEST_BIT(ECORE_MODE_IPGENEVE_TUNN, &p_tun->tunn_mode))\n \t\tp_tunn_cfg->tx_enable_ipgeneve = 1;\n \n \ttype = ecore_tunn_get_clss_type(p_src->tunn_clss_l2geneve);\n-\tp_tunn_cfg->tunnel_clss_l2geneve = type;\n+\tp_tun->tunn_clss_l2geneve = type;\n+\tp_tunn_cfg->tunnel_clss_l2geneve = p_tun->tunn_clss_l2geneve;\n \ttype = ecore_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);\n-\tp_tunn_cfg->tunnel_clss_ipgeneve = type;\n+\tp_tun->tunn_clss_ipgeneve = type;\n+\tp_tunn_cfg->tunnel_clss_ipgeneve = p_tun->tunn_clss_ipgeneve;\n }\n \n static void ecore_set_hw_tunn_mode(struct ecore_hwfn *p_hwfn,\n@@ -269,33 +280,37 @@ ecore_tunn_set_pf_start_params(struct ecore_hwfn *p_hwfn,\n \t\t\t struct ecore_tunn_start_params *p_src,\n \t\t\t struct pf_start_tunnel_config *p_tunn_cfg)\n {\n-\tunsigned long tunn_mode;\n+\tstruct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;\n \tenum tunnel_clss type;\n \n \tif (!p_src)\n \t\treturn;\n \n-\ttunn_mode = p_src->tunn_mode;\n+\tp_tun->tunn_mode = p_src->tunn_mode;\n \ttype = ecore_tunn_get_clss_type(p_src->tunn_clss_vxlan);\n-\tp_tunn_cfg->tunnel_clss_vxlan = type;\n+\tp_tun->tunn_clss_vxlan = type;\n+\tp_tunn_cfg->tunnel_clss_vxlan = p_tun->tunn_clss_vxlan;\n \ttype = ecore_tunn_get_clss_type(p_src->tunn_clss_l2gre);\n-\tp_tunn_cfg->tunnel_clss_l2gre = type;\n+\tp_tun->tunn_clss_l2gre = type;\n+\tp_tunn_cfg->tunnel_clss_l2gre = p_tun->tunn_clss_l2gre;\n \ttype = ecore_tunn_get_clss_type(p_src->tunn_clss_ipgre);\n-\tp_tunn_cfg->tunnel_clss_ipgre = type;\n+\tp_tun->tunn_clss_ipgre = type;\n+\tp_tunn_cfg->tunnel_clss_ipgre = p_tun->tunn_clss_ipgre;\n \n \tif (p_src->update_vxlan_udp_port) {\n+\t\tp_tun->port_vxlan_udp_port = p_src->vxlan_udp_port;\n \t\tp_tunn_cfg->set_vxlan_udp_port_flg = 1;\n \t\tp_tunn_cfg->vxlan_udp_port =\n-\t\t OSAL_CPU_TO_LE16(p_src->vxlan_udp_port);\n+\t\t\t\tOSAL_CPU_TO_LE16(p_tun->port_vxlan_udp_port);\n \t}\n \n-\tif (OSAL_TEST_BIT(ECORE_MODE_L2GRE_TUNN, &tunn_mode))\n+\tif (OSAL_TEST_BIT(ECORE_MODE_L2GRE_TUNN, &p_tun->tunn_mode))\n \t\tp_tunn_cfg->tx_enable_l2gre = 1;\n \n-\tif (OSAL_TEST_BIT(ECORE_MODE_IPGRE_TUNN, &tunn_mode))\n+\tif (OSAL_TEST_BIT(ECORE_MODE_IPGRE_TUNN, &p_tun->tunn_mode))\n \t\tp_tunn_cfg->tx_enable_ipgre = 1;\n \n-\tif (OSAL_TEST_BIT(ECORE_MODE_VXLAN_TUNN, &tunn_mode))\n+\tif (OSAL_TEST_BIT(ECORE_MODE_VXLAN_TUNN, &p_tun->tunn_mode))\n \t\tp_tunn_cfg->tx_enable_vxlan = 1;\n \n \tif (ECORE_IS_BB_A0(p_hwfn->p_dev)) {\n@@ -306,21 +321,24 @@ ecore_tunn_set_pf_start_params(struct ecore_hwfn *p_hwfn,\n \t}\n \n \tif (p_src->update_geneve_udp_port) {\n+\t\tp_tun->port_geneve_udp_port = p_src->geneve_udp_port;\n \t\tp_tunn_cfg->set_geneve_udp_port_flg = 1;\n \t\tp_tunn_cfg->geneve_udp_port =\n-\t\t OSAL_CPU_TO_LE16(p_src->geneve_udp_port);\n+\t\t\t\tOSAL_CPU_TO_LE16(p_tun->port_geneve_udp_port);\n \t}\n \n-\tif (OSAL_TEST_BIT(ECORE_MODE_L2GENEVE_TUNN, &tunn_mode))\n+\tif (OSAL_TEST_BIT(ECORE_MODE_L2GENEVE_TUNN, &p_tun->tunn_mode))\n \t\tp_tunn_cfg->tx_enable_l2geneve = 1;\n \n-\tif (OSAL_TEST_BIT(ECORE_MODE_IPGENEVE_TUNN, &tunn_mode))\n+\tif (OSAL_TEST_BIT(ECORE_MODE_IPGENEVE_TUNN, &p_tun->tunn_mode))\n \t\tp_tunn_cfg->tx_enable_ipgeneve = 1;\n \n \ttype = ecore_tunn_get_clss_type(p_src->tunn_clss_l2geneve);\n-\tp_tunn_cfg->tunnel_clss_l2geneve = type;\n+\tp_tun->tunn_clss_l2geneve = type;\n+\tp_tunn_cfg->tunnel_clss_l2geneve = p_tun->tunn_clss_l2geneve;\n \ttype = ecore_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);\n-\tp_tunn_cfg->tunnel_clss_ipgeneve = type;\n+\tp_tun->tunn_clss_ipgeneve = type;\n+\tp_tunn_cfg->tunnel_clss_ipgeneve = p_tun->tunn_clss_ipgeneve;\n }\n \n enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,\n@@ -420,9 +438,16 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,\n \trc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);\n \n \tif (p_tunn) {\n+\t\tif (p_tunn->update_vxlan_udp_port)\n+\t\t\tecore_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t\t\t p_tunn->vxlan_udp_port);\n+\n+\t\tif (p_tunn->update_geneve_udp_port)\n+\t\t\tecore_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t\t\t p_tunn->geneve_udp_port);\n+\n \t\tecore_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,\n \t\t\t\t p_tunn->tunn_mode);\n-\t\tp_hwfn->p_dev->tunn_mode = p_tunn->tunn_mode;\n \t}\n \n \treturn rc;\n@@ -529,12 +554,12 @@ ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn,\n \tif (p_tunn->update_vxlan_udp_port)\n \t\tecore_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,\n \t\t\t\t\t p_tunn->vxlan_udp_port);\n+\n \tif (p_tunn->update_geneve_udp_port)\n \t\tecore_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,\n \t\t\t\t\t p_tunn->geneve_udp_port);\n \n \tecore_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode);\n-\tp_hwfn->p_dev->tunn_mode = p_tunn->tunn_mode;\n \n \treturn rc;\n }\ndiff --git a/drivers/net/qede/qede_if.h b/drivers/net/qede/qede_if.h\nindex bfd96d6..baa8476 100644\n--- a/drivers/net/qede/qede_if.h\n+++ b/drivers/net/qede/qede_if.h\n@@ -43,6 +43,11 @@ struct qed_dev_info {\n \tuint8_t mf_mode;\n \tbool tx_switching;\n \tu16 mtu;\n+\n+\t/* Out param for qede */\n+\tbool vxlan_enable;\n+\tbool gre_enable;\n+\tbool geneve_enable;\n };\n \n enum qed_sb_type {\ndiff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c\nindex a932c5f..e7195b4 100644\n--- a/drivers/net/qede/qede_main.c\n+++ b/drivers/net/qede/qede_main.c\n@@ -325,8 +325,26 @@ static int\n qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info)\n {\n \tstruct ecore_ptt *ptt = NULL;\n+\tstruct ecore_tunnel_info *tun = &edev->tunnel;\n \n \tmemset(dev_info, 0, sizeof(struct qed_dev_info));\n+\n+\tif (tun->tunn_mode & OSAL_BIT(ECORE_MODE_VXLAN_TUNN) &&\n+\t tun->tunn_clss_vxlan == ECORE_TUNN_CLSS_MAC_VLAN)\n+\t\tdev_info->vxlan_enable = true;\n+\n+\tif (tun->tunn_mode & OSAL_BIT(ECORE_MODE_L2GRE_TUNN) &&\n+\t tun->tunn_mode & OSAL_BIT(ECORE_MODE_IPGRE_TUNN) &&\n+\t tun->tunn_clss_l2gre == ECORE_TUNN_CLSS_MAC_VLAN &&\n+\t tun->tunn_clss_ipgre == ECORE_TUNN_CLSS_MAC_VLAN)\n+\t\tdev_info->gre_enable = true;\n+\n+\tif (tun->tunn_mode & OSAL_BIT(ECORE_MODE_L2GENEVE_TUNN) &&\n+\t tun->tunn_mode & OSAL_BIT(ECORE_MODE_IPGENEVE_TUNN) &&\n+\t tun->tunn_clss_l2geneve == ECORE_TUNN_CLSS_MAC_VLAN &&\n+\t tun->tunn_clss_ipgeneve == ECORE_TUNN_CLSS_MAC_VLAN)\n+\t\tdev_info->geneve_enable = true;\n+\n \tdev_info->num_hwfns = edev->num_hwfns;\n \tdev_info->is_mf_default = IS_MF_DEFAULT(&edev->hwfns[0]);\n \tdev_info->mtu = ECORE_LEADING_HWFN(edev)->hw_info.mtu;\n", "prefixes": [ "dpdk-dev", "v3", "30/61" ] }