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GET /api/patches/21533/?format=api
{ "id": 21533, "url": "http://patches.dpdk.org/api/patches/21533/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20170307113217.11077-2-bruce.richardson@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20170307113217.11077-2-bruce.richardson@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20170307113217.11077-2-bruce.richardson@intel.com", "date": "2017-03-07T11:32:04", "name": "[dpdk-dev,v2,01/14] ring: remove split cacheline build setting", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f9fc073b947a3ca5156576037546e5190202bce5", "submitter": { "id": 20, "url": "http://patches.dpdk.org/api/people/20/?format=api", "name": "Bruce Richardson", "email": "bruce.richardson@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20170307113217.11077-2-bruce.richardson@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/21533/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/21533/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 92E56BD30;\n\tTue, 7 Mar 2017 12:33:35 +0100 (CET)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id B355A5927\n\tfor <dev@dpdk.org>; Tue, 7 Mar 2017 12:33:19 +0100 (CET)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t07 Mar 2017 03:33:00 -0800", "from sivswdev01.ir.intel.com ([10.237.217.45])\n\tby FMSMGA003.fm.intel.com with ESMTP; 07 Mar 2017 03:32:58 -0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.35,258,1484035200\"; d=\"scan'208\";a=\"831864187\"", "From": "Bruce Richardson <bruce.richardson@intel.com>", "To": "olivier.matz@6wind.com", "Cc": "jerin.jacob@caviumnetworks.com, dev@dpdk.org,\n\tBruce Richardson <bruce.richardson@intel.com>", "Date": "Tue, 7 Mar 2017 11:32:04 +0000", "Message-Id": "<20170307113217.11077-2-bruce.richardson@intel.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20170307113217.11077-1-bruce.richardson@intel.com>", "References": "<20170223172407.27664-1-bruce.richardson@intel.com>\n\t<20170307113217.11077-1-bruce.richardson@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 01/14] ring: remove split cacheline build\n\tsetting", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Users compiling DPDK should not need to know or care about the arrangement\nof cachelines in the rte_ring structure. Therefore just remove the build\noption and set the structures to be always split. On platforms with 64B\ncachelines, for improved performance use 128B rather than 64B alignment\nsince it stops the producer and consumer data being on adjacent cachelines.\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n\n---\n\nV2: Limit the cacheline * 2 alignment to platforms with < 128B line size\n---\n config/common_base | 1 -\n doc/guides/rel_notes/release_17_05.rst | 6 ++++++\n lib/librte_ring/rte_ring.c | 2 --\n lib/librte_ring/rte_ring.h | 16 ++++++++++------\n 4 files changed, 16 insertions(+), 9 deletions(-)", "diff": "diff --git a/config/common_base b/config/common_base\nindex aeee13e..099ffda 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -448,7 +448,6 @@ CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y\n #\n CONFIG_RTE_LIBRTE_RING=y\n CONFIG_RTE_LIBRTE_RING_DEBUG=n\n-CONFIG_RTE_RING_SPLIT_PROD_CONS=n\n CONFIG_RTE_RING_PAUSE_REP_COUNT=0\n \n #\ndiff --git a/doc/guides/rel_notes/release_17_05.rst b/doc/guides/rel_notes/release_17_05.rst\nindex e25ea9f..ea45e0c 100644\n--- a/doc/guides/rel_notes/release_17_05.rst\n+++ b/doc/guides/rel_notes/release_17_05.rst\n@@ -110,6 +110,12 @@ API Changes\n Also, make sure to start the actual text at the margin.\n =========================================================\n \n+* **Reworked rte_ring library**\n+\n+ The rte_ring library has been reworked and updated. The following changes\n+ have been made to it:\n+\n+ * removed the build-time setting ``CONFIG_RTE_RING_SPLIT_PROD_CONS``\n \n ABI Changes\n -----------\ndiff --git a/lib/librte_ring/rte_ring.c b/lib/librte_ring/rte_ring.c\nindex ca0a108..4bc6da1 100644\n--- a/lib/librte_ring/rte_ring.c\n+++ b/lib/librte_ring/rte_ring.c\n@@ -127,10 +127,8 @@ rte_ring_init(struct rte_ring *r, const char *name, unsigned count,\n \t/* compilation-time checks */\n \tRTE_BUILD_BUG_ON((sizeof(struct rte_ring) &\n \t\t\t RTE_CACHE_LINE_MASK) != 0);\n-#ifdef RTE_RING_SPLIT_PROD_CONS\n \tRTE_BUILD_BUG_ON((offsetof(struct rte_ring, cons) &\n \t\t\t RTE_CACHE_LINE_MASK) != 0);\n-#endif\n \tRTE_BUILD_BUG_ON((offsetof(struct rte_ring, prod) &\n \t\t\t RTE_CACHE_LINE_MASK) != 0);\n #ifdef RTE_LIBRTE_RING_DEBUG\ndiff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h\nindex 72ccca5..399ae3b 100644\n--- a/lib/librte_ring/rte_ring.h\n+++ b/lib/librte_ring/rte_ring.h\n@@ -139,6 +139,14 @@ struct rte_ring_debug_stats {\n \n struct rte_memzone; /* forward declaration, so as not to require memzone.h */\n \n+#if RTE_CACHE_LINE_SIZE < 128\n+#define PROD_ALIGN (RTE_CACHE_LINE_SIZE * 2)\n+#define CONS_ALIGN (RTE_CACHE_LINE_SIZE * 2)\n+#else\n+#define PROD_ALIGN RTE_CACHE_LINE_SIZE\n+#define CONS_ALIGN RTE_CACHE_LINE_SIZE\n+#endif\n+\n /**\n * An RTE ring structure.\n *\n@@ -168,7 +176,7 @@ struct rte_ring {\n \t\tuint32_t mask; /**< Mask (size-1) of ring. */\n \t\tvolatile uint32_t head; /**< Producer head. */\n \t\tvolatile uint32_t tail; /**< Producer tail. */\n-\t} prod __rte_cache_aligned;\n+\t} prod __rte_aligned(PROD_ALIGN);\n \n \t/** Ring consumer status. */\n \tstruct cons {\n@@ -177,11 +185,7 @@ struct rte_ring {\n \t\tuint32_t mask; /**< Mask (size-1) of ring. */\n \t\tvolatile uint32_t head; /**< Consumer head. */\n \t\tvolatile uint32_t tail; /**< Consumer tail. */\n-#ifdef RTE_RING_SPLIT_PROD_CONS\n-\t} cons __rte_cache_aligned;\n-#else\n-\t} cons;\n-#endif\n+\t} cons __rte_aligned(CONS_ALIGN);\n \n #ifdef RTE_LIBRTE_RING_DEBUG\n \tstruct rte_ring_debug_stats stats[RTE_MAX_LCORE];\n", "prefixes": [ "dpdk-dev", "v2", "01/14" ] }