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{
    "id": 21386,
    "url": "http://patches.dpdk.org/api/patches/21386/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1488562101-6658-34-git-send-email-jerin.jacob@caviumnetworks.com/",
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    "msgid": "<1488562101-6658-34-git-send-email-jerin.jacob@caviumnetworks.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1488562101-6658-34-git-send-email-jerin.jacob@caviumnetworks.com",
    "date": "2017-03-03T17:28:15",
    "name": "[dpdk-dev,33/39] app/test: octeontx queue based two stage sched type test",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "5769d95c71301a3701e3011dbdd1b2dfb7824b6f",
    "submitter": {
        "id": 305,
        "url": "http://patches.dpdk.org/api/people/305/?format=api",
        "name": "Jerin Jacob",
        "email": "jerin.jacob@caviumnetworks.com"
    },
    "delegate": {
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        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
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    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/21386/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/21386/checks/",
    "tags": {},
    "related": [],
    "headers": {
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            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id C5E0CFB30;\n\tFri,  3 Mar 2017 18:31:13 +0100 (CET)",
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        "Authentication-Results": "dpdk.org; dkim=none (message not signed)\n\theader.d=none;dpdk.org; dmarc=none action=none\n\theader.from=caviumnetworks.com;",
        "From": "Jerin Jacob <jerin.jacob@caviumnetworks.com>",
        "To": "dev@dpdk.org",
        "Cc": "thomas.monjalon@6wind.com, bruce.richardson@intel.com,\n\tharry.van.haaren@intel.com, hemant.agrawal@nxp.com, gage.eads@intel.com, \n\tnipun.gupta@nxp.com, santosh.shukla@caviumnetworks.com,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>",
        "Date": "Fri,  3 Mar 2017 22:58:15 +0530",
        "Message-Id": "<1488562101-6658-34-git-send-email-jerin.jacob@caviumnetworks.com>",
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        "Subject": "[dpdk-dev] [PATCH 33/39] app/test: octeontx queue based two stage\n\tsched type test",
        "X-BeenThere": "dev@dpdk.org",
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        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
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    "content": "Add queue based two stage pipeline test with all combination\nof schedule types.\n\nSigned-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>\n---\n app/test/test_eventdev_octeontx.c | 169 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 169 insertions(+)",
    "diff": "diff --git a/app/test/test_eventdev_octeontx.c b/app/test/test_eventdev_octeontx.c\nindex e17bc82..2265576 100644\n--- a/app/test/test_eventdev_octeontx.c\n+++ b/app/test/test_eventdev_octeontx.c\n@@ -952,6 +952,157 @@ test_multi_port_flow_parallel_to_parallel(void)\n \t\t\t\tRTE_SCHED_TYPE_PARALLEL);\n }\n \n+static int\n+worker_group_based_pipeline(void *arg)\n+{\n+\tstruct test_core_param *param = arg;\n+\tstruct rte_event ev;\n+\tuint16_t valid_event;\n+\tuint8_t port = param->port;\n+\tuint8_t new_sched_type = param->sched_type;\n+\trte_atomic32_t *total_events = param->total_events;\n+\tuint64_t dequeue_tmo_ticks = param->dequeue_tmo_ticks;\n+\n+\twhile (rte_atomic32_read(total_events) > 0) {\n+\t\tvalid_event = rte_event_dequeue_burst(evdev, port, &ev, 1,\n+\t\t\t\t\tdequeue_tmo_ticks);\n+\t\tif (!valid_event)\n+\t\t\tcontinue;\n+\n+\t\t/* Events from stage 0(group 0) */\n+\t\tif (ev.queue_id == 0) {\n+\t\t\t/* Move to atomic flow to maintain the ordering */\n+\t\t\tev.flow_id = 0x2;\n+\t\t\tev.event_type = RTE_EVENT_TYPE_CPU;\n+\t\t\tev.sched_type = new_sched_type;\n+\t\t\tev.queue_id = 1; /* Stage 1*/\n+\t\t\tev.op = RTE_EVENT_OP_FORWARD;\n+\t\t\trte_event_enqueue_burst(evdev, port, &ev, 1);\n+\t\t} else if (ev.queue_id == 1) { /* Events from stage 1(group 1)*/\n+\t\t\tif (seqn_list_update(ev.mbuf->seqn) == TEST_SUCCESS) {\n+\t\t\t\trte_pktmbuf_free(ev.mbuf);\n+\t\t\t\trte_atomic32_sub(total_events, 1);\n+\t\t\t} else {\n+\t\t\t\tprintf(\"Failed to update seqn_list\\n\");\n+\t\t\t\treturn TEST_FAILED;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tprintf(\"Invalid ev.queue_id = %d\\n\", ev.queue_id);\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\t}\n+\n+\n+\treturn 0;\n+}\n+\n+static int\n+test_multiport_queue_sched_type_test(uint8_t in_sched_type,\n+\t\t\tuint8_t out_sched_type)\n+{\n+\tconst unsigned int total_events = MAX_EVENTS;\n+\tuint8_t nr_ports;\n+\tint ret;\n+\n+\tnr_ports = RTE_MIN(rte_event_port_count(evdev), rte_lcore_count() - 1);\n+\n+\tif (rte_event_queue_count(evdev) < 2 ||  !nr_ports) {\n+\t\tprintf(\"%s: Not enough queues=%d ports=%d or workers=%d\\n\",\n+\t\t\t __func__, rte_event_queue_count(evdev),\n+\t\t\trte_event_port_count(evdev), rte_lcore_count() - 1);\n+\t\treturn TEST_SUCCESS;\n+\t}\n+\n+\t/* Injects events with m->seqn=0 to total_events */\n+\tret = inject_events(\n+\t\t0x1 /*flow_id */,\n+\t\tRTE_EVENT_TYPE_CPU /* event_type */,\n+\t\t0 /* sub_event_type (stage 0) */,\n+\t\tin_sched_type,\n+\t\t0 /* queue */,\n+\t\t0 /* port */,\n+\t\ttotal_events /* events */);\n+\tif (ret)\n+\t\treturn TEST_FAILED;\n+\n+\tret = launch_workers_and_wait(worker_group_based_pipeline,\n+\t\t\t\t\tworker_group_based_pipeline,\n+\t\t\t\t\ttotal_events, nr_ports, out_sched_type);\n+\tif (ret)\n+\t\treturn TEST_FAILED;\n+\n+\tif (in_sched_type != RTE_SCHED_TYPE_PARALLEL &&\n+\t\t\tout_sched_type == RTE_SCHED_TYPE_ATOMIC) {\n+\t\t/* Check the events order maintained or not */\n+\t\treturn seqn_list_check(total_events);\n+\t}\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_multi_port_queue_ordered_to_atomic(void)\n+{\n+\t/* Ingress event order test */\n+\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ORDERED,\n+\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n+}\n+\n+static int\n+test_multi_port_queue_ordered_to_ordered(void)\n+{\n+\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ORDERED,\n+\t\t\t\tRTE_SCHED_TYPE_ORDERED);\n+}\n+\n+static int\n+test_multi_port_queue_ordered_to_parallel(void)\n+{\n+\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ORDERED,\n+\t\t\t\tRTE_SCHED_TYPE_PARALLEL);\n+}\n+\n+static int\n+test_multi_port_queue_atomic_to_atomic(void)\n+{\n+\t/* Ingress event order test */\n+\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ATOMIC,\n+\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n+}\n+\n+static int\n+test_multi_port_queue_atomic_to_ordered(void)\n+{\n+\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ATOMIC,\n+\t\t\t\tRTE_SCHED_TYPE_ORDERED);\n+}\n+\n+static int\n+test_multi_port_queue_atomic_to_parallel(void)\n+{\n+\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ATOMIC,\n+\t\t\t\tRTE_SCHED_TYPE_PARALLEL);\n+}\n+\n+static int\n+test_multi_port_queue_parallel_to_atomic(void)\n+{\n+\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_PARALLEL,\n+\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n+}\n+\n+static int\n+test_multi_port_queue_parallel_to_ordered(void)\n+{\n+\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_PARALLEL,\n+\t\t\t\tRTE_SCHED_TYPE_ORDERED);\n+}\n+\n+static int\n+test_multi_port_queue_parallel_to_parallel(void)\n+{\n+\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_PARALLEL,\n+\t\t\t\tRTE_SCHED_TYPE_PARALLEL);\n+}\n static struct unit_test_suite eventdev_octeontx_testsuite  = {\n \t.suite_name = \"eventdev octeontx unit test suite\",\n \t.setup = testsuite_setup,\n@@ -991,6 +1142,24 @@ static struct unit_test_suite eventdev_octeontx_testsuite  = {\n \t\t\ttest_multi_port_flow_parallel_to_ordered),\n \t\tTEST_CASE_ST(eventdev_setup, eventdev_teardown,\n \t\t\ttest_multi_port_flow_parallel_to_parallel),\n+\t\tTEST_CASE_ST(eventdev_setup, eventdev_teardown,\n+\t\t\ttest_multi_port_queue_ordered_to_atomic),\n+\t\tTEST_CASE_ST(eventdev_setup, eventdev_teardown,\n+\t\t\ttest_multi_port_queue_ordered_to_ordered),\n+\t\tTEST_CASE_ST(eventdev_setup, eventdev_teardown,\n+\t\t\ttest_multi_port_queue_ordered_to_parallel),\n+\t\tTEST_CASE_ST(eventdev_setup, eventdev_teardown,\n+\t\t\ttest_multi_port_queue_atomic_to_atomic),\n+\t\tTEST_CASE_ST(eventdev_setup, eventdev_teardown,\n+\t\t\ttest_multi_port_queue_atomic_to_ordered),\n+\t\tTEST_CASE_ST(eventdev_setup, eventdev_teardown,\n+\t\t\ttest_multi_port_queue_atomic_to_parallel),\n+\t\tTEST_CASE_ST(eventdev_setup, eventdev_teardown,\n+\t\t\ttest_multi_port_queue_parallel_to_atomic),\n+\t\tTEST_CASE_ST(eventdev_setup, eventdev_teardown,\n+\t\t\ttest_multi_port_queue_parallel_to_ordered),\n+\t\tTEST_CASE_ST(eventdev_setup, eventdev_teardown,\n+\t\t\ttest_multi_port_queue_parallel_to_parallel),\n \t\tTEST_CASES_END() /**< NULL terminate unit test array */\n \t}\n };\n",
    "prefixes": [
        "dpdk-dev",
        "33/39"
    ]
}