Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/21196/?format=api
{ "id": 21196, "url": "http://patches.dpdk.org/api/patches/21196/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1488545223-25739-18-git-send-email-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1488545223-25739-18-git-send-email-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1488545223-25739-18-git-send-email-hemant.agrawal@nxp.com", "date": "2017-03-03T12:46:34", "name": "[dpdk-dev,PATCHv8,17/46] bus/fslmc: dpio portal driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "dfe598b38c6714f5bc5966cc82700b03d52f072d", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1488545223-25739-18-git-send-email-hemant.agrawal@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/21196/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/21196/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 19688F95C;\n\tFri, 3 Mar 2017 08:14:37 +0100 (CET)", "from NAM01-BN3-obe.outbound.protection.outlook.com\n\t(mail-bn3nam01on0049.outbound.protection.outlook.com [104.47.33.49])\n\tby dpdk.org (Postfix) with ESMTP id 6BC26F60E\n\tfor <dev@dpdk.org>; Fri, 3 Mar 2017 08:14:04 +0100 (CET)", "from BN3PR0301CA0084.namprd03.prod.outlook.com (10.160.152.180) by\n\tDM2PR0301MB0734.namprd03.prod.outlook.com (10.160.97.142) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.933.12; Fri, 3 Mar 2017 07:14:02 +0000", "from BY2FFO11OLC010.protection.gbl (2a01:111:f400:7c0c::198) by\n\tBN3PR0301CA0084.outlook.office365.com (2a01:111:e400:401e::52) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.947.12 via\n\tFrontend Transport; Fri, 3 Mar 2017 07:14:01 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBY2FFO11OLC010.mail.protection.outlook.com (10.1.15.21) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.933.11\n\tvia Frontend Transport; Fri, 3 Mar 2017 07:14:00 +0000", "from bf-netperf1.idc ([10.232.134.28])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv237D50K005035; Fri, 3 Mar 2017 00:13:58 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; caviumnetworks.com;\n\tdkim=none (message not signed)\n\theader.d=none; caviumnetworks.com;\n\tdmarc=fail action=none header.from=nxp.com; ", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,\n\t<shreyansh.jain@nxp.com>, <john.mcnamara@intel.com>,\n\t<ferruh.yigit@intel.com>, <jerin.jacob@caviumnetworks.com>", "Date": "Fri, 3 Mar 2017 18:16:34 +0530", "Message-ID": "<1488545223-25739-18-git-send-email-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1488545223-25739-1-git-send-email-hemant.agrawal@nxp.com>", "References": "<1487205586-6785-1-git-send-email-hemant.agrawal@nxp.com>\n\t<1488545223-25739-1-git-send-email-hemant.agrawal@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131329988410298327;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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\n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM2PR0301MB0734", "Subject": "[dpdk-dev] [PATCHv8 17/46] bus/fslmc: dpio portal driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The portal driver is bound to DPIO objects discovered on the fsl-mc bus and\nprovides services that:\n- allow other drivers, such as the Ethernet driver, to enqueue and dequeue\n frames for their respective objects\n\nA system will typically allocate 1 DPIO object per CPU to allow queuing\noperations to happen simultaneously across all CPUs.\n\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n drivers/bus/Makefile | 2 +\n drivers/bus/fslmc/Makefile | 1 +\n drivers/bus/fslmc/fslmc_vfio.c | 17 +-\n drivers/bus/fslmc/fslmc_vfio.h | 5 +\n drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 364 ++++++++++++++++++++++++++++\n drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 60 +++++\n drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 68 ++++++\n drivers/bus/fslmc/rte_bus_fslmc_version.map | 2 +\n 8 files changed, 518 insertions(+), 1 deletion(-)\n create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\n create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\n create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h", "diff": "diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile\nindex 60e9764..8f7864b 100644\n--- a/drivers/bus/Makefile\n+++ b/drivers/bus/Makefile\n@@ -31,6 +31,8 @@\n \n include $(RTE_SDK)/mk/rte.vars.mk\n \n+CONFIG_RTE_LIBRTE_FSLMC_BUS = $(CONFIG_RTE_LIBRTE_DPAA2_PMD)\n+\n DIRS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc\n \n include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile\nindex 90edaad..10740b5 100644\n--- a/drivers/bus/fslmc/Makefile\n+++ b/drivers/bus/fslmc/Makefile\n@@ -68,6 +68,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += \\\n mc/dpio.c \\\n mc/mc_sys.c\n \n+SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += portal/dpaa2_hw_dpio.c\n SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc_vfio.c\n SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc_bus.c\n \ndiff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c\nindex 0d4c0a2..2d7bcd9 100644\n--- a/drivers/bus/fslmc/fslmc_vfio.c\n+++ b/drivers/bus/fslmc/fslmc_vfio.c\n@@ -61,6 +61,9 @@\n #include \"rte_fslmc.h\"\n #include \"fslmc_vfio.h\"\n \n+#include \"portal/dpaa2_hw_pvt.h\"\n+#include \"portal/dpaa2_hw_dpio.h\"\n+\n #define VFIO_MAX_CONTAINERS\t1\n \n #define FSLMC_VFIO_LOG(level, fmt, args...) \\\n@@ -261,12 +264,13 @@ int fslmc_vfio_process_group(void)\n \tstruct fslmc_vfio_device *vdev;\n \tstruct vfio_device_info device_info = { .argsz = sizeof(device_info) };\n \tchar *temp_obj, *object_type, *mcp_obj, *dev_name;\n-\tint32_t object_id, i, dev_fd;\n+\tint32_t object_id, i, dev_fd, ret;\n \tDIR *d;\n \tstruct dirent *dir;\n \tchar path[PATH_MAX];\n \tint64_t v_addr;\n \tint ndev_count;\n+\tint dpio_count = 0;\n \tstruct fslmc_vfio_group *group = &vfio_groups[0];\n \tstatic int process_once;\n \n@@ -409,9 +413,20 @@ int fslmc_vfio_process_group(void)\n \n \t\t\tfslmc_bus_add_device(dev);\n \t\t}\n+\t\tif (!strcmp(object_type, \"dpio\")) {\n+\t\t\tret = dpaa2_create_dpio_device(vdev,\n+\t\t\t\t\t\t &device_info,\n+\t\t\t\t\t\t object_id);\n+\t\t\tif (!ret)\n+\t\t\t\tdpio_count++;\n+\t\t}\n \t}\n \tclosedir(d);\n \n+\tret = dpaa2_affine_qbman_swp();\n+\tif (ret)\n+\t\tFSLMC_VFIO_LOG(DEBUG, \"Error in affining qbman swp %d\", ret);\n+\n \treturn 0;\n \n FAILURE:\ndiff --git a/drivers/bus/fslmc/fslmc_vfio.h b/drivers/bus/fslmc/fslmc_vfio.h\nindex 5e58211..39994dd 100644\n--- a/drivers/bus/fslmc/fslmc_vfio.h\n+++ b/drivers/bus/fslmc/fslmc_vfio.h\n@@ -71,4 +71,9 @@ int vfio_dmamap_mem_region(\n int fslmc_vfio_setup_group(void);\n int fslmc_vfio_process_group(void);\n \n+/* create dpio device */\n+int dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev,\n+\t\t\t struct vfio_device_info *obj_info,\n+\t\t\t int object_id);\n+\n #endif /* _FSLMC_VFIO_H_ */\ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\nnew file mode 100644\nindex 0000000..dd6de4c\n--- /dev/null\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\n@@ -0,0 +1,364 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n+ * Copyright (c) 2016 NXP. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Freescale Semiconductor, Inc nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <unistd.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <stdlib.h>\n+#include <fcntl.h>\n+#include <errno.h>\n+#include <stdarg.h>\n+#include <inttypes.h>\n+#include <signal.h>\n+#include <pthread.h>\n+#include <sys/types.h>\n+#include <sys/queue.h>\n+#include <sys/ioctl.h>\n+#include <sys/stat.h>\n+#include <sys/mman.h>\n+#include <sys/syscall.h>\n+\n+#include <rte_mbuf.h>\n+#include <rte_ethdev.h>\n+#include <rte_malloc.h>\n+#include <rte_memcpy.h>\n+#include <rte_string_fns.h>\n+#include <rte_cycles.h>\n+#include <rte_kvargs.h>\n+#include <rte_dev.h>\n+#include <rte_ethdev.h>\n+\n+#include <fslmc_logs.h>\n+#include <fslmc_vfio.h>\n+#include \"dpaa2_hw_pvt.h\"\n+#include \"dpaa2_hw_dpio.h\"\n+\n+#define NUM_HOST_CPUS RTE_MAX_LCORE\n+\n+struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];\n+RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);\n+\n+TAILQ_HEAD(dpio_device_list, dpaa2_dpio_dev);\n+static struct dpio_device_list *dpio_dev_list; /*!< DPIO device list */\n+static uint32_t io_space_count;\n+\n+/*Stashing Macros default for LS208x*/\n+static int dpaa2_core_cluster_base = 0x04;\n+static int dpaa2_cluster_sz = 2;\n+\n+/* For LS208X platform There are four clusters with following mapping:\n+ * Cluster 1 (ID = x04) : CPU0, CPU1;\n+ * Cluster 2 (ID = x05) : CPU2, CPU3;\n+ * Cluster 3 (ID = x06) : CPU4, CPU5;\n+ * Cluster 4 (ID = x07) : CPU6, CPU7;\n+ */\n+/* For LS108X platform There are two clusters with following mapping:\n+ * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;\n+ * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;\n+ */\n+\n+/* Set the STASH Destination depending on Current CPU ID.\n+ * e.g. Valid values of SDEST are 4,5,6,7. Where,\n+ * CPU 0-1 will have SDEST 4\n+ * CPU 2-3 will have SDEST 5.....and so on.\n+ */\n+static int\n+dpaa2_core_cluster_sdest(int cpu_id)\n+{\n+\tint x = cpu_id / dpaa2_cluster_sz;\n+\n+\tif (x > 3)\n+\t\tx = 3;\n+\n+\treturn dpaa2_core_cluster_base + x;\n+}\n+\n+static int\n+configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)\n+{\n+\tstruct qbman_swp_desc p_des;\n+\tstruct dpio_attr attr;\n+\n+\tdpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));\n+\tif (!dpio_dev->dpio) {\n+\t\tPMD_INIT_LOG(ERR, \"Memory allocation failure\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"\\t Allocated DPIO Portal[%p]\", dpio_dev->dpio);\n+\tdpio_dev->dpio->regs = dpio_dev->mc_portal;\n+\tif (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,\n+\t\t &dpio_dev->token)) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate IO space\\n\");\n+\t\tfree(dpio_dev->dpio);\n+\t\treturn -1;\n+\t}\n+\n+\tif (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to reset dpio\\n\");\n+\t\tdpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);\n+\t\tfree(dpio_dev->dpio);\n+\t\treturn -1;\n+\t}\n+\n+\tif (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to Enable dpio\\n\");\n+\t\tdpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);\n+\t\tfree(dpio_dev->dpio);\n+\t\treturn -1;\n+\t}\n+\n+\tif (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,\n+\t\t\t\tdpio_dev->token, &attr)) {\n+\t\tPMD_INIT_LOG(ERR, \"DPIO Get attribute failed\\n\");\n+\t\tdpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);\n+\t\tdpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);\n+\t\tfree(dpio_dev->dpio);\n+\t\treturn -1;\n+\t}\n+\n+\tPMD_INIT_LOG(DEBUG, \"Qbman Portal ID %d\", attr.qbman_portal_id);\n+\tPMD_INIT_LOG(DEBUG, \"Portal CE adr 0x%lX\", attr.qbman_portal_ce_offset);\n+\tPMD_INIT_LOG(DEBUG, \"Portal CI adr 0x%lX\", attr.qbman_portal_ci_offset);\n+\n+\t/* Configure & setup SW portal */\n+\tp_des.block = NULL;\n+\tp_des.idx = attr.qbman_portal_id;\n+\tp_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);\n+\tp_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);\n+\tp_des.irq = -1;\n+\tp_des.qman_version = attr.qbman_version;\n+\n+\tdpio_dev->sw_portal = qbman_swp_init(&p_des);\n+\tif (dpio_dev->sw_portal == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \" QBMan SW Portal Init failed\\n\");\n+\t\tdpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);\n+\t\tfree(dpio_dev->dpio);\n+\t\treturn -1;\n+\t}\n+\n+\tPMD_INIT_LOG(DEBUG, \"QBMan SW Portal 0x%p\\n\", dpio_dev->sw_portal);\n+\n+\treturn 0;\n+}\n+\n+static int\n+dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)\n+{\n+\tint sdest;\n+\tint cpu_id, ret;\n+\n+\t/* Set the Stashing Destination */\n+\tcpu_id = rte_lcore_id();\n+\tif (cpu_id < 0) {\n+\t\tcpu_id = rte_get_master_lcore();\n+\t\tif (cpu_id < 0) {\n+\t\t\tRTE_LOG(ERR, PMD, \"\\tGetting CPU Index failed\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\t/* Set the STASH Destination depending on Current CPU ID.\n+\t * Valid values of SDEST are 4,5,6,7. Where,\n+\t * CPU 0-1 will have SDEST 4\n+\t * CPU 2-3 will have SDEST 5.....and so on.\n+\t */\n+\n+\tsdest = dpaa2_core_cluster_sdest(cpu_id);\n+\tPMD_DRV_LOG(DEBUG, \"Portal= %d CPU= %u SDEST= %d\",\n+\t\t dpio_dev->index, cpu_id, sdest);\n+\n+\tret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,\n+\t\t\t\t\t dpio_dev->token, sdest);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"%d ERROR in SDEST\\n\", ret);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)\n+{\n+\tstruct dpaa2_dpio_dev *dpio_dev = NULL;\n+\tint ret;\n+\n+\t/* Get DPIO dev handle from list using index */\n+\tTAILQ_FOREACH(dpio_dev, dpio_dev_list, next) {\n+\t\tif (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))\n+\t\t\tbreak;\n+\t}\n+\tif (!dpio_dev)\n+\t\treturn NULL;\n+\n+\tPMD_DRV_LOG(DEBUG, \"New Portal=0x%x (%d) affined thread - %lu\",\n+\t\t dpio_dev, dpio_dev->index, syscall(SYS_gettid));\n+\n+\tret = dpaa2_configure_stashing(dpio_dev);\n+\tif (ret)\n+\t\tPMD_DRV_LOG(ERR, \"dpaa2_configure_stashing failed\");\n+\n+\treturn dpio_dev;\n+}\n+\n+int\n+dpaa2_affine_qbman_swp(void)\n+{\n+\tunsigned int lcore_id = rte_lcore_id();\n+\tuint64_t tid = syscall(SYS_gettid);\n+\n+\tif (lcore_id == LCORE_ID_ANY)\n+\t\tlcore_id = rte_get_master_lcore();\n+\t/* if the core id is not supported */\n+\telse if (lcore_id >= RTE_MAX_LCORE)\n+\t\treturn -1;\n+\n+\tif (dpaa2_io_portal[lcore_id].dpio_dev) {\n+\t\tPMD_DRV_LOG(INFO, \"DPAA Portal=0x%x (%d) is being shared\"\n+\t\t\t \" between thread %lu and current %lu\",\n+\t\t\t dpaa2_io_portal[lcore_id].dpio_dev,\n+\t\t\t dpaa2_io_portal[lcore_id].dpio_dev->index,\n+\t\t\t dpaa2_io_portal[lcore_id].net_tid,\n+\t\t\t tid);\n+\t\tRTE_PER_LCORE(_dpaa2_io).dpio_dev\n+\t\t\t= dpaa2_io_portal[lcore_id].dpio_dev;\n+\t\trte_atomic16_inc(&dpaa2_io_portal\n+\t\t\t\t [lcore_id].dpio_dev->ref_count);\n+\t\tdpaa2_io_portal[lcore_id].net_tid = tid;\n+\n+\t\tPMD_DRV_LOG(DEBUG, \"Old Portal=0x%x (%d) affined thread - %lu\",\n+\t\t\t dpaa2_io_portal[lcore_id].dpio_dev,\n+\t\t\t dpaa2_io_portal[lcore_id].dpio_dev->index,\n+\t\t\t tid);\n+\t\treturn 0;\n+\t}\n+\n+\t/* Populate the dpaa2_io_portal structure */\n+\tdpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp();\n+\n+\tif (dpaa2_io_portal[lcore_id].dpio_dev) {\n+\t\tRTE_PER_LCORE(_dpaa2_io).dpio_dev\n+\t\t\t= dpaa2_io_portal[lcore_id].dpio_dev;\n+\t\tdpaa2_io_portal[lcore_id].net_tid = tid;\n+\n+\t\treturn 0;\n+\t} else {\n+\t\treturn -1;\n+\t}\n+}\n+\n+int\n+dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev,\n+\t\t\t struct vfio_device_info *obj_info,\n+\t\tint object_id)\n+{\n+\tstruct dpaa2_dpio_dev *dpio_dev;\n+\tstruct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};\n+\n+\tif (obj_info->num_regions < NUM_DPIO_REGIONS) {\n+\t\tPMD_INIT_LOG(ERR, \"ERROR, Not sufficient number \"\n+\t\t\t\t\"of DPIO regions.\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tif (!dpio_dev_list) {\n+\t\tdpio_dev_list = malloc(sizeof(struct dpio_device_list));\n+\t\tif (!dpio_dev_list) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Memory alloc failed in DPIO list\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\t/* Initialize the DPIO List */\n+\t\tTAILQ_INIT(dpio_dev_list);\n+\t}\n+\n+\tdpio_dev = malloc(sizeof(struct dpaa2_dpio_dev));\n+\tif (!dpio_dev) {\n+\t\tPMD_INIT_LOG(ERR, \"Memory allocation failed for DPIO Device\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tPMD_DRV_LOG(INFO, \"\\t Aloocated DPIO [%p]\", dpio_dev);\n+\tdpio_dev->dpio = NULL;\n+\tdpio_dev->hw_id = object_id;\n+\tdpio_dev->vfio_fd = vdev->fd;\n+\trte_atomic16_init(&dpio_dev->ref_count);\n+\t/* Using single portal for all devices */\n+\tdpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];\n+\n+\treg_info.index = 0;\n+\tif (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {\n+\t\tPMD_INIT_LOG(ERR, \"vfio: error getting region info\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"\\t Region Offset = %llx\", reg_info.offset);\n+\tPMD_DRV_LOG(DEBUG, \"\\t Region Size = %llx\", reg_info.size);\n+\tdpio_dev->ce_size = reg_info.size;\n+\tdpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,\n+\t\t\t\tPROT_WRITE | PROT_READ, MAP_SHARED,\n+\t\t\t\tdpio_dev->vfio_fd, reg_info.offset);\n+\n+\t/* Create Mapping for QBMan Cache Enabled area. This is a fix for\n+\t * SMMU fault for DQRR statshing transaction.\n+\t */\n+\tif (vfio_dmamap_mem_region(dpio_dev->qbman_portal_ce_paddr,\n+\t\t\t\t reg_info.offset, reg_info.size)) {\n+\t\tPMD_INIT_LOG(ERR, \"DMAMAP for Portal CE area failed.\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treg_info.index = 1;\n+\tif (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {\n+\t\tPMD_INIT_LOG(ERR, \"vfio: error getting region info\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"\\t Region Offset = %llx\", reg_info.offset);\n+\tPMD_DRV_LOG(DEBUG, \"\\t Region Size = %llx\", reg_info.size);\n+\tdpio_dev->ci_size = reg_info.size;\n+\tdpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,\n+\t\t\t\tPROT_WRITE | PROT_READ, MAP_SHARED,\n+\t\t\t\tdpio_dev->vfio_fd, reg_info.offset);\n+\n+\tif (configure_dpio_qbman_swp(dpio_dev)) {\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t \"Fail to configure the dpio qbman portal for %d\\n\",\n+\t\t\t dpio_dev->hw_id);\n+\t\treturn -1;\n+\t}\n+\n+\tio_space_count++;\n+\tdpio_dev->index = io_space_count;\n+\tTAILQ_INSERT_HEAD(dpio_dev_list, dpio_dev, next);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\nnew file mode 100644\nindex 0000000..682f3fa\n--- /dev/null\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\n@@ -0,0 +1,60 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n+ * Copyright (c) 2016 NXP. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Freescale Semiconductor, Inc nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _DPAA2_HW_DPIO_H_\n+#define _DPAA2_HW_DPIO_H_\n+\n+#include <mc/fsl_dpio.h>\n+#include <mc/fsl_mc_sys.h>\n+\n+struct dpaa2_io_portal_t {\n+\tstruct dpaa2_dpio_dev *dpio_dev;\n+\tstruct dpaa2_dpio_dev *sec_dpio_dev;\n+\tuint64_t net_tid;\n+\tuint64_t sec_tid;\n+};\n+\n+/*! Global per thread DPIO portal */\n+RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);\n+\n+#define DPAA2_PER_LCORE_DPIO RTE_PER_LCORE(_dpaa2_io).dpio_dev\n+#define DPAA2_PER_LCORE_PORTAL DPAA2_PER_LCORE_DPIO->sw_portal\n+\n+#define DPAA2_PER_LCORE_SEC_DPIO RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev\n+#define DPAA2_PER_LCORE_SEC_PORTAL DPAA2_PER_LCORE_SEC_DPIO->sw_portal\n+\n+/* Affine a DPIO portal to current processing thread */\n+int dpaa2_affine_qbman_swp(void);\n+\n+\n+#endif /* _DPAA2_HW_DPIO_H_ */\ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\nnew file mode 100644\nindex 0000000..6b44314\n--- /dev/null\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n@@ -0,0 +1,68 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n+ * Copyright (c) 2016 NXP. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Freescale Semiconductor, Inc nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _DPAA2_HW_PVT_H_\n+#define _DPAA2_HW_PVT_H_\n+\n+#include <mc/fsl_mc_sys.h>\n+#include <fsl_qbman_portal.h>\n+\n+\n+#define MC_PORTAL_INDEX\t\t0\n+#define NUM_DPIO_REGIONS\t2\n+\n+struct dpaa2_dpio_dev {\n+\tTAILQ_ENTRY(dpaa2_dpio_dev) next;\n+\t\t/**< Pointer to Next device instance */\n+\tuint16_t index; /**< Index of a instance in the list */\n+\trte_atomic16_t ref_count;\n+\t\t/**< How many thread contexts are sharing this.*/\n+\tstruct fsl_mc_io *dpio; /** handle to DPIO portal object */\n+\tuint16_t token;\n+\tstruct qbman_swp *sw_portal; /** SW portal object */\n+\tconst struct qbman_result *dqrr[4];\n+\t\t/**< DQRR Entry for this SW portal */\n+\tvoid *mc_portal; /**< MC Portal for configuring this device */\n+\tuintptr_t qbman_portal_ce_paddr;\n+\t\t/**< Physical address of Cache Enabled Area */\n+\tuintptr_t ce_size; /**< Size of the CE region */\n+\tuintptr_t qbman_portal_ci_paddr;\n+\t\t/**< Physical address of Cache Inhibit Area */\n+\tuintptr_t ci_size; /**< Size of the CI region */\n+\tint32_t\tvfio_fd; /**< File descriptor received via VFIO */\n+\tint32_t hw_id; /**< An unique ID of this DPIO device instance */\n+};\n+\n+/*! Global MCP list */\n+extern void *(*rte_mcp_ptr_list);\n+#endif\ndiff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map\nindex 463c658..2110b71 100644\n--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map\n+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map\n@@ -1,6 +1,7 @@\n DPDK_17.05 {\n \tglobal:\n \n+\tdpaa2_affine_qbman_swp;\n \tdpbp_disable;\n \tdpbp_enable;\n \tdpbp_get_attributes;\n@@ -14,6 +15,7 @@ DPDK_17.05 {\n \tdpio_reset;\n \tdpio_set_stashing_destination;\n \tmc_send_command;\n+\tper_lcore__dpaa2_io;\n \tqbman_check_command_complete;\n \tqbman_eq_desc_clear;\n \tqbman_eq_desc_set_no_orp;\n", "prefixes": [ "dpdk-dev", "PATCHv8", "17/46" ] }