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GET /api/patches/20667/?format=api
{ "id": 20667, "url": "http://patches.dpdk.org/api/patches/20667/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/74798f347a5b1fad28037b713ad83048c227a2ca.1487770570.git.vasilyf@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<74798f347a5b1fad28037b713ad83048c227a2ca.1487770570.git.vasilyf@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/74798f347a5b1fad28037b713ad83048c227a2ca.1487770570.git.vasilyf@mellanox.com", "date": "2017-02-22T13:42:12", "name": "[dpdk-dev,v2,1/2] net/mlx4: split the definitions to the header file", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "574a99401052573b73418952f2ba55033c9f8105", "submitter": { "id": 615, "url": "http://patches.dpdk.org/api/people/615/?format=api", "name": "Vasily Philipov", "email": "vasilyf@mellanox.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/74798f347a5b1fad28037b713ad83048c227a2ca.1487770570.git.vasilyf@mellanox.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/20667/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/20667/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 8F7702B88;\n\tWed, 22 Feb 2017 14:42:55 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id 75E54FE5\n\tfor <dev@dpdk.org>; Wed, 22 Feb 2017 14:42:53 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n\tvasilyf@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 22 Feb 2017 15:42:47 +0200", "from r-aa-dragon19.mtr.labs.mlnx (r-aa-dragon19.mtr.labs.mlnx\n\t[10.209.68.156])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v1MDglsk017782;\n\tWed, 22 Feb 2017 15:42:47 +0200", "from r-aa-dragon19.mtr.labs.mlnx (localhost [127.0.0.1])\n\tby r-aa-dragon19.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id\n\tv1MDglYC014063; Wed, 22 Feb 2017 13:42:47 GMT", "(from vasilyf@localhost)\n\tby r-aa-dragon19.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id\n\tv1MDglG3014062; Wed, 22 Feb 2017 13:42:47 GMT" ], "From": "Vasily Philipov <vasilyf@mellanox.com>", "To": "dev@dpdk.org", "Cc": "Vasily Philipov <vasilyf@mellanox.com>,\n\tAdrien Mazarguil <adrien.mazarguil@6wind.com>,\n\tNelio Laranjeiro <nelio.laranjeiro@6wind.com>", "Date": "Wed, 22 Feb 2017 13:42:12 +0000", "Message-Id": "<74798f347a5b1fad28037b713ad83048c227a2ca.1487770570.git.vasilyf@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<74798f347a5b1fad28037b713ad83048c227a2ca.1487685098.git.vasilyf@mellanox.com>", "References": "<74798f347a5b1fad28037b713ad83048c227a2ca.1487685098.git.vasilyf@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 1/2] net/mlx4: split the definitions to the\n\theader file", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Make some structs/defines visible from different source files by placing\nthem into mlx4.h header.\n\nSigned-off-by: Vasily Philipov <vasilyf@mellanox.com>\n---\n drivers/net/mlx4/mlx4.c | 183 ++--------------------------------------------\n drivers/net/mlx4/mlx4.h | 187 +++++++++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 189 insertions(+), 181 deletions(-)", "diff": "diff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c\nindex 79efaaa..82ccac8 100644\n--- a/drivers/net/mlx4/mlx4.c\n+++ b/drivers/net/mlx4/mlx4.c\n@@ -1,8 +1,8 @@\n /*-\n * BSD LICENSE\n *\n- * Copyright 2012-2015 6WIND S.A.\n- * Copyright 2012 Mellanox.\n+ * Copyright 2012-2017 6WIND S.A.\n+ * Copyright 2012-2017 Mellanox.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n@@ -68,10 +68,6 @@\n #pragma GCC diagnostic error \"-Wpedantic\"\n #endif\n \n-/* DPDK headers don't like -pedantic. */\n-#ifdef PEDANTIC\n-#pragma GCC diagnostic ignored \"-Wpedantic\"\n-#endif\n #include <rte_ether.h>\n #include <rte_ethdev.h>\n #include <rte_dev.h>\n@@ -86,9 +82,6 @@\n #include <rte_log.h>\n #include <rte_alarm.h>\n #include <rte_memory.h>\n-#ifdef PEDANTIC\n-#pragma GCC diagnostic error \"-Wpedantic\"\n-#endif\n \n /* Generated configuration header. */\n #include \"mlx4_autoconf.h\"\n@@ -96,21 +89,6 @@\n /* PMD header. */\n #include \"mlx4.h\"\n \n-/* Runtime logging through RTE_LOG() is enabled when not in debugging mode.\n- * Intermediate LOG_*() macros add the required end-of-line characters. */\n-#ifndef NDEBUG\n-#define INFO(...) DEBUG(__VA_ARGS__)\n-#define WARN(...) DEBUG(__VA_ARGS__)\n-#define ERROR(...) DEBUG(__VA_ARGS__)\n-#else\n-#define LOG__(level, m, ...) \\\n-\tRTE_LOG(level, PMD, MLX4_DRIVER_NAME \": \" m \"%c\", __VA_ARGS__)\n-#define LOG_(level, ...) LOG__(level, __VA_ARGS__, '\\n')\n-#define INFO(...) LOG_(INFO, __VA_ARGS__)\n-#define WARN(...) LOG_(WARNING, __VA_ARGS__)\n-#define ERROR(...) LOG_(ERR, __VA_ARGS__)\n-#endif\n-\n /* Convenience macros for accessing mbuf fields. */\n #define NEXT(m) ((m)->next)\n #define DATA_LEN(m) ((m)->data_len)\n@@ -137,157 +115,6 @@\n \t (((val) & (from)) / ((from) / (to))) : \\\n \t (((val) & (from)) * ((to) / (from))))\n \n-struct mlx4_rxq_stats {\n-\tunsigned int idx; /**< Mapping index. */\n-#ifdef MLX4_PMD_SOFT_COUNTERS\n-\tuint64_t ipackets; /**< Total of successfully received packets. */\n-\tuint64_t ibytes; /**< Total of successfully received bytes. */\n-#endif\n-\tuint64_t idropped; /**< Total of packets dropped when RX ring full. */\n-\tuint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */\n-};\n-\n-struct mlx4_txq_stats {\n-\tunsigned int idx; /**< Mapping index. */\n-#ifdef MLX4_PMD_SOFT_COUNTERS\n-\tuint64_t opackets; /**< Total of successfully sent packets. */\n-\tuint64_t obytes; /**< Total of successfully sent bytes. */\n-#endif\n-\tuint64_t odropped; /**< Total of packets not sent when TX ring full. */\n-};\n-\n-/* RX element (scattered packets). */\n-struct rxq_elt_sp {\n-\tstruct ibv_recv_wr wr; /* Work Request. */\n-\tstruct ibv_sge sges[MLX4_PMD_SGE_WR_N]; /* Scatter/Gather Elements. */\n-\tstruct rte_mbuf *bufs[MLX4_PMD_SGE_WR_N]; /* SGEs buffers. */\n-};\n-\n-/* RX element. */\n-struct rxq_elt {\n-\tstruct ibv_recv_wr wr; /* Work Request. */\n-\tstruct ibv_sge sge; /* Scatter/Gather Element. */\n-\t/* mbuf pointer is derived from WR_ID(wr.wr_id).offset. */\n-};\n-\n-/* RX queue descriptor. */\n-struct rxq {\n-\tstruct priv *priv; /* Back pointer to private data. */\n-\tstruct rte_mempool *mp; /* Memory Pool for allocations. */\n-\tstruct ibv_mr *mr; /* Memory Region (for mp). */\n-\tstruct ibv_cq *cq; /* Completion Queue. */\n-\tstruct ibv_qp *qp; /* Queue Pair. */\n-\tstruct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */\n-\tstruct ibv_exp_cq_family *if_cq; /* CQ interface. */\n-\t/*\n-\t * Each VLAN ID requires a separate flow steering rule.\n-\t */\n-\tBITFIELD_DECLARE(mac_configured, uint32_t, MLX4_MAX_MAC_ADDRESSES);\n-\tstruct ibv_flow *mac_flow[MLX4_MAX_MAC_ADDRESSES][MLX4_MAX_VLAN_IDS];\n-\tstruct ibv_flow *promisc_flow; /* Promiscuous flow. */\n-\tstruct ibv_flow *allmulti_flow; /* Multicast flow. */\n-\tunsigned int port_id; /* Port ID for incoming packets. */\n-\tunsigned int elts_n; /* (*elts)[] length. */\n-\tunsigned int elts_head; /* Current index in (*elts)[]. */\n-\tunion {\n-\t\tstruct rxq_elt_sp (*sp)[]; /* Scattered RX elements. */\n-\t\tstruct rxq_elt (*no_sp)[]; /* RX elements. */\n-\t} elts;\n-\tunsigned int sp:1; /* Use scattered RX elements. */\n-\tunsigned int csum:1; /* Enable checksum offloading. */\n-\tunsigned int csum_l2tun:1; /* Same for L2 tunnels. */\n-\tstruct mlx4_rxq_stats stats; /* RX queue counters. */\n-\tunsigned int socket; /* CPU socket ID for allocations. */\n-\tstruct ibv_exp_res_domain *rd; /* Resource Domain. */\n-};\n-\n-/* TX element. */\n-struct txq_elt {\n-\tstruct rte_mbuf *buf;\n-};\n-\n-/* Linear buffer type. It is used when transmitting buffers with too many\n- * segments that do not fit the hardware queue (see max_send_sge).\n- * Extra segments are copied (linearized) in such buffers, replacing the\n- * last SGE during TX.\n- * The size is arbitrary but large enough to hold a jumbo frame with\n- * 8 segments considering mbuf.buf_len is about 2048 bytes. */\n-typedef uint8_t linear_t[16384];\n-\n-/* TX queue descriptor. */\n-struct txq {\n-\tstruct priv *priv; /* Back pointer to private data. */\n-\tstruct {\n-\t\tconst struct rte_mempool *mp; /* Cached Memory Pool. */\n-\t\tstruct ibv_mr *mr; /* Memory Region (for mp). */\n-\t\tuint32_t lkey; /* mr->lkey */\n-\t} mp2mr[MLX4_PMD_TX_MP_CACHE]; /* MP to MR translation table. */\n-\tstruct ibv_cq *cq; /* Completion Queue. */\n-\tstruct ibv_qp *qp; /* Queue Pair. */\n-\tstruct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */\n-\tstruct ibv_exp_cq_family *if_cq; /* CQ interface. */\n-#if MLX4_PMD_MAX_INLINE > 0\n-\tuint32_t max_inline; /* Max inline send size <= MLX4_PMD_MAX_INLINE. */\n-#endif\n-\tunsigned int elts_n; /* (*elts)[] length. */\n-\tstruct txq_elt (*elts)[]; /* TX elements. */\n-\tunsigned int elts_head; /* Current index in (*elts)[]. */\n-\tunsigned int elts_tail; /* First element awaiting completion. */\n-\tunsigned int elts_comp; /* Number of completion requests. */\n-\tunsigned int elts_comp_cd; /* Countdown for next completion request. */\n-\tunsigned int elts_comp_cd_init; /* Initial value for countdown. */\n-\tstruct mlx4_txq_stats stats; /* TX queue counters. */\n-\tlinear_t (*elts_linear)[]; /* Linearized buffers. */\n-\tstruct ibv_mr *mr_linear; /* Memory Region for linearized buffers. */\n-\tunsigned int socket; /* CPU socket ID for allocations. */\n-\tstruct ibv_exp_res_domain *rd; /* Resource Domain. */\n-};\n-\n-struct priv {\n-\tstruct rte_eth_dev *dev; /* Ethernet device. */\n-\tstruct ibv_context *ctx; /* Verbs context. */\n-\tstruct ibv_device_attr device_attr; /* Device properties. */\n-\tstruct ibv_pd *pd; /* Protection Domain. */\n-\t/*\n-\t * MAC addresses array and configuration bit-field.\n-\t * An extra entry that cannot be modified by the DPDK is reserved\n-\t * for broadcast frames (destination MAC address ff:ff:ff:ff:ff:ff).\n-\t */\n-\tstruct ether_addr mac[MLX4_MAX_MAC_ADDRESSES];\n-\tBITFIELD_DECLARE(mac_configured, uint32_t, MLX4_MAX_MAC_ADDRESSES);\n-\t/* VLAN filters. */\n-\tstruct {\n-\t\tunsigned int enabled:1; /* If enabled. */\n-\t\tunsigned int id:12; /* VLAN ID (0-4095). */\n-\t} vlan_filter[MLX4_MAX_VLAN_IDS]; /* VLAN filters table. */\n-\t/* Device properties. */\n-\tuint16_t mtu; /* Configured MTU. */\n-\tuint8_t port; /* Physical port number. */\n-\tunsigned int started:1; /* Device started, flows enabled. */\n-\tunsigned int promisc:1; /* Device in promiscuous mode. */\n-\tunsigned int allmulti:1; /* Device receives all multicast packets. */\n-\tunsigned int hw_qpg:1; /* QP groups are supported. */\n-\tunsigned int hw_tss:1; /* TSS is supported. */\n-\tunsigned int hw_rss:1; /* RSS is supported. */\n-\tunsigned int hw_csum:1; /* Checksum offload is supported. */\n-\tunsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */\n-\tunsigned int rss:1; /* RSS is enabled. */\n-\tunsigned int vf:1; /* This is a VF device. */\n-\tunsigned int pending_alarm:1; /* An alarm is pending. */\n-#ifdef INLINE_RECV\n-\tunsigned int inl_recv_size; /* Inline recv size */\n-#endif\n-\tunsigned int max_rss_tbl_sz; /* Maximum number of RSS queues. */\n-\t/* RX/TX queues. */\n-\tstruct rxq rxq_parent; /* Parent queue when RSS is enabled. */\n-\tunsigned int rxqs_n; /* RX queues array size. */\n-\tunsigned int txqs_n; /* TX queues array size. */\n-\tstruct rxq *(*rxqs)[]; /* RX queues. */\n-\tstruct txq *(*txqs)[]; /* TX queues. */\n-\tstruct rte_intr_handle intr_handle; /* Interrupt handler. */\n-\trte_spinlock_t lock; /* Lock for control functions. */\n-};\n-\n /* Local storage for secondary process data. */\n struct mlx4_secondary_data {\n \tstruct rte_eth_dev_data data; /* Local device data. */\n@@ -335,8 +162,7 @@ struct mlx4_secondary_data {\n * @param priv\n * Pointer to private structure.\n */\n-static void\n-priv_lock(struct priv *priv)\n+void priv_lock(struct priv *priv)\n {\n \trte_spinlock_lock(&priv->lock);\n }\n@@ -347,8 +173,7 @@ struct mlx4_secondary_data {\n * @param priv\n * Pointer to private structure.\n */\n-static void\n-priv_unlock(struct priv *priv)\n+void priv_unlock(struct priv *priv)\n {\n \trte_spinlock_unlock(&priv->lock);\n }\ndiff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h\nindex 4c7505e..70c9ecd 100644\n--- a/drivers/net/mlx4/mlx4.h\n+++ b/drivers/net/mlx4/mlx4.h\n@@ -1,8 +1,8 @@\n /*-\n * BSD LICENSE\n *\n- * Copyright 2012-2015 6WIND S.A.\n- * Copyright 2012 Mellanox.\n+ * Copyright 2012-2017 6WIND S.A.\n+ * Copyright 2012-2017 Mellanox.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n@@ -39,6 +39,33 @@\n #include <limits.h>\n \n /*\n+ * Runtime logging through RTE_LOG() is enabled when not in debugging mode.\n+ * Intermediate LOG_*() macros add the required end-of-line characters.\n+ */\n+#ifndef NDEBUG\n+#define INFO(...) DEBUG(__VA_ARGS__)\n+#define WARN(...) DEBUG(__VA_ARGS__)\n+#define ERROR(...) DEBUG(__VA_ARGS__)\n+#else\n+#define LOG__(level, m, ...) \\\n+\tRTE_LOG(level, PMD, MLX4_DRIVER_NAME \": \" m \"%c\", __VA_ARGS__)\n+#define LOG_(level, ...) LOG__(level, __VA_ARGS__, '\\n')\n+#define INFO(...) LOG_(INFO, __VA_ARGS__)\n+#define WARN(...) LOG_(WARNING, __VA_ARGS__)\n+#define ERROR(...) LOG_(ERR, __VA_ARGS__)\n+#endif\n+\n+/* Verbs header. */\n+/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+#include <infiniband/verbs.h>\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-Wpedantic\"\n+#endif\n+\n+/*\n * Maximum number of simultaneous MAC addresses supported.\n *\n * According to ConnectX's Programmer Reference Manual:\n@@ -160,4 +187,160 @@ enum {\n #define claim_positive(...) (__VA_ARGS__)\n #endif /* NDEBUG */\n \n+struct mlx4_rxq_stats {\n+\tunsigned int idx; /**< Mapping index. */\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\tuint64_t ipackets; /**< Total of successfully received packets. */\n+\tuint64_t ibytes; /**< Total of successfully received bytes. */\n+#endif\n+\tuint64_t idropped; /**< Total of packets dropped when RX ring full. */\n+\tuint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */\n+};\n+\n+/* RX element (scattered packets). */\n+struct rxq_elt_sp {\n+\tstruct ibv_recv_wr wr; /* Work Request. */\n+\tstruct ibv_sge sges[MLX4_PMD_SGE_WR_N]; /* Scatter/Gather Elements. */\n+\tstruct rte_mbuf *bufs[MLX4_PMD_SGE_WR_N]; /* SGEs buffers. */\n+};\n+\n+/* RX element. */\n+struct rxq_elt {\n+\tstruct ibv_recv_wr wr; /* Work Request. */\n+\tstruct ibv_sge sge; /* Scatter/Gather Element. */\n+\t/* mbuf pointer is derived from WR_ID(wr.wr_id).offset. */\n+};\n+\n+/* RX queue descriptor. */\n+struct rxq {\n+\tstruct priv *priv; /* Back pointer to private data. */\n+\tstruct rte_mempool *mp; /* Memory Pool for allocations. */\n+\tstruct ibv_mr *mr; /* Memory Region (for mp). */\n+\tstruct ibv_cq *cq; /* Completion Queue. */\n+\tstruct ibv_qp *qp; /* Queue Pair. */\n+\tstruct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */\n+\tstruct ibv_exp_cq_family *if_cq; /* CQ interface. */\n+\t/*\n+\t * Each VLAN ID requires a separate flow steering rule.\n+\t */\n+\tBITFIELD_DECLARE(mac_configured, uint32_t, MLX4_MAX_MAC_ADDRESSES);\n+\tstruct ibv_flow *mac_flow[MLX4_MAX_MAC_ADDRESSES][MLX4_MAX_VLAN_IDS];\n+\tstruct ibv_flow *promisc_flow; /* Promiscuous flow. */\n+\tstruct ibv_flow *allmulti_flow; /* Multicast flow. */\n+\tunsigned int port_id; /* Port ID for incoming packets. */\n+\tunsigned int elts_n; /* (*elts)[] length. */\n+\tunsigned int elts_head; /* Current index in (*elts)[]. */\n+\tunion {\n+\t\tstruct rxq_elt_sp (*sp)[]; /* Scattered RX elements. */\n+\t\tstruct rxq_elt (*no_sp)[]; /* RX elements. */\n+\t} elts;\n+\tunsigned int sp:1; /* Use scattered RX elements. */\n+\tunsigned int csum:1; /* Enable checksum offloading. */\n+\tunsigned int csum_l2tun:1; /* Same for L2 tunnels. */\n+\tstruct mlx4_rxq_stats stats; /* RX queue counters. */\n+\tunsigned int socket; /* CPU socket ID for allocations. */\n+\tstruct ibv_exp_res_domain *rd; /* Resource Domain. */\n+};\n+\n+/* TX element. */\n+struct txq_elt {\n+\tstruct rte_mbuf *buf;\n+};\n+\n+struct mlx4_txq_stats {\n+\tunsigned int idx; /**< Mapping index. */\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\tuint64_t opackets; /**< Total of successfully sent packets. */\n+\tuint64_t obytes; /**< Total of successfully sent bytes. */\n+#endif\n+\tuint64_t odropped; /**< Total of packets not sent when TX ring full. */\n+};\n+\n+/*\n+ * Linear buffer type. It is used when transmitting buffers with too many\n+ * segments that do not fit the hardware queue (see max_send_sge).\n+ * Extra segments are copied (linearized) in such buffers, replacing the\n+ * last SGE during TX.\n+ * The size is arbitrary but large enough to hold a jumbo frame with\n+ * 8 segments considering mbuf.buf_len is about 2048 bytes.\n+ */\n+typedef uint8_t linear_t[16384];\n+\n+/* TX queue descriptor. */\n+struct txq {\n+\tstruct priv *priv; /* Back pointer to private data. */\n+\tstruct {\n+\t\tconst struct rte_mempool *mp; /* Cached Memory Pool. */\n+\t\tstruct ibv_mr *mr; /* Memory Region (for mp). */\n+\t\tuint32_t lkey; /* mr->lkey */\n+\t} mp2mr[MLX4_PMD_TX_MP_CACHE]; /* MP to MR translation table. */\n+\tstruct ibv_cq *cq; /* Completion Queue. */\n+\tstruct ibv_qp *qp; /* Queue Pair. */\n+\tstruct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */\n+\tstruct ibv_exp_cq_family *if_cq; /* CQ interface. */\n+#if MLX4_PMD_MAX_INLINE > 0\n+\tuint32_t max_inline; /* Max inline send size <= MLX4_PMD_MAX_INLINE. */\n+#endif\n+\tunsigned int elts_n; /* (*elts)[] length. */\n+\tstruct txq_elt (*elts)[]; /* TX elements. */\n+\tunsigned int elts_head; /* Current index in (*elts)[]. */\n+\tunsigned int elts_tail; /* First element awaiting completion. */\n+\tunsigned int elts_comp; /* Number of completion requests. */\n+\tunsigned int elts_comp_cd; /* Countdown for next completion request. */\n+\tunsigned int elts_comp_cd_init; /* Initial value for countdown. */\n+\tstruct mlx4_txq_stats stats; /* TX queue counters. */\n+\tlinear_t (*elts_linear)[]; /* Linearized buffers. */\n+\tstruct ibv_mr *mr_linear; /* Memory Region for linearized buffers. */\n+\tunsigned int socket; /* CPU socket ID for allocations. */\n+\tstruct ibv_exp_res_domain *rd; /* Resource Domain. */\n+};\n+\n+struct priv {\n+\tstruct rte_eth_dev *dev; /* Ethernet device. */\n+\tstruct ibv_context *ctx; /* Verbs context. */\n+\tstruct ibv_device_attr device_attr; /* Device properties. */\n+\tstruct ibv_pd *pd; /* Protection Domain. */\n+\t/*\n+\t * MAC addresses array and configuration bit-field.\n+\t * An extra entry that cannot be modified by the DPDK is reserved\n+\t * for broadcast frames (destination MAC address ff:ff:ff:ff:ff:ff).\n+\t */\n+\tstruct ether_addr mac[MLX4_MAX_MAC_ADDRESSES];\n+\tBITFIELD_DECLARE(mac_configured, uint32_t, MLX4_MAX_MAC_ADDRESSES);\n+\t/* VLAN filters. */\n+\tstruct {\n+\t\tunsigned int enabled:1; /* If enabled. */\n+\t\tunsigned int id:12; /* VLAN ID (0-4095). */\n+\t} vlan_filter[MLX4_MAX_VLAN_IDS]; /* VLAN filters table. */\n+\t/* Device properties. */\n+\tuint16_t mtu; /* Configured MTU. */\n+\tuint8_t port; /* Physical port number. */\n+\tunsigned int started:1; /* Device started, flows enabled. */\n+\tunsigned int promisc:1; /* Device in promiscuous mode. */\n+\tunsigned int allmulti:1; /* Device receives all multicast packets. */\n+\tunsigned int hw_qpg:1; /* QP groups are supported. */\n+\tunsigned int hw_tss:1; /* TSS is supported. */\n+\tunsigned int hw_rss:1; /* RSS is supported. */\n+\tunsigned int hw_csum:1; /* Checksum offload is supported. */\n+\tunsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */\n+\tunsigned int rss:1; /* RSS is enabled. */\n+\tunsigned int vf:1; /* This is a VF device. */\n+\tunsigned int pending_alarm:1; /* An alarm is pending. */\n+#ifdef INLINE_RECV\n+\tunsigned int inl_recv_size; /* Inline recv size */\n+#endif\n+\tunsigned int max_rss_tbl_sz; /* Maximum number of RSS queues. */\n+\t/* RX/TX queues. */\n+\tstruct rxq rxq_parent; /* Parent queue when RSS is enabled. */\n+\tunsigned int rxqs_n; /* RX queues array size. */\n+\tunsigned int txqs_n; /* TX queues array size. */\n+\tstruct rxq *(*rxqs)[]; /* RX queues. */\n+\tstruct txq *(*txqs)[]; /* TX queues. */\n+\tstruct rte_intr_handle intr_handle; /* Interrupt handler. */\n+\trte_spinlock_t lock; /* Lock for control functions. */\n+};\n+\n+void priv_lock(struct priv *priv);\n+void priv_unlock(struct priv *priv);\n+\n #endif /* RTE_PMD_MLX4_H_ */\n", "prefixes": [ "dpdk-dev", "v2", "1/2" ] }