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{
    "id": 20381,
    "url": "http://patches.dpdk.org/api/patches/20381/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1486845372-31043-1-git-send-email-thomas.monjalon@6wind.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1486845372-31043-1-git-send-email-thomas.monjalon@6wind.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1486845372-31043-1-git-send-email-thomas.monjalon@6wind.com",
    "date": "2017-02-11T20:36:12",
    "name": "[dpdk-dev] remove unmaintained TILE-Gx architecture",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "25a551e671505a0f9fb1a8499852099ea982e691",
    "submitter": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/people/1/?format=api",
        "name": "Thomas Monjalon",
        "email": "thomas.monjalon@6wind.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1486845372-31043-1-git-send-email-thomas.monjalon@6wind.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/20381/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/20381/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 6926E2BAE;\n\tSat, 11 Feb 2017 21:36:28 +0100 (CET)",
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        ],
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        "X-Gm-Message-State": "AMke39lIK1GNHm8k7jFeQQGAxnfebiHWd40p13eJpFQB4B0FyjrN72Q0JBrCKgvaI4AD7thj",
        "X-Received": "by 10.223.163.30 with SMTP id c30mr12996755wrb.40.1486845383313; \n\tSat, 11 Feb 2017 12:36:23 -0800 (PST)",
        "From": "Thomas Monjalon <thomas.monjalon@6wind.com>",
        "To": "Zhigang Lu <zlu@ezchip.com>,\n\tLiming Sun <lsun@ezchip.com>",
        "Cc": "dev@dpdk.org",
        "Date": "Sat, 11 Feb 2017 21:36:12 +0100",
        "Message-Id": "<1486845372-31043-1-git-send-email-thomas.monjalon@6wind.com>",
        "X-Mailer": "git-send-email 2.7.0",
        "Subject": "[dpdk-dev] [PATCH] remove unmaintained TILE-Gx architecture",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The TILE-Gx architecture and its driver mpipe are not maintained.\nThe code is removed to avoid confusion.\n\nSigned-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>\n---\n MAINTAINERS                                        |    7 -\n config/defconfig_arm-armv7a-linuxapp-gcc           |    1 -\n config/defconfig_tile-tilegx-linuxapp-gcc          |   74 -\n devtools/check-git-log.sh                          |    2 -\n doc/guides/nics/features/default.ini               |    1 -\n doc/guides/nics/features/mpipe.ini                 |    6 -\n doc/guides/nics/features/pcap.ini                  |    1 -\n drivers/net/Makefile                               |    1 -\n drivers/net/mpipe/Makefile                         |   47 -\n drivers/net/mpipe/mpipe_tilegx.c                   | 1665 --------------------\n drivers/net/mpipe/rte_pmd_mpipe_version.map        |    3 -\n lib/librte_eal/common/arch/tile/rte_cpuflags.c     |   47 -\n .../common/include/arch/tile/rte_atomic.h          |   98 --\n .../common/include/arch/tile/rte_byteorder.h       |   91 --\n .../common/include/arch/tile/rte_cpuflags.h        |   53 -\n .../common/include/arch/tile/rte_cycles.h          |   70 -\n lib/librte_eal/common/include/arch/tile/rte_io.h   |   47 -\n .../common/include/arch/tile/rte_memcpy.h          |   87 -\n .../common/include/arch/tile/rte_prefetch.h        |   67 -\n .../common/include/arch/tile/rte_rwlock.h          |   70 -\n .../common/include/arch/tile/rte_spinlock.h        |   92 --\n lib/librte_eal/common/include/arch/tile/rte_vect.h |   38 -\n mk/arch/tile/rte.vars.mk                           |   39 -\n mk/rte.app.mk                                      |    1 -\n 24 files changed, 2608 deletions(-)\n delete mode 100644 config/defconfig_tile-tilegx-linuxapp-gcc\n delete mode 100644 doc/guides/nics/features/mpipe.ini\n delete mode 100644 drivers/net/mpipe/Makefile\n delete mode 100644 drivers/net/mpipe/mpipe_tilegx.c\n delete mode 100644 drivers/net/mpipe/rte_pmd_mpipe_version.map\n delete mode 100644 lib/librte_eal/common/arch/tile/rte_cpuflags.c\n delete mode 100644 lib/librte_eal/common/include/arch/tile/rte_atomic.h\n delete mode 100644 lib/librte_eal/common/include/arch/tile/rte_byteorder.h\n delete mode 100644 lib/librte_eal/common/include/arch/tile/rte_cpuflags.h\n delete mode 100644 lib/librte_eal/common/include/arch/tile/rte_cycles.h\n delete mode 100644 lib/librte_eal/common/include/arch/tile/rte_io.h\n delete mode 100644 lib/librte_eal/common/include/arch/tile/rte_memcpy.h\n delete mode 100644 lib/librte_eal/common/include/arch/tile/rte_prefetch.h\n delete mode 100644 lib/librte_eal/common/include/arch/tile/rte_rwlock.h\n delete mode 100644 lib/librte_eal/common/include/arch/tile/rte_spinlock.h\n delete mode 100644 lib/librte_eal/common/include/arch/tile/rte_vect.h\n delete mode 100644 mk/arch/tile/rte.vars.mk",
    "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex cc3bf98..12090c1 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -155,13 +155,6 @@ F: drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c\n F: drivers/net/i40e/i40e_rxtx_vec_neon.c\n F: drivers/net/virtio/virtio_rxtx_simple_neon.c\n \n-EZchip TILE-Gx\n-M: Zhigang Lu <zlu@ezchip.com>\n-M: Liming Sun <lsun@ezchip.com>\n-F: lib/librte_eal/common/arch/tile/\n-F: lib/librte_eal/common/include/arch/tile/\n-F: drivers/net/mpipe/\n-\n IBM POWER\n M: Chao Zhu <chaozhu@linux.vnet.ibm.com>\n F: lib/librte_eal/common/arch/ppc_64/\ndiff --git a/config/defconfig_arm-armv7a-linuxapp-gcc b/config/defconfig_arm-armv7a-linuxapp-gcc\nindex d99bd0f..d9bd2a8 100644\n--- a/config/defconfig_arm-armv7a-linuxapp-gcc\n+++ b/config/defconfig_arm-armv7a-linuxapp-gcc\n@@ -70,7 +70,6 @@ CONFIG_RTE_LIBRTE_FM10K_PMD=n\n CONFIG_RTE_LIBRTE_I40E_PMD=n\n CONFIG_RTE_LIBRTE_IXGBE_PMD=n\n CONFIG_RTE_LIBRTE_MLX4_PMD=n\n-CONFIG_RTE_LIBRTE_MPIPE_PMD=n\n CONFIG_RTE_LIBRTE_VMXNET3_PMD=n\n CONFIG_RTE_LIBRTE_PMD_XENVIRT=n\n CONFIG_RTE_LIBRTE_PMD_BNX2X=n\ndiff --git a/config/defconfig_tile-tilegx-linuxapp-gcc b/config/defconfig_tile-tilegx-linuxapp-gcc\ndeleted file mode 100644\nindex 44add62..0000000\n--- a/config/defconfig_tile-tilegx-linuxapp-gcc\n+++ /dev/null\n@@ -1,74 +0,0 @@\n-#   BSD LICENSE\n-#\n-#   Copyright (C) EZchip Semiconductor 2015.\n-#\n-#   Redistribution and use in source and binary forms, with or without\n-#   modification, are permitted provided that the following conditions\n-#   are met:\n-#\n-#     * Redistributions of source code must retain the above copyright\n-#       notice, this list of conditions and the following disclaimer.\n-#     * Redistributions in binary form must reproduce the above copyright\n-#       notice, this list of conditions and the following disclaimer in\n-#       the documentation and/or other materials provided with the\n-#       distribution.\n-#     * Neither the name of EZchip Semiconductor nor the names of its\n-#       contributors may be used to endorse or promote products derived\n-#       from this software without specific prior written permission.\n-#\n-#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n-#   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n-#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n-#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n-#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n-#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n-#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n-#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n-#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n-#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n-#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-\n-#include \"common_linuxapp\"\n-\n-CONFIG_RTE_MACHINE=\"tilegx\"\n-\n-CONFIG_RTE_ARCH=\"tile\"\n-CONFIG_RTE_ARCH_TILE=y\n-CONFIG_RTE_ARCH_64=y\n-CONFIG_RTE_ARCH_STRICT_ALIGN=y\n-CONFIG_RTE_FORCE_INTRINSICS=y\n-\n-CONFIG_RTE_TOOLCHAIN=\"gcc\"\n-CONFIG_RTE_TOOLCHAIN_GCC=y\n-\n-CONFIG_RTE_MEMPOOL_ALIGN=128\n-\n-CONFIG_RTE_LIBRTE_MPIPE_PMD=y\n-CONFIG_RTE_LIBRTE_MPIPE_PMD_DEBUG=n\n-\n-# Disable things that we don't support or need\n-CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n\n-CONFIG_RTE_EAL_IGB_UIO=n\n-CONFIG_RTE_EAL_VFIO=n\n-CONFIG_RTE_LIBRTE_KNI=n\n-CONFIG_RTE_KNI_KMOD=n\n-CONFIG_RTE_LIBRTE_XEN_DOM0=n\n-CONFIG_RTE_LIBRTE_IGB_PMD=n\n-CONFIG_RTE_LIBRTE_EM_PMD=n\n-CONFIG_RTE_LIBRTE_IXGBE_PMD=n\n-CONFIG_RTE_LIBRTE_I40E_PMD=n\n-CONFIG_RTE_LIBRTE_FM10K_PMD=n\n-CONFIG_RTE_LIBRTE_VIRTIO_PMD=n\n-CONFIG_RTE_LIBRTE_VMXNET3_PMD=n\n-CONFIG_RTE_LIBRTE_ENIC_PMD=n\n-\n-# This following libraries are not available on the tile architecture.\n-# So they're turned off.\n-CONFIG_RTE_LIBRTE_LPM=n\n-CONFIG_RTE_LIBRTE_ACL=n\n-CONFIG_RTE_LIBRTE_SCHED=n\n-CONFIG_RTE_LIBRTE_PORT=n\n-CONFIG_RTE_LIBRTE_TABLE=n\n-CONFIG_RTE_LIBRTE_PIPELINE=n\n-CONFIG_RTE_LIBRTE_CXGBE_PMD=n\n-CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n\ndiff --git a/devtools/check-git-log.sh b/devtools/check-git-log.sh\nindex 4c50eff..e3ac0e4 100755\n--- a/devtools/check-git-log.sh\n+++ b/devtools/check-git-log.sh\n@@ -133,8 +133,6 @@ bad=$(echo \"$headlines\" | grep -E --color=always \\\n \t-e ':.*\\<pci\\>' \\\n \t-e ':.*\\<pmd\\>' \\\n \t-e ':.*\\<rss\\>' \\\n-\t-e ':.*\\<tile-gx\\>' \\\n-\t-e ':.*\\<tilegx\\>' \\\n \t-e ':.*\\<tso\\>' \\\n \t-e ':.*\\<[Vv]lan\\>' \\\n \t| sed 's,^,\\t,')\ndiff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini\nindex 9e363ff..299078f 100644\n--- a/doc/guides/nics/features/default.ini\n+++ b/doc/guides/nics/features/default.ini\n@@ -63,7 +63,6 @@ Other kdrv           =\n ARMv7                =\n ARMv8                =\n Power8               =\n-TILE-Gx              =\n x86-32               =\n x86-64               =\n Usage doc            =\ndiff --git a/doc/guides/nics/features/mpipe.ini b/doc/guides/nics/features/mpipe.ini\ndeleted file mode 100644\nindex ca60933..0000000\n--- a/doc/guides/nics/features/mpipe.ini\n+++ /dev/null\n@@ -1,6 +0,0 @@\n-;\n-; Supported features of the 'mpipe' network poll mode driver.\n-;\n-; Refer to default.ini for the full list of available PMD features.\n-;\n-[Features]\ndiff --git a/doc/guides/nics/features/pcap.ini b/doc/guides/nics/features/pcap.ini\nindex 8245cbf..28e6488 100644\n--- a/doc/guides/nics/features/pcap.ini\n+++ b/doc/guides/nics/features/pcap.ini\n@@ -10,7 +10,6 @@ Multiprocess aware   = Y\n ARMv7                = Y\n ARMv8                = Y\n Power8               = Y\n-TILE-Gx              = Y\n x86-32               = Y\n x86-64               = Y\n Usage doc            = Y\ndiff --git a/drivers/net/Makefile b/drivers/net/Makefile\nindex 40fc333..a16f25e 100644\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -43,7 +43,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e\n DIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe\n DIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += mlx4\n DIRS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5\n-DIRS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += mpipe\n DIRS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp\n DIRS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += null\ndiff --git a/drivers/net/mpipe/Makefile b/drivers/net/mpipe/Makefile\ndeleted file mode 100644\nindex 846e2e0..0000000\n--- a/drivers/net/mpipe/Makefile\n+++ /dev/null\n@@ -1,47 +0,0 @@\n-#\n-# Copyright 2015 EZchip Semiconductor Ltd.  All rights reserved.\n-#\n-# Redistribution and use in source and binary forms, with or without\n-# modification, are permitted provided that the following conditions\n-# are met:\n-#\n-# 1. Redistributions of source code must retain the above copyright\n-# notice, this list of conditions and the following disclaimer.\n-#\n-# 2. Redistributions in binary form must reproduce the above copyright\n-# notice, this list of conditions and the following disclaimer in\n-# the documentation and/or other materials provided with the\n-# distribution.\n-#\n-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n-# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n-# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n-# POSSIBILITY OF SUCH DAMAGE.\n-\n-include $(RTE_SDK)/mk/rte.vars.mk\n-\n-# library name\n-LIB = librte_pmd_mpipe.a\n-\n-CFLAGS += $(WERROR_FLAGS) -O3\n-LDLIBS += -lgxio\n-\n-EXPORT_MAP := rte_pmd_mpipe_version.map\n-\n-LIBABIVER := 1\n-\n-SRCS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += mpipe_tilegx.c\n-\n-DEPDIRS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += lib/librte_eal lib/librte_ether\n-DEPDIRS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += lib/librte_mempool lib/librte_mbuf\n-DEPDIRS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += lib/librte_net\n-\n-include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/net/mpipe/mpipe_tilegx.c b/drivers/net/mpipe/mpipe_tilegx.c\ndeleted file mode 100644\nindex 7bbd168..0000000\n--- a/drivers/net/mpipe/mpipe_tilegx.c\n+++ /dev/null\n@@ -1,1665 +0,0 @@\n-/*-\n- *   BSD LICENSE\n- *\n- *   Copyright(c) 2015 EZchip Semiconductor Ltd. All rights reserved.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of EZchip Semiconductor nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n- */\n-\n-#include <unistd.h>\n-\n-#include <rte_eal.h>\n-#include <rte_vdev.h>\n-#include <rte_eal_memconfig.h>\n-#include <rte_ethdev.h>\n-#include <rte_malloc.h>\n-#include <rte_cycles.h>\n-\n-#include <arch/mpipe_xaui_def.h>\n-#include <arch/mpipe_gbe_def.h>\n-\n-#include <gxio/mpipe.h>\n-\n-#ifdef RTE_LIBRTE_MPIPE_PMD_DEBUG\n-#define PMD_DEBUG_RX(...)\tRTE_LOG(DEBUG, PMD, __VA_ARGS__)\n-#define PMD_DEBUG_TX(...)\tRTE_LOG(DEBUG, PMD, __VA_ARGS__)\n-#else\n-#define PMD_DEBUG_RX(...)\n-#define PMD_DEBUG_TX(...)\n-#endif\n-\n-#define MPIPE_MAX_CHANNELS\t\t128\n-#define MPIPE_TX_MAX_QUEUES\t\t128\n-#define MPIPE_RX_MAX_QUEUES\t\t16\n-#define MPIPE_TX_DESCS\t\t\t512\n-#define MPIPE_RX_BUCKETS\t\t256\n-#define MPIPE_RX_STACK_SIZE\t\t65536\n-#define MPIPE_RX_IP_ALIGN\t\t2\n-#define MPIPE_BSM_ALIGN\t\t\t128\n-\n-#define MPIPE_LINK_UPDATE_TIMEOUT\t10\t/*  s */\n-#define MPIPE_LINK_UPDATE_INTERVAL\t100000\t/* us */\n-\n-struct mpipe_channel_config {\n-\tint enable;\n-\tint first_bucket;\n-\tint num_buckets;\n-\tint head_room;\n-\tgxio_mpipe_rules_stacks_t stacks;\n-};\n-\n-struct mpipe_context {\n-\trte_spinlock_t        lock;\n-\tgxio_mpipe_context_t  context;\n-\tstruct mpipe_channel_config channels[MPIPE_MAX_CHANNELS];\n-};\n-\n-/* Per-core local data. */\n-struct mpipe_local {\n-\tint mbuf_push_debt[RTE_MAX_ETHPORTS];\t/* Buffer push debt. */\n-} __rte_cache_aligned;\n-\n-#define MPIPE_BUF_DEBT_THRESHOLD\t32\n-static __thread struct mpipe_local mpipe_local;\n-static struct mpipe_context mpipe_contexts[GXIO_MPIPE_INSTANCE_MAX];\n-static int mpipe_instances;\n-\n-/* Per queue statistics. */\n-struct mpipe_queue_stats {\n-\tuint64_t packets, bytes, errors, nomem;\n-};\n-\n-/* Common tx/rx queue fields. */\n-struct mpipe_queue {\n-\tstruct mpipe_dev_priv *priv;\t/* \"priv\" data of its device. */\n-\tuint16_t nb_desc;\t\t/* Number of tx descriptors. */\n-\tuint16_t port_id;\t\t/* Device index. */\n-\tuint16_t stat_idx;\t\t/* Queue stats index. */\n-\tuint8_t queue_idx;\t\t/* Queue index. */\n-\tuint8_t link_status;\t\t/* 0 = link down. */\n-\tstruct mpipe_queue_stats stats;\t/* Stat data for the queue. */\n-};\n-\n-/* Transmit queue description. */\n-struct mpipe_tx_queue {\n-\tstruct mpipe_queue q;\t\t/* Common stuff. */\n-};\n-\n-/* Receive queue description. */\n-struct mpipe_rx_queue {\n-\tstruct mpipe_queue q;\t\t/* Common stuff. */\n-\tgxio_mpipe_iqueue_t iqueue;\t/* mPIPE iqueue. */\n-\tgxio_mpipe_idesc_t *next_desc;\t/* Next idesc to process. */\n-\tint avail_descs;\t\t/* Number of available descs. */\n-\tvoid *rx_ring_mem;\t\t/* DMA ring memory. */\n-};\n-\n-struct mpipe_dev_priv {\n-\tgxio_mpipe_context_t *context;\t/* mPIPE context. */\n-\tgxio_mpipe_link_t link;\t\t/* mPIPE link for the device. */\n-\tgxio_mpipe_equeue_t equeue;\t/* mPIPE equeue. */\n-\tunsigned equeue_size;\t\t/* mPIPE equeue desc count. */\n-\tint instance;\t\t\t/* mPIPE instance. */\n-\tint ering;\t\t\t/* mPIPE eDMA ring. */\n-\tint stack;\t\t\t/* mPIPE buffer stack. */\n-\tint channel;\t\t\t/* Device channel. */\n-\tint port_id;\t\t\t/* DPDK port index. */\n-\tstruct rte_eth_dev *eth_dev;\t/* DPDK device. */\n-\tstruct rte_mbuf **tx_comps;\t/* TX completion array. */\n-\tstruct rte_mempool *rx_mpool;\t/* mpool used by the rx queues. */\n-\tunsigned rx_offset;\t\t/* Receive head room. */\n-\tunsigned rx_size_code;\t\t/* mPIPE rx buffer size code. */\n-\tint is_xaui:1,\t\t\t/* Is this an xgbe or gbe? */\n-\t    initialized:1,\t\t/* Initialized port? */\n-\t    running:1;\t\t\t/* Running port? */\n-\tstruct ether_addr mac_addr;\t/* MAC address. */\n-\tunsigned nb_rx_queues;\t\t/* Configured tx queues. */\n-\tunsigned nb_tx_queues;\t\t/* Configured rx queues. */\n-\tint first_bucket;\t\t/* mPIPE bucket start index. */\n-\tint first_ring;\t\t\t/* mPIPE notif ring start index. */\n-\tint notif_group;\t\t/* mPIPE notif group. */\n-\trte_atomic32_t dp_count __rte_cache_aligned;\t/* DP Entry count. */\n-\tint tx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n-\tint rx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n-};\n-\n-#define mpipe_priv(dev)\t\t\t\\\n-\t((struct mpipe_dev_priv*)(dev)->data->dev_private)\n-\n-#define mpipe_name(priv)\t\t\\\n-\t((priv)->eth_dev->data->name)\n-\n-#define mpipe_rx_queue(priv, n)\t\t\\\n-\t((struct mpipe_rx_queue *)(priv)->eth_dev->data->rx_queues[n])\n-\n-#define mpipe_tx_queue(priv, n)\t\t\\\n-\t((struct mpipe_tx_queue *)(priv)->eth_dev->data->tx_queues[n])\n-\n-static void\n-mpipe_xmit_flush(struct mpipe_dev_priv *priv);\n-\n-static void\n-mpipe_recv_flush(struct mpipe_dev_priv *priv);\n-\n-static int mpipe_equeue_sizes[] = {\n-\t[GXIO_MPIPE_EQUEUE_ENTRY_512]\t= 512,\n-\t[GXIO_MPIPE_EQUEUE_ENTRY_2K]\t= 2048,\n-\t[GXIO_MPIPE_EQUEUE_ENTRY_8K]\t= 8192,\n-\t[GXIO_MPIPE_EQUEUE_ENTRY_64K]\t= 65536,\n-};\n-\n-static int mpipe_iqueue_sizes[] = {\n-\t[GXIO_MPIPE_IQUEUE_ENTRY_128]\t= 128,\n-\t[GXIO_MPIPE_IQUEUE_ENTRY_512]\t= 512,\n-\t[GXIO_MPIPE_IQUEUE_ENTRY_2K]\t= 2048,\n-\t[GXIO_MPIPE_IQUEUE_ENTRY_64K]\t= 65536,\n-};\n-\n-static int mpipe_buffer_sizes[] = {\n-\t[GXIO_MPIPE_BUFFER_SIZE_128]\t= 128,\n-\t[GXIO_MPIPE_BUFFER_SIZE_256]\t= 256,\n-\t[GXIO_MPIPE_BUFFER_SIZE_512]\t= 512,\n-\t[GXIO_MPIPE_BUFFER_SIZE_1024]\t= 1024,\n-\t[GXIO_MPIPE_BUFFER_SIZE_1664]\t= 1664,\n-\t[GXIO_MPIPE_BUFFER_SIZE_4096]\t= 4096,\n-\t[GXIO_MPIPE_BUFFER_SIZE_10368]\t= 10368,\n-\t[GXIO_MPIPE_BUFFER_SIZE_16384]\t= 16384,\n-};\n-\n-static gxio_mpipe_context_t *\n-mpipe_context(int instance)\n-{\n-\tif (instance < 0 || instance >= mpipe_instances)\n-\t\treturn NULL;\n-\treturn &mpipe_contexts[instance].context;\n-}\n-\n-static int mpipe_channel_config(int instance, int channel,\n-\t\t\t\tstruct mpipe_channel_config *config)\n-{\n-\tstruct mpipe_channel_config *data;\n-\tstruct mpipe_context *context;\n-\tgxio_mpipe_rules_t rules;\n-\tint idx, rc = 0;\n-\n-\tif (instance < 0 || instance >= mpipe_instances ||\n-\t    channel < 0 || channel >= MPIPE_MAX_CHANNELS)\n-\t\treturn -EINVAL;\n-\n-\tcontext = &mpipe_contexts[instance];\n-\n-\trte_spinlock_lock(&context->lock);\n-\n-\tgxio_mpipe_rules_init(&rules, &context->context);\n-\n-\tfor (idx = 0; idx < MPIPE_MAX_CHANNELS; idx++) {\n-\t\tdata = (channel == idx) ? config : &context->channels[idx];\n-\n-\t\tif (!data->enable)\n-\t\t\tcontinue;\n-\n-\t\trc = gxio_mpipe_rules_begin(&rules, data->first_bucket,\n-\t\t\t\t\t    data->num_buckets, &data->stacks);\n-\t\tif (rc < 0) {\n-\t\t\tgoto done;\n-\t\t}\n-\n-\t\trc = gxio_mpipe_rules_add_channel(&rules, idx);\n-\t\tif (rc < 0) {\n-\t\t\tgoto done;\n-\t\t}\n-\n-\t\trc = gxio_mpipe_rules_set_headroom(&rules, data->head_room);\n-\t\tif (rc < 0) {\n-\t\t\tgoto done;\n-\t\t}\n-\t}\n-\n-\trc = gxio_mpipe_rules_commit(&rules);\n-\tif (rc == 0) {\n-\t\tmemcpy(&context->channels[channel], config, sizeof(*config));\n-\t}\n-\n-done:\n-\trte_spinlock_unlock(&context->lock);\n-\n-\treturn rc;\n-}\n-\n-static int\n-mpipe_get_size_index(int *array, int count, int size,\n-\t\t     bool roundup)\n-{\n-\tint i, last = -1;\n-\n-\tfor (i = 0; i < count && array[i] < size; i++) {\n-\t\tif (array[i])\n-\t\t\tlast = i;\n-\t}\n-\n-\tif (roundup)\n-\t\treturn i < count ? (int)i : -ENOENT;\n-\telse\n-\t\treturn last >= 0 ? last : -ENOENT;\n-}\n-\n-static int\n-mpipe_calc_size(int *array, int count, int size)\n-{\n-\tint index = mpipe_get_size_index(array, count, size, 1);\n-\treturn index < 0 ? index : array[index];\n-}\n-\n-static int mpipe_equeue_size(int size)\n-{\n-\tint result;\n-\tresult = mpipe_calc_size(mpipe_equeue_sizes,\n-\t\t\t\t RTE_DIM(mpipe_equeue_sizes), size);\n-\treturn result;\n-}\n-\n-static int mpipe_iqueue_size(int size)\n-{\n-\tint result;\n-\tresult = mpipe_calc_size(mpipe_iqueue_sizes,\n-\t\t\t\t RTE_DIM(mpipe_iqueue_sizes), size);\n-\treturn result;\n-}\n-\n-static int mpipe_buffer_size_index(int size)\n-{\n-\tint result;\n-\tresult = mpipe_get_size_index(mpipe_buffer_sizes,\n-\t\t\t\t      RTE_DIM(mpipe_buffer_sizes), size, 0);\n-\treturn result;\n-}\n-\n-static inline int\n-mpipe_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n-\t\t\t\t  struct rte_eth_link *link)\n-{\n-\tstruct rte_eth_link *dst = link;\n-\tstruct rte_eth_link *src = &(dev->data->dev_link);\n-\n-\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n-\t\t\t\t*(uint64_t *)src) == 0)\n-\t\treturn -1;\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-mpipe_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n-\t\t\t\t   struct rte_eth_link *link)\n-{\n-\tstruct rte_eth_link *dst = &(dev->data->dev_link);\n-\tstruct rte_eth_link *src = link;\n-\n-\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n-\t\t\t\t*(uint64_t *)src) == 0)\n-\t\treturn -1;\n-\n-\treturn 0;\n-}\n-\n-static void\n-mpipe_infos_get(struct rte_eth_dev *dev __rte_unused,\n-\t\tstruct rte_eth_dev_info *dev_info)\n-{\n-\tdev_info->min_rx_bufsize  = 128;\n-\tdev_info->max_rx_pktlen   = 1518;\n-\tdev_info->max_tx_queues   = MPIPE_TX_MAX_QUEUES;\n-\tdev_info->max_rx_queues   = MPIPE_RX_MAX_QUEUES;\n-\tdev_info->max_mac_addrs   = 1;\n-\tdev_info->rx_offload_capa = 0;\n-\tdev_info->tx_offload_capa = 0;\n-}\n-\n-static int\n-mpipe_configure(struct rte_eth_dev *dev)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\n-\tif (dev->data->nb_tx_queues > MPIPE_TX_MAX_QUEUES) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Too many tx queues: %d > %d\\n\",\n-\t\t\tmpipe_name(priv), dev->data->nb_tx_queues,\n-\t\t\tMPIPE_TX_MAX_QUEUES);\n-\t\treturn -EINVAL;\n-\t}\n-\tpriv->nb_tx_queues = dev->data->nb_tx_queues;\n-\n-\tif (dev->data->nb_rx_queues > MPIPE_RX_MAX_QUEUES) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Too many rx queues: %d > %d\\n\",\n-\t\t\tmpipe_name(priv), dev->data->nb_rx_queues,\n-\t\t\tMPIPE_RX_MAX_QUEUES);\n-\t}\n-\tpriv->nb_rx_queues = dev->data->nb_rx_queues;\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-mpipe_link_compare(struct rte_eth_link *link1,\n-\t\t   struct rte_eth_link *link2)\n-{\n-\treturn (*(uint64_t *)link1 == *(uint64_t *)link2)\n-\t\t? -1 : 0;\n-}\n-\n-static int\n-mpipe_link_update(struct rte_eth_dev *dev, int wait_to_complete)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tstruct rte_eth_link old, new;\n-\tint64_t state, speed;\n-\tint count, rc;\n-\n-\tmemset(&old, 0, sizeof(old));\n-\tmemset(&new, 0, sizeof(new));\n-\tmpipe_dev_atomic_read_link_status(dev, &old);\n-\n-\tfor (count = 0, rc = 0; count < MPIPE_LINK_UPDATE_TIMEOUT; count++) {\n-\t\tif (!priv->initialized)\n-\t\t\tbreak;\n-\n-\t\tstate = gxio_mpipe_link_get_attr(&priv->link,\n-\t\t\t\t\t\t GXIO_MPIPE_LINK_CURRENT_STATE);\n-\t\tif (state < 0)\n-\t\t\tbreak;\n-\n-\t\tspeed = state & GXIO_MPIPE_LINK_SPEED_MASK;\n-\n-\t\tnew.link_autoneg = (dev->data->dev_conf.link_speeds &\n-\t\t\t\tETH_LINK_SPEED_AUTONEG);\n-\t\tif (speed == GXIO_MPIPE_LINK_1G) {\n-\t\t\tnew.link_speed = ETH_SPEED_NUM_1G;\n-\t\t\tnew.link_duplex = ETH_LINK_FULL_DUPLEX;\n-\t\t\tnew.link_status = ETH_LINK_UP;\n-\t\t} else if (speed == GXIO_MPIPE_LINK_10G) {\n-\t\t\tnew.link_speed = ETH_SPEED_NUM_10G;\n-\t\t\tnew.link_duplex = ETH_LINK_FULL_DUPLEX;\n-\t\t\tnew.link_status = ETH_LINK_UP;\n-\t\t}\n-\n-\t\trc = mpipe_link_compare(&old, &new);\n-\t\tif (rc == 0 || !wait_to_complete)\n-\t\t\tbreak;\n-\n-\t\trte_delay_us(MPIPE_LINK_UPDATE_INTERVAL);\n-\t}\n-\n-\tmpipe_dev_atomic_write_link_status(dev, &new);\n-\treturn rc;\n-}\n-\n-static int\n-mpipe_set_link(struct rte_eth_dev *dev, int up)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tint rc;\n-\n-\trc = gxio_mpipe_link_set_attr(&priv->link,\n-\t\t\t\t      GXIO_MPIPE_LINK_DESIRED_STATE,\n-\t\t\t\t      up ? GXIO_MPIPE_LINK_ANYSPEED : 0);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to set link %s.\\n\",\n-\t\t\tmpipe_name(priv), up ? \"up\" : \"down\");\n-\t} else {\n-\t\tmpipe_link_update(dev, 0);\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static int\n-mpipe_set_link_up(struct rte_eth_dev *dev)\n-{\n-\treturn mpipe_set_link(dev, 1);\n-}\n-\n-static int\n-mpipe_set_link_down(struct rte_eth_dev *dev)\n-{\n-\treturn mpipe_set_link(dev, 0);\n-}\n-\n-static inline void\n-mpipe_dp_enter(struct mpipe_dev_priv *priv)\n-{\n-\t__insn_mtspr(SPR_DSTREAM_PF, 0);\n-\trte_atomic32_inc(&priv->dp_count);\n-}\n-\n-static inline void\n-mpipe_dp_exit(struct mpipe_dev_priv *priv)\n-{\n-\trte_atomic32_dec(&priv->dp_count);\n-}\n-\n-static inline void\n-mpipe_dp_wait(struct mpipe_dev_priv *priv)\n-{\n-\twhile (rte_atomic32_read(&priv->dp_count) != 0) {\n-\t\trte_pause();\n-\t}\n-}\n-\n-static inline int\n-mpipe_mbuf_stack_index(struct mpipe_dev_priv *priv, struct rte_mbuf *mbuf)\n-{\n-\treturn (mbuf->port < RTE_MAX_ETHPORTS) ?\n-\t\tmpipe_priv(&rte_eth_devices[mbuf->port])->stack :\n-\t\tpriv->stack;\n-}\n-\n-static inline struct rte_mbuf *\n-mpipe_recv_mbuf(struct mpipe_dev_priv *priv, gxio_mpipe_idesc_t *idesc,\n-\t\tint in_port)\n-{\n-\tvoid *va = gxio_mpipe_idesc_get_va(idesc);\n-\tuint16_t size = gxio_mpipe_idesc_get_xfer_size(idesc);\n-\tstruct rte_mbuf *mbuf = RTE_PTR_SUB(va, priv->rx_offset);\n-\n-\trte_pktmbuf_reset(mbuf);\n-\tmbuf->data_off = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;\n-\tmbuf->port     = in_port;\n-\tmbuf->data_len = size;\n-\tmbuf->pkt_len  = size;\n-\tmbuf->hash.rss = gxio_mpipe_idesc_get_flow_hash(idesc);\n-\n-\tPMD_DEBUG_RX(\"%s: RX mbuf %p, buffer %p, buf_addr %p, size %d\\n\",\n-\t\t     mpipe_name(priv), mbuf, va, mbuf->buf_addr, size);\n-\n-\treturn mbuf;\n-}\n-\n-static inline void\n-mpipe_recv_push(struct mpipe_dev_priv *priv, struct rte_mbuf *mbuf)\n-{\n-\tconst int offset = RTE_PKTMBUF_HEADROOM + MPIPE_RX_IP_ALIGN;\n-\tvoid *buf_addr = RTE_PTR_ADD(mbuf->buf_addr, offset);\n-\n-\tgxio_mpipe_push_buffer(priv->context, priv->stack, buf_addr);\n-\tPMD_DEBUG_RX(\"%s: Pushed mbuf %p, buffer %p into stack %d\\n\",\n-\t\t     mpipe_name(priv), mbuf, buf_addr, priv->stack);\n-}\n-\n-static inline void\n-mpipe_recv_fill_stack(struct mpipe_dev_priv *priv, int count)\n-{\n-\tstruct rte_mbuf *mbuf;\n-\tint i;\n-\n-\tfor (i = 0; i < count; i++) {\n-\t\tmbuf = rte_mbuf_raw_alloc(priv->rx_mpool);\n-\t\tif (!mbuf)\n-\t\t\tbreak;\n-\t\tmpipe_recv_push(priv, mbuf);\n-\t}\n-\n-\tPMD_DEBUG_RX(\"%s: Filled %d/%d buffers\\n\", mpipe_name(priv), i, count);\n-}\n-\n-static inline void\n-mpipe_recv_flush_stack(struct mpipe_dev_priv *priv)\n-{\n-\tconst int offset = priv->rx_offset & ~RTE_MEMPOOL_ALIGN_MASK;\n-\tuint8_t in_port = priv->port_id;\n-\tstruct rte_mbuf *mbuf;\n-\tvoid *va;\n-\n-\twhile (1) {\n-\t\tva = gxio_mpipe_pop_buffer(priv->context, priv->stack);\n-\t\tif (!va)\n-\t\t\tbreak;\n-\t\tmbuf = RTE_PTR_SUB(va, offset);\n-\n-\t\tPMD_DEBUG_RX(\"%s: Flushing mbuf %p, va %p\\n\",\n-\t\t\t     mpipe_name(priv), mbuf, va);\n-\n-\t\tmbuf->data_off    = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;\n-\t\tmbuf->refcnt      = 1;\n-\t\tmbuf->nb_segs     = 1;\n-\t\tmbuf->port        = in_port;\n-\t\tmbuf->packet_type = 0;\n-\t\tmbuf->data_len    = 0;\n-\t\tmbuf->pkt_len     = 0;\n-\n-\t\t__rte_mbuf_raw_free(mbuf);\n-\t}\n-}\n-\n-static void\n-mpipe_register_segment(struct mpipe_dev_priv *priv, const struct rte_memseg *ms)\n-{\n-\tsize_t size = ms->hugepage_sz;\n-\tuint8_t *addr, *end;\n-\tint rc;\n-\n-\tfor (addr = ms->addr, end = addr + ms->len; addr < end; addr += size) {\n-\t\trc = gxio_mpipe_register_page(priv->context, priv->stack, addr,\n-\t\t\t\t\t      size, 0);\n-\t\tif (rc < 0)\n-\t\t\tbreak;\n-\t}\n-\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Could not register memseg @%p, %d.\\n\",\n-\t\t\tmpipe_name(priv), ms->addr, rc);\n-\t} else {\n-\t\tRTE_LOG(DEBUG, PMD, \"%s: Registered segment %p - %p\\n\",\n-\t\t\tmpipe_name(priv), ms->addr,\n-\t\t\tRTE_PTR_ADD(ms->addr, ms->len - 1));\n-\t}\n-}\n-\n-static int\n-mpipe_recv_init(struct mpipe_dev_priv *priv)\n-{\n-\tconst struct rte_memseg *seg = rte_eal_get_physmem_layout();\n-\tsize_t stack_size;\n-\tvoid *stack_mem;\n-\tint rc;\n-\n-\tif (!priv->rx_mpool) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: No buffer pool.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn -ENODEV;\n-\t}\n-\n-\t/* Allocate one NotifRing for each queue. */\n-\trc = gxio_mpipe_alloc_notif_rings(priv->context, MPIPE_RX_MAX_QUEUES,\n-\t\t\t\t\t  0, 0);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate notif rings.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\tpriv->first_ring = rc;\n-\n-\t/* Allocate a NotifGroup. */\n-\trc = gxio_mpipe_alloc_notif_groups(priv->context, 1, 0, 0);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate rx group.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\tpriv->notif_group = rc;\n-\n-\t/* Allocate required buckets. */\n-\trc = gxio_mpipe_alloc_buckets(priv->context, MPIPE_RX_BUCKETS, 0, 0);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate buckets.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\tpriv->first_bucket = rc;\n-\n-\trc = gxio_mpipe_alloc_buffer_stacks(priv->context, 1, 0, 0);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate buffer stack.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\tpriv->stack = rc;\n-\n-\twhile (seg && seg->addr)\n-\t\tmpipe_register_segment(priv, seg++);\n-\n-\tstack_size = gxio_mpipe_calc_buffer_stack_bytes(MPIPE_RX_STACK_SIZE);\n-\tstack_mem = rte_zmalloc(NULL, stack_size, 65536);\n-\tif (!stack_mem) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate buffer memory.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn -ENOMEM;\n-\t} else {\n-\t\tRTE_LOG(DEBUG, PMD, \"%s: Buffer stack memory %p - %p.\\n\",\n-\t\t\tmpipe_name(priv), stack_mem,\n-\t\t\tRTE_PTR_ADD(stack_mem, stack_size - 1));\n-\t}\n-\n-\trc = gxio_mpipe_init_buffer_stack(priv->context, priv->stack,\n-\t\t\t\t\t  priv->rx_size_code, stack_mem,\n-\t\t\t\t\t  stack_size, 0);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to initialize buffer stack.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-mpipe_xmit_init(struct mpipe_dev_priv *priv)\n-{\n-\tsize_t ring_size;\n-\tvoid *ring_mem;\n-\tint rc;\n-\n-\t/* Allocate eDMA ring. */\n-\trc = gxio_mpipe_alloc_edma_rings(priv->context, 1, 0, 0);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to alloc tx ring.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\tpriv->ering = rc;\n-\n-\trc = mpipe_equeue_size(MPIPE_TX_DESCS);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Cannot allocate %d equeue descs.\\n\",\n-\t\t\tmpipe_name(priv), (int)MPIPE_TX_DESCS);\n-\t\treturn -ENOMEM;\n-\t}\n-\tpriv->equeue_size = rc;\n-\n-\t/* Initialize completion array. */\n-\tring_size = sizeof(priv->tx_comps[0]) * priv->equeue_size;\n-\tpriv->tx_comps = rte_zmalloc(NULL, ring_size, RTE_CACHE_LINE_SIZE);\n-\tif (!priv->tx_comps) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate egress comps.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\t/* Allocate eDMA ring memory. */\n-\tring_size = sizeof(gxio_mpipe_edesc_t) * priv->equeue_size;\n-\tring_mem = rte_zmalloc(NULL, ring_size, ring_size);\n-\tif (!ring_mem) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate egress descs.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn -ENOMEM;\n-\t} else {\n-\t\tRTE_LOG(DEBUG, PMD, \"%s: eDMA ring memory %p - %p.\\n\",\n-\t\t\tmpipe_name(priv), ring_mem,\n-\t\t\tRTE_PTR_ADD(ring_mem, ring_size - 1));\n-\t}\n-\n-\t/* Initialize eDMA ring. */\n-\trc = gxio_mpipe_equeue_init(&priv->equeue, priv->context, priv->ering,\n-\t\t\t\t    priv->channel, ring_mem, ring_size, 0);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init equeue\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-mpipe_link_init(struct mpipe_dev_priv *priv)\n-{\n-\tint rc;\n-\n-\t/* Open the link. */\n-\trc = gxio_mpipe_link_open(&priv->link, priv->context,\n-\t\t\t\t  mpipe_name(priv), GXIO_MPIPE_LINK_AUTO_NONE);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to open link.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\n-\t/* Get the channel index. */\n-\trc = gxio_mpipe_link_channel(&priv->link);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Bad channel\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\tpriv->channel = rc;\n-\n-\treturn 0;\n-}\n-\n-static int\n-mpipe_init(struct mpipe_dev_priv *priv)\n-{\n-\tint rc;\n-\n-\tif (priv->initialized)\n-\t\treturn 0;\n-\n-\trc = mpipe_recv_init(priv);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init rx.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\n-\trc = mpipe_xmit_init(priv);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init tx.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\trte_free(priv);\n-\t\treturn rc;\n-\t}\n-\n-\tpriv->initialized = 1;\n-\n-\treturn 0;\n-}\n-\n-static int\n-mpipe_start(struct rte_eth_dev *dev)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tstruct mpipe_channel_config config;\n-\tstruct mpipe_rx_queue *rx_queue;\n-\tstruct rte_eth_link eth_link;\n-\tunsigned queue, buffers = 0;\n-\tsize_t ring_size;\n-\tvoid *ring_mem;\n-\tint rc;\n-\n-\tmemset(&eth_link, 0, sizeof(eth_link));\n-\tmpipe_dev_atomic_write_link_status(dev, &eth_link);\n-\n-\trc = mpipe_init(priv);\n-\tif (rc < 0)\n-\t\treturn rc;\n-\n-\t/* Initialize NotifRings. */\n-\tfor (queue = 0; queue < priv->nb_rx_queues; queue++) {\n-\t\trx_queue = mpipe_rx_queue(priv, queue);\n-\t\tring_size = rx_queue->q.nb_desc * sizeof(gxio_mpipe_idesc_t);\n-\n-\t\tring_mem = rte_malloc(NULL, ring_size, ring_size);\n-\t\tif (!ring_mem) {\n-\t\t\tRTE_LOG(ERR, PMD, \"%s: Failed to alloc rx descs.\\n\",\n-\t\t\t\tmpipe_name(priv));\n-\t\t\treturn -ENOMEM;\n-\t\t} else {\n-\t\t\tRTE_LOG(DEBUG, PMD, \"%s: iDMA ring %d memory %p - %p.\\n\",\n-\t\t\t\tmpipe_name(priv), queue, ring_mem,\n-\t\t\t\tRTE_PTR_ADD(ring_mem, ring_size - 1));\n-\t\t}\n-\n-\t\trc = gxio_mpipe_iqueue_init(&rx_queue->iqueue, priv->context,\n-\t\t\t\t\t    priv->first_ring + queue, ring_mem,\n-\t\t\t\t\t    ring_size, 0);\n-\t\tif (rc < 0) {\n-\t\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init rx queue.\\n\",\n-\t\t\t\tmpipe_name(priv));\n-\t\t\treturn rc;\n-\t\t}\n-\n-\t\trx_queue->rx_ring_mem = ring_mem;\n-\t\tbuffers += rx_queue->q.nb_desc;\n-\t}\n-\n-\t/* Initialize ingress NotifGroup and buckets. */\n-\trc = gxio_mpipe_init_notif_group_and_buckets(priv->context,\n-\t\t\tpriv->notif_group, priv->first_ring, priv->nb_rx_queues,\n-\t\t\tpriv->first_bucket, MPIPE_RX_BUCKETS,\n-\t\t\tGXIO_MPIPE_BUCKET_STATIC_FLOW_AFFINITY);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init group and buckets.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\n-\t/* Configure the classifier to deliver packets from this port. */\n-\tconfig.enable = 1;\n-\tconfig.first_bucket = priv->first_bucket;\n-\tconfig.num_buckets = MPIPE_RX_BUCKETS;\n-\tmemset(&config.stacks, 0xff, sizeof(config.stacks));\n-\tconfig.stacks.stacks[priv->rx_size_code] = priv->stack;\n-\tconfig.head_room = priv->rx_offset & RTE_MEMPOOL_ALIGN_MASK;\n-\n-\trc = mpipe_channel_config(priv->instance, priv->channel,\n-\t\t\t\t  &config);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to setup classifier.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\n-\t/* Fill empty buffers into the buffer stack. */\n-\tmpipe_recv_fill_stack(priv, buffers);\n-\n-\t/* Bring up the link. */\n-\tmpipe_set_link_up(dev);\n-\n-\t/* Start xmit/recv on queues. */\n-\tfor (queue = 0; queue < priv->nb_tx_queues; queue++)\n-\t\tmpipe_tx_queue(priv, queue)->q.link_status = ETH_LINK_UP;\n-\tfor (queue = 0; queue < priv->nb_rx_queues; queue++)\n-\t\tmpipe_rx_queue(priv, queue)->q.link_status = ETH_LINK_UP;\n-\tpriv->running = 1;\n-\n-\treturn 0;\n-}\n-\n-static void\n-mpipe_stop(struct rte_eth_dev *dev)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tstruct mpipe_channel_config config;\n-\tunsigned queue;\n-\tint rc;\n-\n-\tfor (queue = 0; queue < priv->nb_tx_queues; queue++)\n-\t\tmpipe_tx_queue(priv, queue)->q.link_status = ETH_LINK_DOWN;\n-\tfor (queue = 0; queue < priv->nb_rx_queues; queue++)\n-\t\tmpipe_rx_queue(priv, queue)->q.link_status = ETH_LINK_DOWN;\n-\n-\t/* Make sure the link_status writes land. */\n-\trte_wmb();\n-\n-\t/*\n-\t * Wait for link_status change to register with straggling datapath\n-\t * threads.\n-\t */\n-\tmpipe_dp_wait(priv);\n-\n-\t/* Bring down the link. */\n-\tmpipe_set_link_down(dev);\n-\n-\t/* Remove classifier rules. */\n-\tmemset(&config, 0, sizeof(config));\n-\trc = mpipe_channel_config(priv->instance, priv->channel,\n-\t\t\t\t  &config);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to stop classifier.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t}\n-\n-\t/* Flush completed xmit packets. */\n-\tmpipe_xmit_flush(priv);\n-\n-\t/* Flush buffer stacks. */\n-\tmpipe_recv_flush(priv);\n-\n-\tpriv->running = 0;\n-}\n-\n-static void\n-mpipe_close(struct rte_eth_dev *dev)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tif (priv->running)\n-\t\tmpipe_stop(dev);\n-}\n-\n-static void\n-mpipe_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tstruct mpipe_tx_queue *tx_queue;\n-\tstruct mpipe_rx_queue *rx_queue;\n-\tunsigned i;\n-\tuint16_t idx;\n-\n-\tmemset(stats, 0, sizeof(*stats));\n-\n-\tfor (i = 0; i < priv->nb_tx_queues; i++) {\n-\t\ttx_queue = mpipe_tx_queue(priv, i);\n-\n-\t\tstats->opackets += tx_queue->q.stats.packets;\n-\t\tstats->obytes   += tx_queue->q.stats.bytes;\n-\t\tstats->oerrors  += tx_queue->q.stats.errors;\n-\n-\t\tidx = tx_queue->q.stat_idx;\n-\t\tif (idx != (uint16_t)-1) {\n-\t\t\tstats->q_opackets[idx] += tx_queue->q.stats.packets;\n-\t\t\tstats->q_obytes[idx]   += tx_queue->q.stats.bytes;\n-\t\t\tstats->q_errors[idx]   += tx_queue->q.stats.errors;\n-\t\t}\n-\t}\n-\n-\tfor (i = 0; i < priv->nb_rx_queues; i++) {\n-\t\trx_queue = mpipe_rx_queue(priv, i);\n-\n-\t\tstats->ipackets  += rx_queue->q.stats.packets;\n-\t\tstats->ibytes    += rx_queue->q.stats.bytes;\n-\t\tstats->ierrors   += rx_queue->q.stats.errors;\n-\t\tstats->rx_nombuf += rx_queue->q.stats.nomem;\n-\n-\t\tidx = rx_queue->q.stat_idx;\n-\t\tif (idx != (uint16_t)-1) {\n-\t\t\tstats->q_ipackets[idx] += rx_queue->q.stats.packets;\n-\t\t\tstats->q_ibytes[idx]   += rx_queue->q.stats.bytes;\n-\t\t\tstats->q_errors[idx]   += rx_queue->q.stats.errors;\n-\t\t}\n-\t}\n-}\n-\n-static void\n-mpipe_stats_reset(struct rte_eth_dev *dev)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tstruct mpipe_tx_queue *tx_queue;\n-\tstruct mpipe_rx_queue *rx_queue;\n-\tunsigned i;\n-\n-\tfor (i = 0; i < priv->nb_tx_queues; i++) {\n-\t\ttx_queue = mpipe_tx_queue(priv, i);\n-\t\tmemset(&tx_queue->q.stats, 0, sizeof(tx_queue->q.stats));\n-\t}\n-\n-\tfor (i = 0; i < priv->nb_rx_queues; i++) {\n-\t\trx_queue = mpipe_rx_queue(priv, i);\n-\t\tmemset(&rx_queue->q.stats, 0, sizeof(rx_queue->q.stats));\n-\t}\n-}\n-\n-static int\n-mpipe_queue_stats_mapping_set(struct rte_eth_dev *dev, uint16_t queue_id,\n-\t\t\t      uint8_t stat_idx, uint8_t is_rx)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\n-\tif (is_rx) {\n-\t\tpriv->rx_stat_mapping[stat_idx] = queue_id;\n-\t} else {\n-\t\tpriv->tx_stat_mapping[stat_idx] = queue_id;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-mpipe_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n-\t\t     uint16_t nb_desc, unsigned int socket_id __rte_unused,\n-\t\t     const struct rte_eth_txconf *tx_conf __rte_unused)\n-{\n-\tstruct mpipe_tx_queue *tx_queue = dev->data->tx_queues[queue_idx];\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tuint16_t idx;\n-\n-\ttx_queue = rte_realloc(tx_queue, sizeof(*tx_queue),\n-\t\t\t       RTE_CACHE_LINE_SIZE);\n-\tif (!tx_queue) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate TX queue.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tmemset(&tx_queue->q, 0, sizeof(tx_queue->q));\n-\ttx_queue->q.priv = priv;\n-\ttx_queue->q.queue_idx = queue_idx;\n-\ttx_queue->q.port_id = dev->data->port_id;\n-\ttx_queue->q.nb_desc = nb_desc;\n-\n-\ttx_queue->q.stat_idx = -1;\n-\tfor (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {\n-\t\tif (priv->tx_stat_mapping[idx] == queue_idx)\n-\t\t\ttx_queue->q.stat_idx = idx;\n-\t}\n-\n-\tdev->data->tx_queues[queue_idx] = tx_queue;\n-\n-\treturn 0;\n-}\n-\n-static void\n-mpipe_tx_queue_release(void *_txq)\n-{\n-\trte_free(_txq);\n-}\n-\n-static int\n-mpipe_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n-\t\t     uint16_t nb_desc, unsigned int socket_id __rte_unused,\n-\t\t     const struct rte_eth_rxconf *rx_conf __rte_unused,\n-\t\t     struct rte_mempool *mp)\n-{\n-\tstruct mpipe_rx_queue *rx_queue = dev->data->rx_queues[queue_idx];\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tuint16_t idx;\n-\tint size, rc;\n-\n-\trc = mpipe_iqueue_size(nb_desc);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Cannot allocate %d iqueue descs.\\n\",\n-\t\t\tmpipe_name(priv), (int)nb_desc);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tif (rc != nb_desc) {\n-\t\tRTE_LOG(WARNING, PMD, \"%s: Extending RX descs from %d to %d.\\n\",\n-\t\t\tmpipe_name(priv), (int)nb_desc, rc);\n-\t\tnb_desc = rc;\n-\t}\n-\n-\tsize = sizeof(*rx_queue);\n-\trx_queue = rte_realloc(rx_queue, size, RTE_CACHE_LINE_SIZE);\n-\tif (!rx_queue) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate RX queue.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tmemset(&rx_queue->q, 0, sizeof(rx_queue->q));\n-\trx_queue->q.priv = priv;\n-\trx_queue->q.nb_desc = nb_desc;\n-\trx_queue->q.port_id = dev->data->port_id;\n-\trx_queue->q.queue_idx = queue_idx;\n-\n-\tif (!priv->rx_mpool) {\n-\t\tint size = (rte_pktmbuf_data_room_size(mp) -\n-\t\t\t    RTE_PKTMBUF_HEADROOM -\n-\t\t\t    MPIPE_RX_IP_ALIGN);\n-\n-\t\tpriv->rx_offset = (sizeof(struct rte_mbuf) +\n-\t\t\t\t   rte_pktmbuf_priv_size(mp) +\n-\t\t\t\t   RTE_PKTMBUF_HEADROOM +\n-\t\t\t\t   MPIPE_RX_IP_ALIGN);\n-\t\tif (size < 0) {\n-\t\t\tRTE_LOG(ERR, PMD, \"%s: Bad buffer size %d.\\n\",\n-\t\t\t\tmpipe_name(priv),\n-\t\t\t\trte_pktmbuf_data_room_size(mp));\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\n-\t\tpriv->rx_size_code = mpipe_buffer_size_index(size);\n-\t\tpriv->rx_mpool = mp;\n-\t}\n-\n-\tif (priv->rx_mpool != mp) {\n-\t\tRTE_LOG(WARNING, PMD, \"%s: Ignoring multiple buffer pools.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t}\n-\n-\trx_queue->q.stat_idx = -1;\n-\tfor (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {\n-\t\tif (priv->rx_stat_mapping[idx] == queue_idx)\n-\t\t\trx_queue->q.stat_idx = idx;\n-\t}\n-\n-\tdev->data->rx_queues[queue_idx] = rx_queue;\n-\n-\treturn 0;\n-}\n-\n-static void\n-mpipe_rx_queue_release(void *_rxq)\n-{\n-\trte_free(_rxq);\n-}\n-\n-#define MPIPE_XGBE_ENA_HASH_MULTI\t\\\n-\t(1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_MULTI_SHIFT)\n-#define MPIPE_XGBE_ENA_HASH_UNI\t\t\\\n-\t(1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_UNI_SHIFT)\n-#define MPIPE_XGBE_COPY_ALL\t\t\\\n-\t(1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__COPY_ALL_SHIFT)\n-#define MPIPE_GBE_ENA_MULTI_HASH\t\\\n-\t(1UL << MPIPE_GBE_NETWORK_CONFIGURATION__MULTI_HASH_ENA_SHIFT)\n-#define MPIPE_GBE_ENA_UNI_HASH\t\t\\\n-\t(1UL << MPIPE_GBE_NETWORK_CONFIGURATION__UNI_HASH_ENA_SHIFT)\n-#define MPIPE_GBE_COPY_ALL\t\t\\\n-\t(1UL << MPIPE_GBE_NETWORK_CONFIGURATION__COPY_ALL_SHIFT)\n-\n-static void\n-mpipe_promiscuous_enable(struct rte_eth_dev *dev)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tint64_t reg;\n-\tint addr;\n-\n-\tif (priv->is_xaui) {\n-\t\taddr = MPIPE_XAUI_RECEIVE_CONFIGURATION;\n-\t\treg  = gxio_mpipe_link_mac_rd(&priv->link, addr);\n-\t\treg &= ~MPIPE_XGBE_ENA_HASH_MULTI;\n-\t\treg &= ~MPIPE_XGBE_ENA_HASH_UNI;\n-\t\treg |=  MPIPE_XGBE_COPY_ALL;\n-\t\tgxio_mpipe_link_mac_wr(&priv->link, addr, reg);\n-\t} else {\n-\t\taddr = MPIPE_GBE_NETWORK_CONFIGURATION;\n-\t\treg  = gxio_mpipe_link_mac_rd(&priv->link, addr);\n-\t\treg &= ~MPIPE_GBE_ENA_MULTI_HASH;\n-\t\treg &= ~MPIPE_GBE_ENA_UNI_HASH;\n-\t\treg |=  MPIPE_GBE_COPY_ALL;\n-\t\tgxio_mpipe_link_mac_wr(&priv->link, addr, reg);\n-\t}\n-}\n-\n-static void\n-mpipe_promiscuous_disable(struct rte_eth_dev *dev)\n-{\n-\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n-\tint64_t reg;\n-\tint addr;\n-\n-\tif (priv->is_xaui) {\n-\t\taddr = MPIPE_XAUI_RECEIVE_CONFIGURATION;\n-\t\treg  = gxio_mpipe_link_mac_rd(&priv->link, addr);\n-\t\treg |=  MPIPE_XGBE_ENA_HASH_MULTI;\n-\t\treg |=  MPIPE_XGBE_ENA_HASH_UNI;\n-\t\treg &= ~MPIPE_XGBE_COPY_ALL;\n-\t\tgxio_mpipe_link_mac_wr(&priv->link, addr, reg);\n-\t} else {\n-\t\taddr = MPIPE_GBE_NETWORK_CONFIGURATION;\n-\t\treg  = gxio_mpipe_link_mac_rd(&priv->link, addr);\n-\t\treg |=  MPIPE_GBE_ENA_MULTI_HASH;\n-\t\treg |=  MPIPE_GBE_ENA_UNI_HASH;\n-\t\treg &= ~MPIPE_GBE_COPY_ALL;\n-\t\tgxio_mpipe_link_mac_wr(&priv->link, addr, reg);\n-\t}\n-}\n-\n-static const struct eth_dev_ops mpipe_dev_ops = {\n-\t.dev_infos_get\t         = mpipe_infos_get,\n-\t.dev_configure\t         = mpipe_configure,\n-\t.dev_start\t         = mpipe_start,\n-\t.dev_stop\t         = mpipe_stop,\n-\t.dev_close\t         = mpipe_close,\n-\t.stats_get\t         = mpipe_stats_get,\n-\t.stats_reset\t         = mpipe_stats_reset,\n-\t.queue_stats_mapping_set = mpipe_queue_stats_mapping_set,\n-\t.tx_queue_setup\t         = mpipe_tx_queue_setup,\n-\t.rx_queue_setup\t         = mpipe_rx_queue_setup,\n-\t.tx_queue_release\t = mpipe_tx_queue_release,\n-\t.rx_queue_release\t = mpipe_rx_queue_release,\n-\t.link_update\t         = mpipe_link_update,\n-\t.dev_set_link_up         = mpipe_set_link_up,\n-\t.dev_set_link_down       = mpipe_set_link_down,\n-\t.promiscuous_enable      = mpipe_promiscuous_enable,\n-\t.promiscuous_disable     = mpipe_promiscuous_disable,\n-};\n-\n-static inline void\n-mpipe_xmit_null(struct mpipe_dev_priv *priv, int64_t start, int64_t end)\n-{\n-\tgxio_mpipe_edesc_t null_desc = { { .bound = 1, .ns = 1 } };\n-\tgxio_mpipe_equeue_t *equeue = &priv->equeue;\n-\tint64_t slot;\n-\n-\tfor (slot = start; slot < end; slot++) {\n-\t\tgxio_mpipe_equeue_put_at(equeue, null_desc, slot);\n-\t}\n-}\n-\n-static void\n-mpipe_xmit_flush(struct mpipe_dev_priv *priv)\n-{\n-\tgxio_mpipe_equeue_t *equeue = &priv->equeue;\n-\tint64_t slot;\n-\n-\t/* Post a dummy descriptor and wait for its return. */\n-\tslot = gxio_mpipe_equeue_reserve(equeue, 1);\n-\tif (slot < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to reserve stop slot.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn;\n-\t}\n-\n-\tmpipe_xmit_null(priv, slot, slot + 1);\n-\n-\twhile (!gxio_mpipe_equeue_is_complete(equeue, slot, 1)) {\n-\t\trte_pause();\n-\t}\n-\n-\tfor (slot = 0; slot < priv->equeue_size; slot++) {\n-\t\tif (priv->tx_comps[slot])\n-\t\t\trte_pktmbuf_free_seg(priv->tx_comps[slot]);\n-\t}\n-}\n-\n-static void\n-mpipe_recv_flush(struct mpipe_dev_priv *priv)\n-{\n-\tuint8_t in_port = priv->port_id;\n-\tstruct mpipe_rx_queue *rx_queue;\n-\tgxio_mpipe_iqueue_t *iqueue;\n-\tgxio_mpipe_idesc_t idesc;\n-\tstruct rte_mbuf *mbuf;\n-\tunsigned queue;\n-\n-\t/* Release packets on the buffer stack. */\n-\tmpipe_recv_flush_stack(priv);\n-\n-\t/* Flush packets sitting in recv queues. */\n-\tfor (queue = 0; queue < priv->nb_rx_queues; queue++) {\n-\t\trx_queue = mpipe_rx_queue(priv, queue);\n-\t\tiqueue = &rx_queue->iqueue;\n-\t\twhile (gxio_mpipe_iqueue_try_get(iqueue, &idesc) >= 0) {\n-\t\t\t/* Skip idesc with the 'buffer error' bit set. */\n-\t\t\tif (idesc.be)\n-\t\t\t\tcontinue;\n-\t\t\tmbuf = mpipe_recv_mbuf(priv, &idesc, in_port);\n-\t\t\trte_pktmbuf_free(mbuf);\n-\t\t}\n-\t\trte_free(rx_queue->rx_ring_mem);\n-\t}\n-}\n-\n-static inline uint16_t\n-mpipe_do_xmit(struct mpipe_tx_queue *tx_queue, struct rte_mbuf **tx_pkts,\n-\t      uint16_t nb_pkts)\n-{\n-\tstruct mpipe_dev_priv *priv = tx_queue->q.priv;\n-\tgxio_mpipe_equeue_t *equeue = &priv->equeue;\n-\tunsigned nb_bytes = 0;\n-\tunsigned nb_sent = 0;\n-\tint nb_slots, i;\n-\tuint8_t port_id;\n-\n-\tPMD_DEBUG_TX(\"Trying to transmit %d packets on %s:%d.\\n\",\n-\t\t     nb_pkts, mpipe_name(tx_queue->q.priv),\n-\t\t     tx_queue->q.queue_idx);\n-\n-\t/* Optimistic assumption that we need exactly one slot per packet. */\n-\tnb_slots = RTE_MIN(nb_pkts, MPIPE_TX_DESCS / 2);\n-\n-\tdo {\n-\t\tstruct rte_mbuf *mbuf = NULL, *pkt = NULL;\n-\t\tint64_t slot;\n-\n-\t\t/* Reserve eDMA ring slots. */\n-\t\tslot = gxio_mpipe_equeue_try_reserve_fast(equeue, nb_slots);\n-\t\tif (unlikely(slot < 0)) {\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tfor (i = 0; i < nb_slots; i++) {\n-\t\t\tunsigned idx = (slot + i) & (priv->equeue_size - 1);\n-\t\t\trte_prefetch0(priv->tx_comps[idx]);\n-\t\t}\n-\n-\t\t/* Fill up slots with descriptor and completion info. */\n-\t\tfor (i = 0; i < nb_slots; i++) {\n-\t\t\tunsigned idx = (slot + i) & (priv->equeue_size - 1);\n-\t\t\tgxio_mpipe_edesc_t desc;\n-\t\t\tstruct rte_mbuf *next;\n-\n-\t\t\t/* Starting on a new packet? */\n-\t\t\tif (likely(!mbuf)) {\n-\t\t\t\tint room = nb_slots - i;\n-\n-\t\t\t\tpkt = mbuf = tx_pkts[nb_sent];\n-\n-\t\t\t\t/* Bail out if we run out of descs. */\n-\t\t\t\tif (unlikely(pkt->nb_segs > room))\n-\t\t\t\t\tbreak;\n-\n-\t\t\t\tnb_sent++;\n-\t\t\t}\n-\n-\t\t\t/* We have a segment to send. */\n-\t\t\tnext = mbuf->next;\n-\n-\t\t\tif (priv->tx_comps[idx])\n-\t\t\t\trte_pktmbuf_free_seg(priv->tx_comps[idx]);\n-\n-\t\t\tport_id = (mbuf->port < RTE_MAX_ETHPORTS) ?\n-\t\t\t\t\t\tmbuf->port : priv->port_id;\n-\t\t\tdesc = (gxio_mpipe_edesc_t) { {\n-\t\t\t\t.va        = rte_pktmbuf_mtod(mbuf, uintptr_t),\n-\t\t\t\t.xfer_size = rte_pktmbuf_data_len(mbuf),\n-\t\t\t\t.bound     = next ? 0 : 1,\n-\t\t\t\t.stack_idx = mpipe_mbuf_stack_index(priv, mbuf),\n-\t\t\t\t.size      = priv->rx_size_code,\n-\t\t\t} };\n-\t\t\tif (mpipe_local.mbuf_push_debt[port_id] > 0) {\n-\t\t\t\tmpipe_local.mbuf_push_debt[port_id]--;\n-\t\t\t\tdesc.hwb = 1;\n-\t\t\t\tpriv->tx_comps[idx] = NULL;\n-\t\t\t} else\n-\t\t\t\tpriv->tx_comps[idx] = mbuf;\n-\n-\t\t\tnb_bytes += mbuf->data_len;\n-\t\t\tgxio_mpipe_equeue_put_at(equeue, desc, slot + i);\n-\n-\t\t\tPMD_DEBUG_TX(\"%s:%d: Sending packet %p, len %d\\n\",\n-\t\t\t\t     mpipe_name(priv),\n-\t\t\t\t     tx_queue->q.queue_idx,\n-\t\t\t\t     rte_pktmbuf_mtod(mbuf, void *),\n-\t\t\t\t     rte_pktmbuf_data_len(mbuf));\n-\n-\t\t\tmbuf = next;\n-\t\t}\n-\n-\t\tif (unlikely(nb_sent < nb_pkts)) {\n-\n-\t\t\t/* Fill remaining slots with null descriptors. */\n-\t\t\tmpipe_xmit_null(priv, slot + i, slot + nb_slots);\n-\n-\t\t\t/*\n-\t\t\t * Calculate exact number of descriptors needed for\n-\t\t\t * the next go around.\n-\t\t\t */\n-\t\t\tnb_slots = 0;\n-\t\t\tfor (i = nb_sent; i < nb_pkts; i++) {\n-\t\t\t\tnb_slots += tx_pkts[i]->nb_segs;\n-\t\t\t}\n-\n-\t\t\tnb_slots = RTE_MIN(nb_slots, MPIPE_TX_DESCS / 2);\n-\t\t}\n-\t} while (nb_sent < nb_pkts);\n-\n-\ttx_queue->q.stats.packets += nb_sent;\n-\ttx_queue->q.stats.bytes   += nb_bytes;\n-\n-\treturn nb_sent;\n-}\n-\n-static inline uint16_t\n-mpipe_do_recv(struct mpipe_rx_queue *rx_queue, struct rte_mbuf **rx_pkts,\n-\t      uint16_t nb_pkts)\n-{\n-\tstruct mpipe_dev_priv *priv = rx_queue->q.priv;\n-\tgxio_mpipe_iqueue_t *iqueue = &rx_queue->iqueue;\n-\tgxio_mpipe_idesc_t *first_idesc, *idesc, *last_idesc;\n-\tuint8_t in_port = rx_queue->q.port_id;\n-\tconst unsigned look_ahead = 8;\n-\tint room = nb_pkts, rc = 0;\n-\tunsigned nb_packets = 0;\n-\tunsigned nb_dropped = 0;\n-\tunsigned nb_nomem = 0;\n-\tunsigned nb_bytes = 0;\n-\tunsigned nb_descs, i;\n-\n-\twhile (room && !rc) {\n-\t\tif (rx_queue->avail_descs < room) {\n-\t\t\trc = gxio_mpipe_iqueue_try_peek(iqueue,\n-\t\t\t\t\t\t\t&rx_queue->next_desc);\n-\t\t\trx_queue->avail_descs = rc < 0 ? 0 : rc;\n-\t\t}\n-\n-\t\tif (unlikely(!rx_queue->avail_descs)) {\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tnb_descs = RTE_MIN(room, rx_queue->avail_descs);\n-\n-\t\tfirst_idesc = rx_queue->next_desc;\n-\t\tlast_idesc  = first_idesc + nb_descs;\n-\n-\t\trx_queue->next_desc   += nb_descs;\n-\t\trx_queue->avail_descs -= nb_descs;\n-\n-\t\tfor (i = 1; i < look_ahead; i++) {\n-\t\t\trte_prefetch0(first_idesc + i);\n-\t\t}\n-\n-\t\tPMD_DEBUG_RX(\"%s:%d: Trying to receive %d packets\\n\",\n-\t\t\t     mpipe_name(rx_queue->q.priv),\n-\t\t\t     rx_queue->q.queue_idx,\n-\t\t\t     nb_descs);\n-\n-\t\tfor (idesc = first_idesc; idesc < last_idesc; idesc++) {\n-\t\t\tstruct rte_mbuf *mbuf;\n-\n-\t\t\tPMD_DEBUG_RX(\"%s:%d: processing idesc %d/%d\\n\",\n-\t\t\t\t     mpipe_name(priv),\n-\t\t\t\t     rx_queue->q.queue_idx,\n-\t\t\t\t     nb_packets, nb_descs);\n-\n-\t\t\trte_prefetch0(idesc + look_ahead);\n-\n-\t\t\tPMD_DEBUG_RX(\"%s:%d: idesc %p, %s%s%s%s%s%s%s%s%s%s\"\n-\t\t\t\t     \"size: %d, bkt: %d, chan: %d, ring: %d, sqn: %lu, va: %lu\\n\",\n-\t\t\t\t     mpipe_name(priv),\n-\t\t\t\t     rx_queue->q.queue_idx,\n-\t\t\t\t     idesc,\n-\t\t\t\t     idesc->me ? \"me, \" : \"\",\n-\t\t\t\t     idesc->tr ? \"tr, \" : \"\",\n-\t\t\t\t     idesc->ce ? \"ce, \" : \"\",\n-\t\t\t\t     idesc->ct ? \"ct, \" : \"\",\n-\t\t\t\t     idesc->cs ? \"cs, \" : \"\",\n-\t\t\t\t     idesc->nr ? \"nr, \" : \"\",\n-\t\t\t\t     idesc->sq ? \"sq, \" : \"\",\n-\t\t\t\t     idesc->ts ? \"ts, \" : \"\",\n-\t\t\t\t     idesc->ps ? \"ps, \" : \"\",\n-\t\t\t\t     idesc->be ? \"be, \" : \"\",\n-\t\t\t\t     idesc->l2_size,\n-\t\t\t\t     idesc->bucket_id,\n-\t\t\t\t     idesc->channel,\n-\t\t\t\t     idesc->notif_ring,\n-\t\t\t\t     (unsigned long)idesc->packet_sqn,\n-\t\t\t\t     (unsigned long)idesc->va);\n-\n-\t\t\tif (unlikely(gxio_mpipe_idesc_has_error(idesc))) {\n-\t\t\t\tnb_dropped++;\n-\t\t\t\tgxio_mpipe_iqueue_drop(iqueue, idesc);\n-\t\t\t\tPMD_DEBUG_RX(\"%s:%d: Descriptor error\\n\",\n-\t\t\t\t\t     mpipe_name(rx_queue->q.priv),\n-\t\t\t\t\t     rx_queue->q.queue_idx);\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\n-\t\t\tif (mpipe_local.mbuf_push_debt[in_port] <\n-\t\t\t\t\tMPIPE_BUF_DEBT_THRESHOLD)\n-\t\t\t\tmpipe_local.mbuf_push_debt[in_port]++;\n-\t\t\telse {\n-\t\t\t\tmbuf = rte_mbuf_raw_alloc(priv->rx_mpool);\n-\t\t\t\tif (unlikely(!mbuf)) {\n-\t\t\t\t\tnb_nomem++;\n-\t\t\t\t\tgxio_mpipe_iqueue_drop(iqueue, idesc);\n-\t\t\t\t\tPMD_DEBUG_RX(\"%s:%d: alloc failure\\n\",\n-\t\t\t\t\t     mpipe_name(rx_queue->q.priv),\n-\t\t\t\t\t     rx_queue->q.queue_idx);\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n-\n-\t\t\t\tmpipe_recv_push(priv, mbuf);\n-\t\t\t}\n-\n-\t\t\t/* Get and setup the mbuf for the received packet. */\n-\t\t\tmbuf = mpipe_recv_mbuf(priv, idesc, in_port);\n-\n-\t\t\t/* Update results and statistics counters. */\n-\t\t\trx_pkts[nb_packets] = mbuf;\n-\t\t\tnb_bytes += mbuf->pkt_len;\n-\t\t\tnb_packets++;\n-\t\t}\n-\n-\t\t/*\n-\t\t * We release the ring in bursts, but do not track and release\n-\t\t * buckets.  This therefore breaks dynamic flow affinity, but\n-\t\t * we always operate in static affinity mode, and so we're OK\n-\t\t * with this optimization.\n-\t\t */\n-\t\tgxio_mpipe_iqueue_advance(iqueue, nb_descs);\n-\t\tgxio_mpipe_credit(iqueue->context, iqueue->ring, -1, nb_descs);\n-\n-\t\t/*\n-\t\t * Go around once more if we haven't yet peeked the queue, and\n-\t\t * if we have more room to receive.\n-\t\t */\n-\t\troom = nb_pkts - nb_packets;\n-\t}\n-\n-\trx_queue->q.stats.packets += nb_packets;\n-\trx_queue->q.stats.bytes   += nb_bytes;\n-\trx_queue->q.stats.errors  += nb_dropped;\n-\trx_queue->q.stats.nomem   += nb_nomem;\n-\n-\tPMD_DEBUG_RX(\"%s:%d: RX: %d/%d pkts/bytes, %d/%d drops/nomem\\n\",\n-\t\t     mpipe_name(rx_queue->q.priv), rx_queue->q.queue_idx,\n-\t\t     nb_packets, nb_bytes, nb_dropped, nb_nomem);\n-\n-\treturn nb_packets;\n-}\n-\n-static uint16_t\n-mpipe_recv_pkts(void *_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n-{\n-\tstruct mpipe_rx_queue *rx_queue = _rxq;\n-\tuint16_t result = 0;\n-\n-\tif (rx_queue) {\n-\t\tmpipe_dp_enter(rx_queue->q.priv);\n-\t\tif (likely(rx_queue->q.link_status))\n-\t\t\tresult = mpipe_do_recv(rx_queue, rx_pkts, nb_pkts);\n-\t\tmpipe_dp_exit(rx_queue->q.priv);\n-\t}\n-\n-\treturn result;\n-}\n-\n-static uint16_t\n-mpipe_xmit_pkts(void *_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n-{\n-\tstruct mpipe_tx_queue *tx_queue = _txq;\n-\tuint16_t result = 0;\n-\n-\tif (tx_queue) {\n-\t\tmpipe_dp_enter(tx_queue->q.priv);\n-\t\tif (likely(tx_queue->q.link_status))\n-\t\t\tresult = mpipe_do_xmit(tx_queue, tx_pkts, nb_pkts);\n-\t\tmpipe_dp_exit(tx_queue->q.priv);\n-\t}\n-\n-\treturn result;\n-}\n-\n-static int\n-mpipe_link_mac(const char *ifname, uint8_t *mac)\n-{\n-\tint rc, idx;\n-\tchar name[GXIO_MPIPE_LINK_NAME_LEN];\n-\n-\tfor (idx = 0, rc = 0; !rc; idx++) {\n-\t\trc = gxio_mpipe_link_enumerate_mac(idx, name, mac);\n-\t\tif (!rc && !strncmp(name, ifname, GXIO_MPIPE_LINK_NAME_LEN))\n-\t\t\treturn 0;\n-\t}\n-\treturn -ENODEV;\n-}\n-\n-static int\n-rte_pmd_mpipe_probe_common(struct rte_vdev_driver *drv, const char *ifname,\n-\t\t      const char *params __rte_unused)\n-{\n-\tgxio_mpipe_context_t *context;\n-\tstruct rte_eth_dev *eth_dev;\n-\tstruct mpipe_dev_priv *priv;\n-\tint instance, rc;\n-\tuint8_t *mac;\n-\n-\t/* Get the mPIPE instance that the device belongs to. */\n-\tinstance = gxio_mpipe_link_instance(ifname);\n-\tcontext = mpipe_context(instance);\n-\tif (!context) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: No device for link.\\n\", ifname);\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tpriv = rte_zmalloc(NULL, sizeof(*priv), 0);\n-\tif (!priv) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate priv.\\n\", ifname);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tmemset(&priv->tx_stat_mapping, 0xff, sizeof(priv->tx_stat_mapping));\n-\tmemset(&priv->rx_stat_mapping, 0xff, sizeof(priv->rx_stat_mapping));\n-\tpriv->context = context;\n-\tpriv->instance = instance;\n-\tpriv->is_xaui = (strncmp(ifname, \"xgbe\", 4) == 0);\n-\tpriv->channel = -1;\n-\n-\tmac = priv->mac_addr.addr_bytes;\n-\trc = mpipe_link_mac(ifname, mac);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to enumerate link.\\n\", ifname);\n-\t\trte_free(priv);\n-\t\treturn -ENODEV;\n-\t}\n-\n-\teth_dev = rte_eth_dev_allocate(ifname);\n-\tif (!eth_dev) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate device.\\n\", ifname);\n-\t\trte_free(priv);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tRTE_LOG(INFO, PMD, \"%s: Initialized mpipe device\"\n-\t\t\"(mac %02x:%02x:%02x:%02x:%02x:%02x).\\n\",\n-\t\tifname, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);\n-\n-\tpriv->eth_dev = eth_dev;\n-\tpriv->port_id = eth_dev->data->port_id;\n-\teth_dev->data->dev_private = priv;\n-\teth_dev->data->mac_addrs = &priv->mac_addr;\n-\n-\teth_dev->data->kdrv = RTE_KDRV_NONE;\n-\teth_dev->driver = NULL;\n-\teth_dev->data->drv_name = drv->driver.name;\n-\teth_dev->data->numa_node = instance;\n-\n-\teth_dev->dev_ops      = &mpipe_dev_ops;\n-\teth_dev->rx_pkt_burst = &mpipe_recv_pkts;\n-\teth_dev->tx_pkt_burst = &mpipe_xmit_pkts;\n-\n-\trc = mpipe_link_init(priv);\n-\tif (rc < 0) {\n-\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init link.\\n\",\n-\t\t\tmpipe_name(priv));\n-\t\treturn rc;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-rte_pmd_mpipe_xgbe_probe(const char *ifname, const char *params __rte_unused)\n-{\n-\treturn rte_pmd_mpipe_probe_common(&pmd_mpipe_xgbe_drv, ifname, params);\n-}\n-\n-static int\n-rte_pmd_mpipe_gbe_probe(const char *ifname, const char *params __rte_unused)\n-{\n-\treturn rte_pmd_mpipe_probe_common(&pmd_mpipe_gbe_drv, ifname, params);\n-}\n-\n-static struct rte_vdev_driver pmd_mpipe_xgbe_drv = {\n-\t.probe = rte_pmd_mpipe_xgbe_probe,\n-};\n-\n-static struct rte_vdev_driver pmd_mpipe_gbe_drv = {\n-\t.probe = rte_pmd_mpipe_gbe_probe,\n-};\n-\n-RTE_PMD_REGISTER_VDEV(net_mpipe_xgbe, pmd_mpipe_xgbe_drv);\n-RTE_PMD_REGISTER_ALIAS(net_mpipe_xgbe, xgbe);\n-RTE_PMD_REGISTER_VDEV(net_mpipe_gbe, pmd_mpipe_gbe_drv);\n-RTE_PMD_REGISTER_ALIAS(net_mpipe_gbe, gbe);\n-\n-static void __attribute__((constructor, used))\n-mpipe_init_contexts(void)\n-{\n-\tstruct mpipe_context *context;\n-\tint rc, instance;\n-\n-\tfor (instance = 0; instance < GXIO_MPIPE_INSTANCE_MAX; instance++) {\n-\t\tcontext = &mpipe_contexts[instance];\n-\n-\t\trte_spinlock_init(&context->lock);\n-\t\trc = gxio_mpipe_init(&context->context, instance);\n-\t\tif (rc < 0)\n-\t\t\tbreak;\n-\t}\n-\n-\tmpipe_instances = instance;\n-}\ndiff --git a/drivers/net/mpipe/rte_pmd_mpipe_version.map b/drivers/net/mpipe/rte_pmd_mpipe_version.map\ndeleted file mode 100644\nindex ad607bb..0000000\n--- a/drivers/net/mpipe/rte_pmd_mpipe_version.map\n+++ /dev/null\n@@ -1,3 +0,0 @@\n-DPDK_2.2 {\n-\tlocal: *;\n-};\ndiff --git a/lib/librte_eal/common/arch/tile/rte_cpuflags.c b/lib/librte_eal/common/arch/tile/rte_cpuflags.c\ndeleted file mode 100644\nindex a2b6c51..0000000\n--- a/lib/librte_eal/common/arch/tile/rte_cpuflags.c\n+++ /dev/null\n@@ -1,47 +0,0 @@\n-/*\n- *   BSD LICENSE\n- *\n- *   Copyright (C) EZchip Semiconductor Ltd. 2015.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of EZchip Semiconductor nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-*/\n-\n-#include \"rte_cpuflags.h\"\n-\n-#include <errno.h>\n-\n-const struct feature_entry rte_cpu_feature_table[] = {\n-};\n-\n-/*\n- * Checks if a particular flag is available on current machine.\n- */\n-int\n-rte_cpu_get_flag_enabled(__attribute__((unused)) enum rte_cpu_flag_t feature)\n-{\n-\treturn -ENOENT;\n-}\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_atomic.h b/lib/librte_eal/common/include/arch/tile/rte_atomic.h\ndeleted file mode 100644\nindex 1f332ee..0000000\n--- a/lib/librte_eal/common/include/arch/tile/rte_atomic.h\n+++ /dev/null\n@@ -1,98 +0,0 @@\n-/*\n- *   BSD LICENSE\n- *\n- *   Copyright (C) EZchip Semiconductor Ltd. 2015.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of EZchip Semiconductor nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-*/\n-\n-#ifndef _RTE_ATOMIC_TILE_H_\n-#define _RTE_ATOMIC_TILE_H_\n-\n-#ifndef RTE_FORCE_INTRINSICS\n-#  error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n-#endif\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-#include \"generic/rte_atomic.h\"\n-\n-/**\n- * General memory barrier.\n- *\n- * Guarantees that the LOAD and STORE operations generated before the\n- * barrier occur before the LOAD and STORE operations generated after.\n- * This function is architecture dependent.\n- */\n-static inline void rte_mb(void)\n-{\n-\t__sync_synchronize();\n-}\n-\n-/**\n- * Write memory barrier.\n- *\n- * Guarantees that the STORE operations generated before the barrier\n- * occur before the STORE operations generated after.\n- * This function is architecture dependent.\n- */\n-static inline void rte_wmb(void)\n-{\n-\t__sync_synchronize();\n-}\n-\n-/**\n- * Read memory barrier.\n- *\n- * Guarantees that the LOAD operations generated before the barrier\n- * occur before the LOAD operations generated after.\n- * This function is architecture dependent.\n- */\n-static inline void rte_rmb(void)\n-{\n-\t__sync_synchronize();\n-}\n-\n-#define rte_smp_mb() rte_mb()\n-\n-#define rte_smp_wmb() rte_compiler_barrier()\n-\n-#define rte_smp_rmb() rte_compiler_barrier()\n-\n-#define rte_io_mb() rte_mb()\n-\n-#define rte_io_wmb() rte_compiler_barrier()\n-\n-#define rte_io_rmb() rte_compiler_barrier()\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_ATOMIC_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_byteorder.h b/lib/librte_eal/common/include/arch/tile/rte_byteorder.h\ndeleted file mode 100644\nindex 7239e43..0000000\n--- a/lib/librte_eal/common/include/arch/tile/rte_byteorder.h\n+++ /dev/null\n@@ -1,91 +0,0 @@\n-/*\n- *   BSD LICENSE\n- *\n- *   Copyright (C) EZchip Semiconductor Ltd. 2015.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of EZchip Semiconductor nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-*/\n-\n-#ifndef _RTE_BYTEORDER_TILE_H_\n-#define _RTE_BYTEORDER_TILE_H_\n-\n-#ifndef RTE_FORCE_INTRINSICS\n-#  error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n-#endif\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-#include \"generic/rte_byteorder.h\"\n-\n-#if !(__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8))\n-#define rte_bswap16(x) rte_constant_bswap16(x)\n-#endif\n-\n-#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n-\n-#define rte_cpu_to_le_16(x) (x)\n-#define rte_cpu_to_le_32(x) (x)\n-#define rte_cpu_to_le_64(x) (x)\n-\n-#define rte_cpu_to_be_16(x) rte_bswap16(x)\n-#define rte_cpu_to_be_32(x) rte_bswap32(x)\n-#define rte_cpu_to_be_64(x) rte_bswap64(x)\n-\n-#define rte_le_to_cpu_16(x) (x)\n-#define rte_le_to_cpu_32(x) (x)\n-#define rte_le_to_cpu_64(x) (x)\n-\n-#define rte_be_to_cpu_16(x) rte_bswap16(x)\n-#define rte_be_to_cpu_32(x) rte_bswap32(x)\n-#define rte_be_to_cpu_64(x) rte_bswap64(x)\n-\n-#else /* RTE_BIG_ENDIAN */\n-\n-#define rte_cpu_to_le_16(x) rte_bswap16(x)\n-#define rte_cpu_to_le_32(x) rte_bswap32(x)\n-#define rte_cpu_to_le_64(x) rte_bswap64(x)\n-\n-#define rte_cpu_to_be_16(x) (x)\n-#define rte_cpu_to_be_32(x) (x)\n-#define rte_cpu_to_be_64(x) (x)\n-\n-#define rte_le_to_cpu_16(x) rte_bswap16(x)\n-#define rte_le_to_cpu_32(x) rte_bswap32(x)\n-#define rte_le_to_cpu_64(x) rte_bswap64(x)\n-\n-#define rte_be_to_cpu_16(x) (x)\n-#define rte_be_to_cpu_32(x) (x)\n-#define rte_be_to_cpu_64(x) (x)\n-#endif\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_BYTEORDER_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h b/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h\ndeleted file mode 100644\nindex 1849b52..0000000\n--- a/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h\n+++ /dev/null\n@@ -1,53 +0,0 @@\n-/*\n- *   BSD LICENSE\n- *\n- *   Copyright (C) EZchip Semiconductor Ltd. 2015.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of EZchip Semiconductor nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-*/\n-\n-#ifndef _RTE_CPUFLAGS_TILE_H_\n-#define _RTE_CPUFLAGS_TILE_H_\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-/**\n- * Enumeration of all CPU features supported\n- */\n-enum rte_cpu_flag_t {\n-\tRTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */\n-};\n-\n-#include \"generic/rte_cpuflags.h\"\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_CPUFLAGS_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_cycles.h b/lib/librte_eal/common/include/arch/tile/rte_cycles.h\ndeleted file mode 100644\nindex 0b2200a..0000000\n--- a/lib/librte_eal/common/include/arch/tile/rte_cycles.h\n+++ /dev/null\n@@ -1,70 +0,0 @@\n-/*\n- *   BSD LICENSE\n- *\n- *   Copyright (C) EZchip Semiconductor Ltd. 2015.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of EZchip Semiconductor nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-*/\n-\n-#ifndef _RTE_CYCLES_TILE_H_\n-#define _RTE_CYCLES_TILE_H_\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-#include <arch/cycle.h>\n-\n-#include \"generic/rte_cycles.h\"\n-\n-/**\n- * Read the time base register.\n- *\n- * @return\n- *   The time base for this lcore.\n- */\n-static inline uint64_t\n-rte_rdtsc(void)\n-{\n-\treturn get_cycle_count();\n-}\n-\n-static inline uint64_t\n-rte_rdtsc_precise(void)\n-{\n-\trte_mb();\n-\treturn rte_rdtsc();\n-}\n-\n-static inline uint64_t\n-rte_get_tsc_cycles(void) { return rte_rdtsc(); }\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_CYCLES_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_io.h b/lib/librte_eal/common/include/arch/tile/rte_io.h\ndeleted file mode 100644\nindex 9c8588f..0000000\n--- a/lib/librte_eal/common/include/arch/tile/rte_io.h\n+++ /dev/null\n@@ -1,47 +0,0 @@\n-/*\n- *   BSD LICENSE\n- *\n- *   Copyright(c) 2016 Cavium networks. All rights reserved.\n- *   All rights reserved.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of Cavium networks nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n- */\n-\n-#ifndef _RTE_IO_TILE_H_\n-#define _RTE_IO_TILE_H_\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-#include \"generic/rte_io.h\"\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_IO_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_memcpy.h b/lib/librte_eal/common/include/arch/tile/rte_memcpy.h\ndeleted file mode 100644\nindex e606957..0000000\n--- a/lib/librte_eal/common/include/arch/tile/rte_memcpy.h\n+++ /dev/null\n@@ -1,87 +0,0 @@\n-/*\n- *   BSD LICENSE\n- *\n- *   Copyright (C) EZchip Semiconductor Ltd. 2015.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of EZchip Semiconductor nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-*/\n-\n-#ifndef _RTE_MEMCPY_TILE_H_\n-#define _RTE_MEMCPY_TILE_H_\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-#include <stdint.h>\n-#include <string.h>\n-\n-#include \"generic/rte_memcpy.h\"\n-\n-static inline void\n-rte_mov16(uint8_t *dst, const uint8_t *src)\n-{\n-\tmemcpy(dst, src, 16);\n-}\n-\n-static inline void\n-rte_mov32(uint8_t *dst, const uint8_t *src)\n-{\n-\tmemcpy(dst, src, 32);\n-}\n-\n-static inline void\n-rte_mov48(uint8_t *dst, const uint8_t *src)\n-{\n-\tmemcpy(dst, src, 48);\n-}\n-\n-static inline void\n-rte_mov64(uint8_t *dst, const uint8_t *src)\n-{\n-\tmemcpy(dst, src, 64);\n-}\n-\n-static inline void\n-rte_mov128(uint8_t *dst, const uint8_t *src)\n-{\n-\tmemcpy(dst, src, 128);\n-}\n-\n-static inline void\n-rte_mov256(uint8_t *dst, const uint8_t *src)\n-{\n-\tmemcpy(dst, src, 256);\n-}\n-\n-#define rte_memcpy(d, s, n)\tmemcpy((d), (s), (n))\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_MEMCPY_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_prefetch.h b/lib/librte_eal/common/include/arch/tile/rte_prefetch.h\ndeleted file mode 100644\nindex 7a1bb93..0000000\n--- a/lib/librte_eal/common/include/arch/tile/rte_prefetch.h\n+++ /dev/null\n@@ -1,67 +0,0 @@\n-/*\n- *   BSD LICENSE\n- *\n- *   Copyright (C) EZchip Semiconductor Ltd. 2015.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of EZchip Semiconductor nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-*/\n-\n-#ifndef _RTE_PREFETCH_TILE_H_\n-#define _RTE_PREFETCH_TILE_H_\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-#include \"generic/rte_prefetch.h\"\n-\n-static inline void rte_prefetch0(const volatile void *p)\n-{\n-\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 3);\n-}\n-\n-static inline void rte_prefetch1(const volatile void *p)\n-{\n-\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 2);\n-}\n-\n-static inline void rte_prefetch2(const volatile void *p)\n-{\n-\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 1);\n-}\n-\n-static inline void rte_prefetch_non_temporal(const volatile void *p)\n-{\n-\t/* non-temporal version not available, fallback to rte_prefetch0 */\n-\trte_prefetch0(p);\n-}\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_PREFETCH_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_rwlock.h b/lib/librte_eal/common/include/arch/tile/rte_rwlock.h\ndeleted file mode 100644\nindex 8f67a19..0000000\n--- a/lib/librte_eal/common/include/arch/tile/rte_rwlock.h\n+++ /dev/null\n@@ -1,70 +0,0 @@\n-/*\n- *   BSD LICENSE\n- *\n- *   Copyright (C) EZchip Semiconductor Ltd. 2015.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of EZchip Semiconductor nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-*/\n-\n-#ifndef _RTE_RWLOCK_TILE_H_\n-#define _RTE_RWLOCK_TILE_H_\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-#include \"generic/rte_rwlock.h\"\n-\n-static inline void\n-rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)\n-{\n-\trte_rwlock_read_lock(rwl);\n-}\n-\n-static inline void\n-rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)\n-{\n-\trte_rwlock_read_unlock(rwl);\n-}\n-\n-static inline void\n-rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)\n-{\n-\trte_rwlock_write_lock(rwl);\n-}\n-\n-static inline void\n-rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)\n-{\n-\trte_rwlock_write_unlock(rwl);\n-}\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_RWLOCK_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_spinlock.h b/lib/librte_eal/common/include/arch/tile/rte_spinlock.h\ndeleted file mode 100644\nindex e91f99e..0000000\n--- a/lib/librte_eal/common/include/arch/tile/rte_spinlock.h\n+++ /dev/null\n@@ -1,92 +0,0 @@\n-/*\n- *   BSD LICENSE\n- *\n- *   Copyright (C) EZchip Semiconductor Ltd. 2015.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of EZchip Semiconductor nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-*/\n-\n-#ifndef _RTE_SPINLOCK_TILE_H_\n-#define _RTE_SPINLOCK_TILE_H_\n-\n-#ifndef RTE_FORCE_INTRINSICS\n-#  error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n-#endif\n-\n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n-\n-#include <rte_common.h>\n-#include \"generic/rte_spinlock.h\"\n-\n-static inline int rte_tm_supported(void)\n-{\n-\treturn 0;\n-}\n-\n-static inline void\n-rte_spinlock_lock_tm(rte_spinlock_t *sl)\n-{\n-\trte_spinlock_lock(sl); /* fall-back */\n-}\n-\n-static inline int\n-rte_spinlock_trylock_tm(rte_spinlock_t *sl)\n-{\n-\treturn rte_spinlock_trylock(sl);\n-}\n-\n-static inline void\n-rte_spinlock_unlock_tm(rte_spinlock_t *sl)\n-{\n-\trte_spinlock_unlock(sl);\n-}\n-\n-static inline void\n-rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)\n-{\n-\trte_spinlock_recursive_lock(slr); /* fall-back */\n-}\n-\n-static inline void\n-rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)\n-{\n-\trte_spinlock_recursive_unlock(slr);\n-}\n-\n-static inline int\n-rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)\n-{\n-\treturn rte_spinlock_recursive_trylock(slr);\n-}\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_SPINLOCK_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_vect.h b/lib/librte_eal/common/include/arch/tile/rte_vect.h\ndeleted file mode 100644\nindex f1e1709..0000000\n--- a/lib/librte_eal/common/include/arch/tile/rte_vect.h\n+++ /dev/null\n@@ -1,38 +0,0 @@\n-/*-\n- *   BSD LICENSE\n- *\n- *   Copyright 2016 6WIND S.A.\n- *\n- *   Redistribution and use in source and binary forms, with or without\n- *   modification, are permitted provided that the following conditions\n- *   are met:\n- *\n- *     * Redistributions of source code must retain the above copyright\n- *       notice, this list of conditions and the following disclaimer.\n- *     * Redistributions in binary form must reproduce the above copyright\n- *       notice, this list of conditions and the following disclaimer in\n- *       the documentation and/or other materials provided with the\n- *       distribution.\n- *     * Neither the name of 6WIND S.A. nor the names of its\n- *       contributors may be used to endorse or promote products derived\n- *       from this software without specific prior written permission.\n- *\n- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n- */\n-\n-#ifndef _RTE_VECT_TILE_H_\n-#define _RTE_VECT_TILE_H_\n-\n-#include \"generic/rte_vect.h\"\n-\n-#endif /* _RTE_VECT_TILE_H_ */\ndiff --git a/mk/arch/tile/rte.vars.mk b/mk/arch/tile/rte.vars.mk\ndeleted file mode 100644\nindex 5ad3738..0000000\n--- a/mk/arch/tile/rte.vars.mk\n+++ /dev/null\n@@ -1,39 +0,0 @@\n-#   BSD LICENSE\n-#\n-#   Copyright (C) EZchip Semiconductor Ltd. 2015.\n-#\n-#   Redistribution and use in source and binary forms, with or without\n-#   modification, are permitted provided that the following conditions\n-#   are met:\n-#\n-#     * Redistributions of source code must retain the above copyright\n-#       notice, this list of conditions and the following disclaimer.\n-#     * Redistributions in binary form must reproduce the above copyright\n-#       notice, this list of conditions and the following disclaimer in\n-#       the documentation and/or other materials provided with the\n-#       distribution.\n-#     * Neither the name of EZchip Semiconductor nor the names of its\n-#       contributors may be used to endorse or promote products derived\n-#       from this software without specific prior written permission.\n-#\n-#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n-#   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n-#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n-#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n-#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n-#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n-#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n-#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n-#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n-#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n-#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n-\n-\n-ARCH  ?= tile\n-CROSS ?=\n-\n-CPU_CFLAGS  ?=\n-CPU_LDFLAGS ?=\n-CPU_ASFLAGS ?=\n-\n-export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 92f3635..cf417f3 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -116,7 +116,6 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_I40E_PMD)       += -lrte_pmd_i40e\n _LDLIBS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD)      += -lrte_pmd_ixgbe\n _LDLIBS-$(CONFIG_RTE_LIBRTE_MLX4_PMD)       += -lrte_pmd_mlx4 -libverbs\n _LDLIBS-$(CONFIG_RTE_LIBRTE_MLX5_PMD)       += -lrte_pmd_mlx5 -libverbs\n-_LDLIBS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD)      += -lrte_pmd_mpipe -lgxio\n _LDLIBS-$(CONFIG_RTE_LIBRTE_NFP_PMD)        += -lrte_pmd_nfp -lm\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL)       += -lrte_pmd_null\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_PCAP)       += -lrte_pmd_pcap -lpcap\n",
    "prefixes": [
        "dpdk-dev"
    ]
}