Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/19890/?format=api
{ "id": 19890, "url": "http://patches.dpdk.org/api/patches/19890/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1485172803-17288-19-git-send-email-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1485172803-17288-19-git-send-email-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1485172803-17288-19-git-send-email-hemant.agrawal@nxp.com", "date": "2017-01-23T11:59:48", "name": "[dpdk-dev,PATCHv6,18/33] net/dpaa2: adding eth ops to dpaa2", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "826d76478d0297e17a86319de7883afcde13e70b", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1485172803-17288-19-git-send-email-hemant.agrawal@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/19890/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/19890/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id A924CFA47;\n\tMon, 23 Jan 2017 13:01:45 +0100 (CET)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n\t(mail-sn1nam02on0069.outbound.protection.outlook.com [104.47.36.69])\n\tby dpdk.org (Postfix) with ESMTP id 57E9AF95A\n\tfor <dev@dpdk.org>; Mon, 23 Jan 2017 13:01:14 +0100 (CET)", "from CY1PR03CA0013.namprd03.prod.outlook.com (10.174.128.23) by\n\tBY2PR0301MB1573.namprd03.prod.outlook.com (10.163.28.15) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.860.13; Mon, 23 Jan 2017 12:01:12 +0000", "from BY2FFO11FD028.protection.gbl (2a01:111:f400:7c0c::176) by\n\tCY1PR03CA0013.outlook.office365.com (2603:10b6:600::23) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.860.13 via Frontend Transport; Mon, 23 Jan 2017 12:01:12 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBY2FFO11FD028.mail.protection.outlook.com (10.1.15.217) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.803.8\n\tvia Frontend Transport; Mon, 23 Jan 2017 12:01:12 +0000", "from bf-netperf1.idc ([10.232.134.28])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv0NC07eg019311; Mon, 23 Jan 2017 05:01:09 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com;\n\tnxp.com; \n\tdkim=none (message not signed) header.d=none;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,\n\t<shreyansh.jain@nxp.com>, <john.mcnamara@intel.com>,\n\t<ferruh.yigit@intel.com>, <jerin.jacob@caviumnetworks.com>,\n\tHemant Agrawal <hemant.agrawal@nxp.com>", "Date": "Mon, 23 Jan 2017 17:29:48 +0530", "Message-ID": "<1485172803-17288-19-git-send-email-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1485172803-17288-1-git-send-email-hemant.agrawal@nxp.com>", "References": "<1484832240-2048-1-git-send-email-hemant.agrawal@nxp.com>\n\t<1485172803-17288-1-git-send-email-hemant.agrawal@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131296464722135840;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0; RULEID:(22001);\n\tSRVR:BY2PR0301MB1573; ", "X-Microsoft-Antispam-PRVS": "<BY2PR0301MB1573695B9525F85F738EA60189720@BY2PR0301MB1573.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197)(275809806118684); ", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(6095060)(601004)(2401047)(13023025)(13017025)(13015025)(13024025)(13018025)(5005006)(8121501046)(3002001)(10201501046)(6055026)(6096035)(20161123561025)(20161123559025)(20161123556025)(20161123563025)(20161123565025);\n\tSRVR:BY2PR0301MB1573; BCL:0; PCL:0; RULEID:(400006);\n\tSRVR:BY2PR0301MB1573; ", "X-Forefront-PRVS": "0196A226D1", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Jan 2017 12:01:12.0107\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY2PR0301MB1573", "Subject": "[dpdk-dev] [PATCHv6 18/33] net/dpaa2: adding eth ops to dpaa2", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n doc/guides/nics/features/dpaa2.ini | 1 +\n drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 20 ++\n drivers/net/dpaa2/Makefile | 3 +\n drivers/net/dpaa2/dpaa2_ethdev.c | 412 +++++++++++++++++++++++++++++++-\n drivers/net/dpaa2/dpaa2_ethdev.h | 15 ++\n 5 files changed, 450 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/features/dpaa2.ini b/doc/guides/nics/features/dpaa2.ini\nindex b176208..0b59725 100644\n--- a/doc/guides/nics/features/dpaa2.ini\n+++ b/doc/guides/nics/features/dpaa2.ini\n@@ -4,6 +4,7 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Queue start/stop = Y\n Linux VFIO = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\nindex ad2847f..42c5517 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n@@ -37,9 +37,12 @@\n #include <mc/fsl_mc_sys.h>\n #include <fsl_qbman_portal.h>\n \n+#define DPAA2_DQRR_RING_SIZE\t16\n+\t/** <Maximum number of slots available in RX ring*/\n \n #define MC_PORTAL_INDEX\t\t0\n #define NUM_DPIO_REGIONS\t2\n+#define NUM_DQS_PER_QUEUE 2\n \n #define MEMPOOL_F_HW_PKT_POOL 0x8000 /**< mpool flag to check offloaded pool */\n \n@@ -79,6 +82,23 @@ struct dpaa2_dpbp_dev {\n \tuint32_t dpbp_id; /*HW ID for DPBP object */\n };\n \n+struct queue_storage_info_t {\n+\tstruct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];\n+};\n+\n+struct dpaa2_queue {\n+\tstruct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */\n+\tvoid *dev;\n+\tint32_t eventfd;\t/*!< Event Fd of this queue */\n+\tuint32_t fqid;\t\t/*!< Unique ID of this queue */\n+\tuint8_t tc_index;\t/*!< traffic class identifier */\n+\tuint16_t flow_id;\t/*!< To be used by DPAA2 frmework */\n+\tuint64_t rx_pkts;\n+\tuint64_t tx_pkts;\n+\tuint64_t err_pkts;\n+\tstruct queue_storage_info_t *q_storage;\n+};\n+\n /*! Global MCP list */\n extern void *(*rte_mcp_ptr_list);\n \ndiff --git a/drivers/net/dpaa2/Makefile b/drivers/net/dpaa2/Makefile\nindex 6e0396a..5fb5f67 100644\n--- a/drivers/net/dpaa2/Makefile\n+++ b/drivers/net/dpaa2/Makefile\n@@ -46,6 +46,8 @@ endif\n \n CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2\n CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc\n+CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc\n+CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/portal\n CFLAGS += -I$(RTE_SDK)/drivers/common/dpaa2/qbman/include\n CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal\n \n@@ -59,6 +61,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += dpaa2_ethdev.c\n \n # library dependencies\n DEPDIRS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += lib/librte_eal lib/librte_ether\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += lib/librte_common_dpaa2_qbman\n DEPDIRS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += lib/librte_bus_fslmc\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c\nindex ead6a2c..df16159 100644\n--- a/drivers/net/dpaa2/dpaa2_ethdev.c\n+++ b/drivers/net/dpaa2/dpaa2_ethdev.c\n@@ -47,32 +47,442 @@\n \n #include <fslmc_logs.h>\n #include <fslmc_vfio.h>\n+#include <dpaa2_hw_pvt.h>\n+\n #include \"dpaa2_ethdev.h\"\n \n static struct rte_dpaa2_driver rte_dpaa2_pmd;\n \n+static void\n+dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n+{\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tdev_info->if_index = priv->hw_id;\n+\n+\tdev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;\n+\tdev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;\n+\n+\tdev_info->speed_capa = ETH_LINK_SPEED_1G |\n+\t\t\tETH_LINK_SPEED_2_5G |\n+\t\t\tETH_LINK_SPEED_10G;\n+}\n+\n+static int\n+dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)\n+{\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\tuint16_t dist_idx;\n+\tuint32_t vq_id;\n+\tstruct dpaa2_queue *mc_q, *mcq;\n+\tuint32_t tot_queues;\n+\tint i;\n+\tstruct dpaa2_queue *dpaa2_q;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttot_queues = priv->nb_rx_queues + priv->nb_tx_queues;\n+\tmc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,\n+\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (!mc_q) {\n+\t\tPMD_INIT_LOG(ERR, \"malloc failed for rx/tx queues\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tfor (i = 0; i < priv->nb_rx_queues; i++) {\n+\t\tmc_q->dev = dev;\n+\t\tpriv->rx_vq[i] = mc_q++;\n+\t\tdpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];\n+\t\tdpaa2_q->q_storage = rte_malloc(\"dq_storage\",\n+\t\t\t\t\tsizeof(struct queue_storage_info_t),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\t\tif (!dpaa2_q->q_storage)\n+\t\t\tgoto fail;\n+\n+\t\tmemset(dpaa2_q->q_storage, 0,\n+\t\t sizeof(struct queue_storage_info_t));\n+\t\tdpaa2_q->q_storage->dq_storage[0] = rte_malloc(NULL,\n+\t\t\tDPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\t}\n+\n+\tfor (i = 0; i < priv->nb_tx_queues; i++) {\n+\t\tmc_q->dev = dev;\n+\t\tmc_q->flow_id = DPNI_NEW_FLOW_ID;\n+\t\tpriv->tx_vq[i] = mc_q++;\n+\t}\n+\n+\tvq_id = 0;\n+\tfor (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {\n+\t\tmcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];\n+\t\tmcq->tc_index = DPAA2_DEF_TC;\n+\t\tmcq->flow_id = dist_idx;\n+\t\tvq_id++;\n+\t}\n+\n+\treturn 0;\n+fail:\n+\ti -= 1;\n+\tmc_q = priv->rx_vq[0];\n+\twhile (i >= 0) {\n+\t\tdpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];\n+\t\trte_free(dpaa2_q->q_storage->dq_storage[0]);\n+\t\trte_free(dpaa2_q->q_storage);\n+\t\tpriv->rx_vq[i--] = NULL;\n+\t}\n+\trte_free(mc_q);\n+\treturn -1;\n+}\n+\n+static int\n+dpaa2_eth_dev_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_eth_dev_data *data = dev->data;\n+\tstruct rte_eth_conf *eth_conf = &data->dev_conf;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Check for correct configuration */\n+\tif (eth_conf->rxmode.mq_mode != ETH_MQ_RX_RSS &&\n+\t data->nb_rx_queues > 1) {\n+\t\tPMD_INIT_LOG(ERR, \"Distribution is not enabled, \"\n+\t\t\t \"but Rx queues more than 1\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Function to setup RX flow information. It contains traffic class ID,\n+ * flow ID, destination configuration etc.\n+ */\n+static int\n+dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,\n+\t\t\t uint16_t rx_queue_id,\n+\t\t\t uint16_t nb_rx_desc __rte_unused,\n+\t\t\t unsigned int socket_id __rte_unused,\n+\t\t\t const struct rte_eth_rxconf *rx_conf __rte_unused,\n+\t\t\t struct rte_mempool *mb_pool)\n+{\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n+\tstruct dpaa2_queue *dpaa2_q;\n+\tstruct dpni_queue cfg;\n+\tuint8_t options = 0;\n+\tuint8_t flow_id;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tPMD_INIT_LOG(DEBUG, \"dev =%p, queue =%d, pool = %p, conf =%p\",\n+\t\t dev, rx_queue_id, mb_pool, rx_conf);\n+\n+\tdpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];\n+\tdpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */\n+\n+\t/*Get the tc id and flow id from given VQ id*/\n+\tflow_id = rx_queue_id;\n+\tmemset(&cfg, 0, sizeof(struct dpni_queue));\n+\n+\toptions = options | DPNI_QUEUE_OPT_USER_CTX;\n+\tcfg.user_context = (uint64_t)(dpaa2_q);\n+\n+\tret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,\n+\t\t\t dpaa2_q->tc_index, flow_id, options, &cfg);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Error in setting the rx flow: = %d\\n\", ret);\n+\t\treturn -1;\n+\t}\n+\n+\tdev->data->rx_queues[rx_queue_id] = dpaa2_q;\n+\treturn 0;\n+}\n+\n+static int\n+dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,\n+\t\t\t uint16_t tx_queue_id,\n+\t\t\t uint16_t nb_tx_desc __rte_unused,\n+\t\t\t unsigned int socket_id __rte_unused,\n+\t\t\t const struct rte_eth_txconf *tx_conf __rte_unused)\n+{\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\tstruct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)\n+\t\tpriv->tx_vq[tx_queue_id];\n+\tstruct fsl_mc_io *dpni = priv->hw;\n+\tstruct dpni_queue tx_conf_cfg;\n+\tstruct dpni_queue tx_flow_cfg;\n+\tuint8_t options = 0, flow_id;\n+\tuint32_t tc_id;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Return if queue already configured */\n+\tif (dpaa2_q->flow_id != DPNI_NEW_FLOW_ID)\n+\t\treturn 0;\n+\n+\tmemset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));\n+\tmemset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));\n+\n+\ttc_id = 0;\n+\tflow_id = tx_queue_id;\n+\n+\tret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,\n+\t\t\t tc_id, flow_id, options, &tx_flow_cfg);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Error in setting the tx flow: \"\n+\t\t\t \"tc_id=%d, flow =%d ErrorCode = %x\\n\",\n+\t\t\t tc_id, flow_id, -ret);\n+\t\t\treturn -1;\n+\t}\n+\n+\tdpaa2_q->flow_id = flow_id;\n+\n+\tif (tx_queue_id == 0) {\n+\t\t/*Set tx-conf and error configuration*/\n+\t\tret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,\n+\t\t\t\t\t\t priv->token,\n+\t\t\t\t\t\t DPNI_CONF_DISABLE);\n+\t\tif (ret) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Error in set tx conf mode settings\"\n+\t\t\t\t \" ErrorCode = %x\", ret);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\tdpaa2_q->tc_index = tc_id;\n+\n+\tdev->data->tx_queues[tx_queue_id] = dpaa2_q;\n+\treturn 0;\n+}\n+\n+static void\n+dpaa2_dev_rx_queue_release(void *q __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+}\n+\n+static void\n+dpaa2_dev_tx_queue_release(void *q __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+}\n+\n+static int\n+dpaa2_dev_start(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_eth_dev_data *data = dev->data;\n+\tstruct dpaa2_dev_priv *priv = data->dev_private;\n+\tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n+\tstruct dpni_queue cfg;\n+\tuint16_t qdid;\n+\tstruct dpni_queue_id qid;\n+\tstruct dpaa2_queue *dpaa2_q;\n+\tint ret, i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure %d in enabling dpni %d device\\n\",\n+\t\t\t ret, priv->hw_id);\n+\t\treturn ret;\n+\t}\n+\n+\tret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,\n+\t\t\t DPNI_QUEUE_TX, &qdid);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Error to get qdid:ErrorCode = %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tpriv->qdid = qdid;\n+\n+\tfor (i = 0; i < data->nb_rx_queues; i++) {\n+\t\tdpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];\n+\t\tret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,\n+\t\t\t\t DPNI_QUEUE_RX, dpaa2_q->tc_index,\n+\t\t\t\t dpaa2_q->flow_id, &cfg, &qid);\n+\t\tif (ret) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Error to get flow \"\n+\t\t\t\t \"information Error code = %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tdpaa2_q->fqid = qid.fqid;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * This routine disables all traffic on the adapter by issuing a\n+ * global reset on the MAC.\n+ */\n+static void\n+dpaa2_dev_stop(struct rte_eth_dev *dev)\n+{\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure (ret %d) in disabling dpni %d dev\\n\",\n+\t\t\t ret, priv->hw_id);\n+\t\treturn;\n+\t}\n+}\n+\n+static void\n+dpaa2_dev_close(struct rte_eth_dev *dev)\n+{\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Clean the device first */\n+\tret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure cleaning dpni device with\"\n+\t\t\t \" error code %d\\n\", ret);\n+\t\treturn;\n+\t}\n+}\n+\n+static struct eth_dev_ops dpaa2_ethdev_ops = {\n+\t.dev_configure\t = dpaa2_eth_dev_configure,\n+\t.dev_start\t = dpaa2_dev_start,\n+\t.dev_stop\t = dpaa2_dev_stop,\n+\t.dev_close\t = dpaa2_dev_close,\n+\t.dev_infos_get\t = dpaa2_dev_info_get,\n+\t.rx_queue_setup = dpaa2_dev_rx_queue_setup,\n+\t.rx_queue_release = dpaa2_dev_rx_queue_release,\n+\t.tx_queue_setup = dpaa2_dev_tx_queue_setup,\n+\t.tx_queue_release = dpaa2_dev_tx_queue_release,\n+};\n+\n static int\n dpaa2_dev_init(struct rte_eth_dev *eth_dev)\n {\n+\tstruct rte_device *dev = eth_dev->device;\n+\tstruct rte_dpaa2_device *dpaa2_dev;\n+\tstruct fsl_mc_io *dpni_dev;\n+\tstruct dpni_attr attr;\n+\tstruct dpaa2_dev_priv *priv = eth_dev->data->dev_private;\n+\tint ret, hw_id;\n+\n \tPMD_INIT_FUNC_TRACE();\n \n \t/* For secondary processes, the primary has done all the work */\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\tdpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);\n+\n+\thw_id = dpaa2_dev->object_id;\n+\n+\tdpni_dev = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));\n+\tif (!dpni_dev) {\n+\t\tPMD_INIT_LOG(ERR, \"malloc failed for dpni device\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tdpni_dev->regs = rte_mcp_ptr_list[0];\n+\tret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure in opening dpni@%d device with\"\n+\t\t\t\" error code %d\\n\", hw_id, ret);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Clean the device first */\n+\tret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure cleaning dpni@%d device with\"\n+\t\t\t\" error code %d\\n\", hw_id, ret);\n+\t\treturn -1;\n+\t}\n+\n+\tret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure in getting dpni@%d attribute, \"\n+\t\t\t\" error code %d\\n\", hw_id, ret);\n+\t\treturn -1;\n+\t}\n+\n+\tpriv->num_tc = attr.num_tcs;\n+\tpriv->nb_rx_queues = attr.num_queues;\n+\tpriv->nb_tx_queues = attr.num_queues;\n+\n+\teth_dev->data->nb_rx_queues = priv->nb_rx_queues;\n+\teth_dev->data->nb_tx_queues = priv->nb_tx_queues;\n+\n+\tpriv->hw = dpni_dev;\n+\tpriv->hw_id = hw_id;\n+\tpriv->flags = 0;\n+\n+\tret = dpaa2_alloc_rx_tx_queues(eth_dev);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"dpaa2_alloc_rx_tx_queuesFailed\\n\");\n+\t\treturn -ret;\n+\t}\n+\n+\teth_dev->dev_ops = &dpaa2_ethdev_ops;\n \teth_dev->data->drv_name = rte_dpaa2_pmd.driver.name;\n \n \treturn 0;\n }\n \n static int\n-dpaa2_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused)\n+dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)\n {\n+\tstruct dpaa2_dev_priv *priv = eth_dev->data->dev_private;\n+\tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n+\tint i, ret;\n+\tstruct dpaa2_queue *dpaa2_q;\n+\n \tPMD_INIT_FUNC_TRACE();\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn -EPERM;\n \n+\tif (!dpni) {\n+\t\tPMD_INIT_LOG(WARNING, \"Already closed or not started\");\n+\t\treturn -1;\n+\t}\n+\n+\tdpaa2_dev_close(eth_dev);\n+\n+\tif (priv->rx_vq[0]) {\n+\t\t/* cleaning up queue storage */\n+\t\tfor (i = 0; i < priv->nb_rx_queues; i++) {\n+\t\t\tdpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];\n+\t\t\tif (dpaa2_q->q_storage)\n+\t\t\t\trte_free(dpaa2_q->q_storage);\n+\t\t}\n+\t\t/*free the all queue memory */\n+\t\trte_free(priv->rx_vq[0]);\n+\t\tpriv->rx_vq[0] = NULL;\n+\t}\n+\n+\n+\t/*Close the device at underlying layer*/\n+\tret = dpni_close(dpni, CMD_PRI_LOW, priv->token);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure closing dpni device with\"\n+\t\t\t\" error code %d\\n\", ret);\n+\t}\n+\n+\t/*Free the allocated memory for ethernet private data and dpni*/\n+\tpriv->hw = NULL;\n+\tfree(dpni);\n+\n+\teth_dev->dev_ops = NULL;\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h\nindex 5778780..5f599a7 100644\n--- a/drivers/net/dpaa2/dpaa2_ethdev.h\n+++ b/drivers/net/dpaa2/dpaa2_ethdev.h\n@@ -34,11 +34,26 @@\n #ifndef _DPAA2_ETHDEV_H\n #define _DPAA2_ETHDEV_H\n \n+#include <mc/fsl_dpni.h>\n+#include <mc/fsl_mc_sys.h>\n+\n+#define MAX_RX_QUEUES\t\t16\n+#define MAX_TX_QUEUES\t\t16\n+\n+/*default tc to be used for ,congestion, distribution etc configuration. */\n+#define DPAA2_DEF_TC\t\t0\n+\n struct dpaa2_dev_priv {\n \tvoid *hw;\n \tint32_t hw_id;\n+\tint32_t qdid;\n \tuint16_t token;\n+\tuint8_t nb_tx_queues;\n+\tuint8_t nb_rx_queues;\n+\tvoid *rx_vq[MAX_RX_QUEUES];\n+\tvoid *tx_vq[MAX_TX_QUEUES];\n \n+\tuint8_t num_tc;\n \tuint8_t flags; /*dpaa2 config flags */\n };\n #endif /* _DPAA2_ETHDEV_H */\n", "prefixes": [ "dpdk-dev", "PATCHv6", "18/33" ] }