Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/19812/?format=api
{ "id": 19812, "url": "http://patches.dpdk.org/api/patches/19812/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1484832240-2048-28-git-send-email-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1484832240-2048-28-git-send-email-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1484832240-2048-28-git-send-email-hemant.agrawal@nxp.com", "date": "2017-01-19T13:23:52", "name": "[dpdk-dev,PATCHv5,25/33] net/dpaa2: add packet rx and tx support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "698b184a617f55a0d8b41ab0518323ddc25f655a", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1484832240-2048-28-git-send-email-hemant.agrawal@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/19812/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/19812/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 29E4CFAD2;\n\tThu, 19 Jan 2017 14:26:14 +0100 (CET)", "from NAM01-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam01on0088.outbound.protection.outlook.com [104.47.34.88])\n\tby dpdk.org (Postfix) with ESMTP id B68F9F965\n\tfor <dev@dpdk.org>; Thu, 19 Jan 2017 14:25:38 +0100 (CET)", "from BN3PR03CA0098.namprd03.prod.outlook.com (10.174.66.16) by\n\tMWHPR03MB2478.namprd03.prod.outlook.com (10.169.200.148) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.860.13; Thu, 19 Jan 2017 13:25:36 +0000", "from BN1AFFO11FD008.protection.gbl (2a01:111:f400:7c10::103) by\n\tBN3PR03CA0098.outlook.office365.com (2603:10b6:400:4::16) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.860.13 via Frontend Transport; Thu, 19 Jan 2017 13:25:37 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBN1AFFO11FD008.mail.protection.outlook.com (10.58.52.68) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.803.8\n\tvia Frontend Transport; Thu, 19 Jan 2017 13:25:36 +0000", "from bf-netperf1.idc ([10.232.134.28])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv0JDO4f3015351; Thu, 19 Jan 2017 06:25:33 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com;\n\tnxp.com; \n\tdkim=none (message not signed) header.d=none;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,\n\t<shreyansh.jain@nxp.com>, <john.mcnamara@intel.com>,\n\t<ferruh.yigit@intel.com>, <jerin.jacob@caviumnetworks.com>,\n\tHemant Agrawal <hemant.agrawal@nxp.com>", "Date": "Thu, 19 Jan 2017 18:53:52 +0530", "Message-ID": "<1484832240-2048-28-git-send-email-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1484832240-2048-1-git-send-email-hemant.agrawal@nxp.com>", "References": "<1484679174-4174-1-git-send-email-hemant.agrawal@nxp.com>\n\t<1484832240-2048-1-git-send-email-hemant.agrawal@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131293059366432386;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0; RULEID:(22001);\n\tSRVR:MWHPR03MB2478; ", "X-Microsoft-Antispam-PRVS": "<MWHPR03MB24780F3E4AC163837E46CC9F897E0@MWHPR03MB2478.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197)(275809806118684); ", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(6095060)(601004)(2401047)(13023025)(13017025)(13015025)(13024025)(13018025)(5005006)(8121501046)(3002001)(10201501046)(6055026)(6096035)(20161123561025)(20161123559025)(20161123556025)(20161123563025)(20161123565025);\n\tSRVR:MWHPR03MB2478; BCL:0; PCL:0; RULEID:(400006); SRVR:MWHPR03MB2478;", "X-Forefront-PRVS": "0192E812EC", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Jan 2017 13:25:36.3156\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR03MB2478", "Subject": "[dpdk-dev] [PATCHv5 25/33] net/dpaa2: add packet rx and tx support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 54 +++++++\n drivers/net/dpaa2/Makefile | 1 +\n drivers/net/dpaa2/dpaa2_ethdev.c | 4 +\n drivers/net/dpaa2/dpaa2_ethdev.h | 3 +\n drivers/net/dpaa2/dpaa2_rxtx.c | 260 ++++++++++++++++++++++++++++++++\n 5 files changed, 322 insertions(+)\n create mode 100644 drivers/net/dpaa2/dpaa2_rxtx.c", "diff": "diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\nindex 7c6cc7e..158dfef 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n@@ -43,10 +43,16 @@\n #ifndef true\n #define true 1\n #endif\n+#define lower_32_bits(x) ((uint32_t)(x))\n+#define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))\n \n #ifndef ETH_VLAN_HLEN\n #define ETH_VLAN_HLEN 4 /** < Vlan Header Length */\n #endif\n+\n+#define MAX_TX_RING_SLOTS\t8\n+\t/** <Maximum number of slots available in TX ring*/\n+\n #define DPAA2_DQRR_RING_SIZE\t16\n \t/** <Maximum number of slots available in RX ring*/\n \n@@ -121,6 +127,54 @@ struct dpaa2_queue {\n \n /*! Global MCP list */\n extern void *(*mcp_ptr_list);\n+\n+/* Refer to Table 7-3 in SEC BG */\n+struct qbman_fle {\n+\tuint32_t addr_lo;\n+\tuint32_t addr_hi;\n+\tuint32_t length;\n+\t/* FMT must be 00, MSB is final bit */\n+\tuint32_t fin_bpid_offset;\n+\tuint32_t frc;\n+\tuint32_t reserved[3]; /* Not used currently */\n+};\n+\n+/*Macros to define operations on FD*/\n+#define DPAA2_SET_FD_ADDR(fd, addr) do {\t\t\t\\\n+\tfd->simple.addr_lo = lower_32_bits((uint64_t)(addr));\t\\\n+\tfd->simple.addr_hi = upper_32_bits((uint64_t)(addr));\t\\\n+} while (0)\n+#define DPAA2_SET_FD_LEN(fd, length)\t(fd)->simple.len = length\n+#define DPAA2_SET_FD_BPID(fd, bpid)\t((fd)->simple.bpid_offset |= bpid)\n+#define DPAA2_SET_FD_OFFSET(fd, offset)\t\\\n+\t((fd->simple.bpid_offset |= (uint32_t)(offset) << 16))\n+#define DPAA2_RESET_FD_CTRL(fd)\t(fd)->simple.ctrl = 0\n+\n+#define\tDPAA2_SET_FD_ASAL(fd, asal)\t((fd)->simple.ctrl |= (asal << 16))\n+#define DPAA2_SET_FD_FLC(fd, addr)\tdo { \\\n+\tfd->simple.flc_lo = lower_32_bits((uint64_t)(addr));\t\\\n+\tfd->simple.flc_hi = upper_32_bits((uint64_t)(addr));\t\\\n+} while (0)\n+#define DPAA2_GET_FD_ADDR(fd)\t\\\n+((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))\n+\n+#define DPAA2_GET_FD_LEN(fd)\t((fd)->simple.len)\n+#define DPAA2_GET_FD_BPID(fd)\t(((fd)->simple.bpid_offset & 0x00003FFF))\n+#define DPAA2_GET_FD_OFFSET(fd)\t(((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)\n+#define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \\\n+\t((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size)))\n+\n+#define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)\n+\n+/* Only Enqueue Error responses will be\n+ * pushed on FQID_ERR of Enqueue FQ\n+ */\n+#define DPAA2_EQ_RESP_ERR_FQ\t\t0\n+/* All Enqueue responses will be pushed on address\n+ * set with qbman_eq_desc_set_response\n+ */\n+#define DPAA2_EQ_RESP_ALWAYS\t\t1\n+\n struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);\n void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);\n \ndiff --git a/drivers/net/dpaa2/Makefile b/drivers/net/dpaa2/Makefile\nindex ca51402..5e669df 100644\n--- a/drivers/net/dpaa2/Makefile\n+++ b/drivers/net/dpaa2/Makefile\n@@ -59,6 +59,7 @@ EXPORT_MAP := rte_pmd_dpaa2_version.map\n LIBABIVER := 1\n \n SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += base/dpaa2_hw_dpni.c\n+SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += dpaa2_rxtx.c\n SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += dpaa2_ethdev.c\n \n # library dependencies\ndiff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c\nindex f98e7b8..448aac7 100644\n--- a/drivers/net/dpaa2/dpaa2_ethdev.c\n+++ b/drivers/net/dpaa2/dpaa2_ethdev.c\n@@ -682,6 +682,8 @@\n \teth_dev->dev_ops = &dpaa2_ethdev_ops;\n \teth_dev->data->drv_name = drivername;\n \n+\teth_dev->rx_pkt_burst = dpaa2_dev_rx;\n+\teth_dev->tx_pkt_burst = dpaa2_dev_tx;\n \treturn 0;\n }\n \n@@ -735,6 +737,8 @@\n \tfree(dpni);\n \n \teth_dev->dev_ops = NULL;\n+\teth_dev->rx_pkt_burst = NULL;\n+\teth_dev->tx_pkt_burst = NULL;\n \n \treturn 0;\n }\ndiff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h\nindex a56b525..7196398 100644\n--- a/drivers/net/dpaa2/dpaa2_ethdev.h\n+++ b/drivers/net/dpaa2/dpaa2_ethdev.h\n@@ -77,4 +77,7 @@ int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,\n \n int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);\n \n+uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);\n+uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);\n+\n #endif /* _DPAA2_ETHDEV_H */\ndiff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c\nnew file mode 100644\nindex 0000000..4b76be5\n--- /dev/null\n+++ b/drivers/net/dpaa2/dpaa2_rxtx.c\n@@ -0,0 +1,260 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n+ * Copyright (c) 2016 NXP. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Freescale Semiconductor, Inc nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <time.h>\n+#include <net/if.h>\n+\n+#include <rte_mbuf.h>\n+#include <rte_ethdev.h>\n+#include <rte_malloc.h>\n+#include <rte_memcpy.h>\n+#include <rte_string_fns.h>\n+#include <rte_dev.h>\n+#include <rte_ethdev.h>\n+\n+#include <fslmc_logs.h>\n+#include <fslmc_vfio.h>\n+#include <dpaa2_hw_pvt.h>\n+#include <dpaa2_hw_dpio.h>\n+#include <dpaa2_hw_mempool.h>\n+\n+#include \"dpaa2_ethdev.h\"\n+\n+static inline struct rte_mbuf *__attribute__((hot))\n+eth_fd_to_mbuf(const struct qbman_fd *fd)\n+{\n+\tstruct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(\n+\t\t\tDPAA2_GET_FD_ADDR(fd),\n+\t\t\tbpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);\n+\n+\t/* need to repopulated some of the fields,\n+\t * as they may have changed in last transmission\n+\t */\n+\tmbuf->nb_segs = 1;\n+\tmbuf->ol_flags = 0;\n+\tmbuf->data_off = DPAA2_GET_FD_OFFSET(fd);\n+\tmbuf->data_len = DPAA2_GET_FD_LEN(fd);\n+\tmbuf->pkt_len = mbuf->data_len;\n+\n+\tmbuf->packet_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;\n+\n+\tmbuf->next = NULL;\n+\trte_mbuf_refcnt_set(mbuf, 1);\n+\n+\tPMD_RX_LOG(DEBUG, \"to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,\"\n+\t\t\"fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\\n\",\n+\t\tmbuf, mbuf->buf_addr, mbuf->data_off,\n+\t\tDPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),\n+\t\tbpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,\n+\t\tDPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));\n+\n+\treturn mbuf;\n+}\n+\n+static void __attribute__ ((noinline)) __attribute__((hot))\n+eth_mbuf_to_fd(struct rte_mbuf *mbuf,\n+\t struct qbman_fd *fd, uint16_t bpid)\n+{\n+\t/*Resetting the buffer pool id and offset field*/\n+\tfd->simple.bpid_offset = 0;\n+\n+\tDPAA2_SET_FD_ADDR(fd, (mbuf->buf_addr));\n+\tDPAA2_SET_FD_LEN(fd, mbuf->data_len);\n+\tDPAA2_SET_FD_BPID(fd, bpid);\n+\tDPAA2_SET_FD_OFFSET(fd, mbuf->data_off);\n+\tDPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);\n+\n+\tPMD_TX_LOG(DEBUG, \"mbuf =%p, mbuf->buf_addr =%p, off = %d,\"\n+\t\t\"fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\\n\",\n+\t\tmbuf, mbuf->buf_addr, mbuf->data_off,\n+\t\tDPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),\n+\t\tbpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,\n+\t\tDPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));\n+}\n+\n+uint16_t\n+dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n+{\n+\t/* Function is responsible to receive frames for a given device and VQ*/\n+\tstruct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;\n+\tstruct qbman_result *dq_storage;\n+\tuint32_t fqid = dpaa2_q->fqid;\n+\tint ret, num_rx = 0;\n+\tuint8_t is_last = 0, status;\n+\tstruct qbman_swp *swp;\n+\tconst struct qbman_fd *fd;\n+\tstruct qbman_pull_desc pulldesc;\n+\tstruct rte_eth_dev *dev = dpaa2_q->dev;\n+\n+\tif (unlikely(!DPAA2_PER_LCORE_DPIO)) {\n+\t\tret = dpaa2_affine_qbman_swp();\n+\t\tif (ret) {\n+\t\t\tRTE_LOG(ERR, PMD, \"Failure in affining portal\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\tswp = DPAA2_PER_LCORE_PORTAL;\n+\tdq_storage = dpaa2_q->q_storage->dq_storage[0];\n+\n+\tqbman_pull_desc_clear(&pulldesc);\n+\tqbman_pull_desc_set_numframes(&pulldesc,\n+\t\t\t\t (nb_pkts > DPAA2_DQRR_RING_SIZE) ?\n+\t\t\t\t DPAA2_DQRR_RING_SIZE : nb_pkts);\n+\tqbman_pull_desc_set_fq(&pulldesc, fqid);\n+\t/* todo optimization - we can have dq_storage_phys available*/\n+\tqbman_pull_desc_set_storage(&pulldesc, dq_storage,\n+\t\t\t(dma_addr_t)(dq_storage), 1);\n+\n+\t/*Issue a volatile dequeue command. */\n+\twhile (1) {\n+\t\tif (qbman_swp_pull(swp, &pulldesc)) {\n+\t\t\tPMD_RX_LOG(ERR, \"VDQ command is not issued.\"\n+\t\t\t\t \"QBMAN is busy\\n\");\n+\t\t\t/* Portal was busy, try again */\n+\t\t\tcontinue;\n+\t\t}\n+\t\tbreak;\n+\t};\n+\n+\t/* Receive the packets till Last Dequeue entry is found with\n+\t * respect to the above issues PULL command.\n+\t */\n+\twhile (!is_last) {\n+\t\tstruct rte_mbuf *mbuf;\n+\t\t/*Check if the previous issued command is completed.\n+\t\t * Also seems like the SWP is shared between the\n+\t\t * Ethernet Driver and the SEC driver.\n+\t\t */\n+\t\twhile (!qbman_check_command_complete(swp, dq_storage))\n+\t\t\t;\n+\t\t/* Loop until the dq_storage is updated with\n+\t\t * new token by QBMAN\n+\t\t */\n+\t\twhile (!qbman_result_has_new_result(swp, dq_storage))\n+\t\t\t;\n+\t\t/* Check whether Last Pull command is Expired and\n+\t\t * setting Condition for Loop termination\n+\t\t */\n+\t\tif (qbman_result_DQ_is_pull_complete(dq_storage)) {\n+\t\t\tis_last = 1;\n+\t\t\t/* Check for valid frame. */\n+\t\t\tstatus = (uint8_t)qbman_result_DQ_flags(dq_storage);\n+\t\t\tif (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))\n+\t\t\t\tcontinue;\n+\t\t}\n+\n+\t\tfd = qbman_result_DQ_fd(dq_storage);\n+\t\tmbuf = (struct rte_mbuf *)(DPAA2_GET_FD_ADDR(fd)\n+\t\t\t - bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);\n+\t\t/* Prefeth mbuf */\n+\t\trte_prefetch0(mbuf);\n+\t\t/* Prefetch Annotation address for the parse results */\n+\t\trte_prefetch0((void *)((uint64_t)DPAA2_GET_FD_ADDR(fd)\n+\t\t\t\t\t\t+ DPAA2_FD_PTA_SIZE + 16));\n+\n+\t\tbufs[num_rx] = eth_fd_to_mbuf(fd);\n+\t\tbufs[num_rx]->port = dev->data->port_id;\n+\n+\t\tnum_rx++;\n+\t\tdq_storage++;\n+\t} /* End of Packet Rx loop */\n+\n+\tdpaa2_q->rx_pkts += num_rx;\n+\n+\t/*Return the total number of packets received to DPAA2 app*/\n+\treturn num_rx;\n+}\n+\n+/*\n+ * Callback to handle sending packets through WRIOP based interface\n+ */\n+uint16_t\n+dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n+{\n+\t/* Function to transmit the frames to given device and VQ*/\n+\tuint32_t loop;\n+\tint32_t ret;\n+\tstruct qbman_fd fd_arr[MAX_TX_RING_SLOTS];\n+\tuint32_t frames_to_send;\n+\tstruct rte_mempool *mp;\n+\tstruct qbman_eq_desc eqdesc;\n+\tstruct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;\n+\tstruct qbman_swp *swp;\n+\tuint16_t num_tx = 0;\n+\tuint16_t bpid;\n+\tstruct rte_eth_dev *dev = dpaa2_q->dev;\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\n+\tif (unlikely(!DPAA2_PER_LCORE_DPIO)) {\n+\t\tret = dpaa2_affine_qbman_swp();\n+\t\tif (ret) {\n+\t\t\tRTE_LOG(ERR, PMD, \"Failure in affining portal\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\tswp = DPAA2_PER_LCORE_PORTAL;\n+\n+\tPMD_TX_LOG(DEBUG, \"===> dev =%p, fqid =%d\", dev, dpaa2_q->fqid);\n+\n+\t/*Prepare enqueue descriptor*/\n+\tqbman_eq_desc_clear(&eqdesc);\n+\tqbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);\n+\tqbman_eq_desc_set_response(&eqdesc, 0, 0);\n+\tqbman_eq_desc_set_qd(&eqdesc, priv->qdid,\n+\t\t\t dpaa2_q->flow_id, dpaa2_q->tc_index);\n+\n+\t/*Clear the unused FD fields before sending*/\n+\twhile (nb_pkts) {\n+\t\tframes_to_send = (nb_pkts >> 3) ? MAX_TX_RING_SLOTS : nb_pkts;\n+\n+\t\tfor (loop = 0; loop < frames_to_send; loop++) {\n+\t\t\tfd_arr[loop].simple.frc = 0;\n+\t\t\tDPAA2_RESET_FD_CTRL((&fd_arr[loop]));\n+\t\t\tDPAA2_SET_FD_FLC((&fd_arr[loop]), NULL);\n+\t\t\tmp = (*bufs)->pool;\n+\t\t\tbpid = mempool_to_bpid(mp);\n+\t\t\teth_mbuf_to_fd(*bufs, &fd_arr[loop], bpid);\n+\t\t\tbufs++;\n+\t\t}\n+\t\tloop = 0;\n+\t\twhile (loop < frames_to_send) {\n+\t\t\tloop += qbman_swp_send_multiple(swp, &eqdesc,\n+\t\t\t\t\t&fd_arr[loop], frames_to_send - loop);\n+\t\t}\n+\n+\t\tnum_tx += frames_to_send;\n+\t\tdpaa2_q->tx_pkts += frames_to_send;\n+\t\tnb_pkts -= frames_to_send;\n+\t}\n+\treturn num_tx;\n+}\n", "prefixes": [ "dpdk-dev", "PATCHv5", "25/33" ] }